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Add Xilinx dist RAM as comb boxes

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This commit is contained in:
Eddie Hung 2019-06-24 21:54:01 -07:00
parent 49a762ba46
commit 152e682bd5
2 changed files with 16 additions and 0 deletions
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14
techlibs/xilinx/abc_xc7.box
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@ -29,3 +29,17 @@ CARRY4 3 1 10 8
494 465 445 - - 433 469 - - 157
592 540 520 356 - 512 548 292 - 228
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# SLICEM/A6LUT
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
# Outputs: DPO SPO
RAM64X1D 4 0 15 2
- - - - - - - 124 124 124 124 124 124 - -
124 124 124 124 124 124 - - - - - - 124 - -
# SLICEM/A6LUT + F7[AB]MUX
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
# Outputs: DPO SPO
RAM128X1D 5 0 17 2
- - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - -