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Fix #1462, #1480.

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Marcin Kościelnicki 2019-11-18 08:19:53 +01:00 • committed by Marcin Kościelnicki
parent 7a9081440c
commit 15232a48af
4 changed files with 40 additions and 9 deletions
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11
tests/various/bug1462.ys Normal file
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@ -0,0 +1,11 @@
read_verilog << EOF
module top(...);
input wire [31:0] A;
output wire [31:0] P;
assign P = A * 32'h12300000;
endmodule
EOF
synth_xilinx