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Fix #1462, #1480.

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Marcin Kościelnicki 2019-11-18 08:19:53 +01:00 • committed by Marcin Kościelnicki
parent 7a9081440c
commit 15232a48af
4 changed files with 40 additions and 9 deletions
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8
passes/pmgen/xilinx_dsp_CREG.pmg
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@ -63,12 +63,12 @@ code sigC sigP clock
if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
// Only care about those bits that are used
int i;
for (i = 0; i < GetSize(P); i++) {
if (nusers(P[i]) <= 1)
for (i = GetSize(P)-1; i >= 0; i--)
if (nusers(P[i]) > 1)
break;
sigP.append(P[i]);
}
i++;
log_assert(nusers(P.extract_end(i)) <= 1);
sigP = P.extract(0, i);
}
else
sigP = P;