From 151be52500ebc0195545370a7e72542648f28937 Mon Sep 17 00:00:00 2001
From: Alain Dargelas <alain@silimate.com>
Date: Thu, 17 Oct 2024 11:02:35 -0700
Subject: [PATCH] Activity clear pass

---
 passes/cmds/activity.cc | 43 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)

diff --git a/passes/cmds/activity.cc b/passes/cmds/activity.cc
index efac64cb9..2940bad2a 100644
--- a/passes/cmds/activity.cc
+++ b/passes/cmds/activity.cc
@@ -126,6 +126,22 @@ struct ActivityProp {
 	}
 };
 
+struct ActivityClear {
+	Module *module;
+
+	ActivityClear(Module *module) : module(module)
+	{
+		for (Wire *wire : module->wires()) {
+			wire->set_string_attribute("$ACKT", "");
+			wire->set_string_attribute("$DUTY", "");
+		}
+		for (auto cell : module->cells()) {
+			cell->set_string_attribute("$ACKT:", "");
+			cell->set_string_attribute("$DUTY:", "");
+		}
+	}
+};
+
 struct ActivityPropPass : public Pass {
 	ActivityPropPass() : Pass("activity_prop", "Attaches wire activity to cell ports") {}
 	void help() override
@@ -152,4 +168,31 @@ struct ActivityPropPass : public Pass {
 	}
 } ActivityPropPass;
 
+struct ActivityClearPass : public Pass {
+	ActivityClearPass() : Pass("activity_clear", "Clears activity attached to cells and wires") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    activity_clear\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing Activity clearing pass\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// No options currently. When adding in the future make sure to update docstring with [options]
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->modules()) {
+			ActivityClear worker(module);
+		}
+	}
+} ActivityClearPass;
+
+
 PRIVATE_NAMESPACE_END