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Docs: Adding mux cell descriptions

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Also making ver2 cell descriptions consistently spaced.
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Krystine Sherwin 2024-10-15 07:11:56 +13:00
parent dfe803b5c6
commit 1513366f21
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1 changed files with 14 additions and 13 deletions
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27
techlibs/common/simlib.v
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@ -32,7 +32,6 @@
*/ */
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Bit-wise inverter //* title Bit-wise inverter
//* group unary //* group unary
@ -526,14 +525,12 @@ endgenerate
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Variable shifter //* title Variable shifter
//* group binary //* group binary
//- Performs a right logical shift if the second operand is positive (or //- Performs a right logical shift if the second operand is positive (or
//- unsigned), and a left logical shift if it is negative. //- unsigned), and a left logical shift if it is negative.
//- //-
module \$shift (A, B, Y); module \$shift (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
@ -565,14 +562,12 @@ endgenerate
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Indexed part-select //* title Indexed part-select
//* group binary //* group binary
//* tags x-output //* tags x-output
//- Same as the `$shift` cell, but fills with 'x'. //- Same as the `$shift` cell, but fills with 'x'.
//- //-
module \$shiftx (A, B, Y); module \$shiftx (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
@ -649,7 +644,6 @@ end
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Arithmetic logic unit //* title Arithmetic logic unit
//* group arith //* group arith
@ -839,7 +833,6 @@ endgenerate
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Case equality //* title Case equality
//* group binary //* group binary
@ -873,7 +866,6 @@ endgenerate
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Case inequality //* title Case inequality
//* group binary //* group binary
@ -1215,7 +1207,6 @@ end
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Divider //* title Divider
//* group binary //* group binary
@ -1246,7 +1237,6 @@ endgenerate
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Modulo //* title Modulo
//* group binary //* group binary
@ -1544,8 +1534,12 @@ assign Y = S ? B : A;
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2
//* title Binary-encoded multiplexer
//* group mux //* group mux
//- Selects between 'slices' of A where each value of S corresponds to a unique
//- slice.
//-
module \$bmux (A, S, Y); module \$bmux (A, S, Y);
parameter WIDTH = 0; parameter WIDTH = 0;
@ -1572,9 +1566,13 @@ endgenerate
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2
//* title Priority-encoded multiplexer
//* group mux //* group mux
//* tags x-output //* tags x-output
//- Selects between 'slices' of B where each slice corresponds to a single bit
//- of S. Outputs A when all bits of S are low.
//-
module \$pmux (A, B, S, Y); module \$pmux (A, B, S, Y);
parameter WIDTH = 0; parameter WIDTH = 0;
@ -1881,7 +1879,6 @@ endspecify
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2 //* ver 2
//* title Bit-wise case equality //* title Bit-wise case equality
//* group binary //* group binary
@ -1905,7 +1902,11 @@ endgenerate
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------
//* ver 2
//* title Bit-wise multiplexer
//* group mux //* group mux
//- Equivalent to a series of 1-bit wide `$mux` cells.
//-
module \$bwmux (A, B, S, Y); module \$bwmux (A, B, S, Y);
parameter WIDTH = 0; parameter WIDTH = 0;