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This commit is contained in:
Eddie Hung 2019-11-26 22:41:35 -08:00
parent a30d5e1cc3
commit 15042eaf57
1 changed files with 0 additions and 9 deletions
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9
tests/simple_abc9/abc9.v
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@ -218,12 +218,6 @@ module MUXF8(input I0, I1, S, output O);
endmodule endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet // Citation: https://github.com/alexforencich/verilog-ethernet
// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q
// returns before b4321a31
// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no
// driver.
// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no
// driver.
module abc9_test022 module abc9_test022
( (
input wire clk, input wire clk,
@ -237,9 +231,6 @@ module abc9_test022
endmodule endmodule
// Citation: https://github.com/riscv/riscv-bitmanip // Citation: https://github.com/riscv/riscv-bitmanip
// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q
// returns before 14233843
// Warning: Wire abc9_test023.\dout [1] is used but has no driver.
module abc9_test023 #( module abc9_test023 #(
parameter integer N = 2, parameter integer N = 2,
parameter integer M = 2 parameter integer M = 2