diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 8add396f7..9f01ad944 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -257,8 +257,11 @@ struct SimInstance
 
 			if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
 				fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
-				if (id==0 && wire->name.isPublic())
+				if (id==0 && wire->name.isPublic()) {
 					log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)));
+				} else {
+					log("Found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)));
+				}
 				fst_handles[wire] = id;
 			}
 
diff --git a/passes/silimate/Makefile.inc b/passes/silimate/Makefile.inc
index 0dec65cad..9de3e0204 100644
--- a/passes/silimate/Makefile.inc
+++ b/passes/silimate/Makefile.inc
@@ -10,6 +10,7 @@ OBJS += passes/silimate/lut2bmux.o
 OBJS += passes/silimate/obs_clean.o
 OBJS += passes/silimate/opt_balance_tree.o
 OBJS += passes/silimate/reg_rename.o
+OBJS += passes/silimate/reg_width.o
 OBJS += passes/silimate/segv.o
 OBJS += passes/silimate/splitfanout.o
 OBJS += passes/silimate/splitlarge.o
diff --git a/passes/silimate/reg_width.cc b/passes/silimate/reg_width.cc
new file mode 100644
index 000000000..19a58fd6f
--- /dev/null
+++ b/passes/silimate/reg_width.cc
@@ -0,0 +1,67 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *                2026  Stan Lee          <stan@silimate.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+ #include "kernel/yosys.h"
+ #include <regex>
+ 
+ USING_YOSYS_NAMESPACE
+ PRIVATE_NAMESPACE_BEGIN
+ 
+ struct RegWidthPass : public Pass {
+	 RegWidthPass() : Pass("reg_width", "annotates multi-bit registers with their width") { }
+	 void help() override
+	 {
+		 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		 log("\n");
+		 log("    reg_width\n");
+		 log("\n");
+	 }
+	 void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	 {
+		 log_header(design, "Executing reg_width pass\n");
+ 
+		 size_t argidx;
+		 for (argidx = 1; argidx < args.size(); argidx++) {
+			 // No options currently. When adding in the future make sure to update docstring with [options]
+			 break;
+		 }
+		 extra_args(args, argidx, design);
+ 
+			// Data structure used to keep track of multi-bit registers.
+			// Relevant for correct register annotation.
+			for (auto module : design->selected_modules()) {
+				log("Processing module %s\n", module->name.c_str());
+				for (auto cell : module->selected_cells()) {
+					if (cell->name.ends_with("_reg")) {
+						std::string width = std::to_string(cell->getParam(ID::WIDTH).as_int());
+						if (width != "1") { // only care about multi-bit registers
+							cell->set_string_attribute("$ORIG_REG_WIDTH", width);
+							log("Annotating register %s with width %s\n", cell->name.c_str(), width);
+						}
+					}
+				}
+			}
+
+		 log_flush();
+	 }
+ } RegWidthPass;
+ 
+ PRIVATE_NAMESPACE_END
+ 
\ No newline at end of file