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Parser changes to support typedef.
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parent
f828cb5132
commit
14f32028ec
4 changed files with 88 additions and 10 deletions
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@ -47,6 +47,22 @@ static void error_on_dpi_function(AST::AstNode *node)
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error_on_dpi_function(child);
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}
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static void add_package_types(std::map<std::string, AST::AstNode *> &user_types, std::vector<AST::AstNode *> &package_list)
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{
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// prime the parser's user type lookup table with the package qualified names
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// of typedefed names in the packages seen so far.
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user_types.clear();
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for (const auto &pkg : package_list) {
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log_assert(pkg->type==AST::AST_PACKAGE);
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for (const auto &node: pkg->children) {
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if (node->type == AST::AST_TYPEDEF) {
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std::string s = pkg->str + "::" + node->str.substr(1);
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user_types[s] = node;
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}
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}
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}
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}
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struct VerilogFrontend : public Frontend {
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VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
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void help() YS_OVERRIDE
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@ -468,6 +484,9 @@ struct VerilogFrontend : public Frontend {
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AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
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flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
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// make latest package info available to next parser
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add_package_types(pkg_user_types, design->verilog_packages);
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if (!flag_nopp)
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delete lexin;
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