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Added Altera Cyclon III cell library to xsthammer

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This commit is contained in:
Clifford Wolf 2013-07-04 14:50:03 +02:00
parent a4fd3cde8c
commit 14c84c111b
3 changed files with 115 additions and 14 deletions
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2
tests/xsthammer/Makefile
View file

@ -14,7 +14,7 @@ check_vivado/%.log: rtl/%.v vivado/%.v
bash run-check.sh -vivado $(notdir $(basename $<))
check_quartus/%.log: rtl/%.v quartus/%.v
# bash run-check.sh -quartus $(notdir $(basename $<))
bash run-check.sh -quartus $(notdir $(basename $<))
xst/%.v: rtl/%.v
bash run-xst.sh $(notdir $(basename $<))

86
tests/xsthammer/cy_cells.v Normal file
View file

@ -0,0 +1,86 @@
// Based on the simulation models from /opt/altera/13.0/quartus/eda/sim_lib/cycloneiii_atoms.v
module cycloneiii_lcell_comb (dataa, datab, datac, datad, cin, combout, cout);
input dataa, datab, datac, datad, cin;
output combout, cout;
parameter lut_mask = 16'hFFFF;
parameter sum_lutc_input = "datac";
parameter dont_touch = "off";
parameter lpm_type = "cycloneiii_lcell_comb";
reg cout_tmp, combout_tmp;
reg [1:0] isum_lutc_input;
// 4-input LUT function
function lut4;
input [15:0] mask;
input dataa, datab, datac, datad;
begin
lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
: ( dataa ? mask[13] : mask[12]))
: ( datab ? ( dataa ? mask[11] : mask[10])
: ( dataa ? mask[ 9] : mask[ 8])))
: ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
: ( dataa ? mask[ 5] : mask[ 4]))
: ( datab ? ( dataa ? mask[ 3] : mask[ 2])
: ( dataa ? mask[ 1] : mask[ 0])));
end
endfunction
initial
if (sum_lutc_input == "datac")
isum_lutc_input = 0;
else if (sum_lutc_input == "cin")
isum_lutc_input = 1;
else
isum_lutc_input = 2;
always @* begin
if (isum_lutc_input == 0) // datac
combout_tmp = lut4(lut_mask, dataa, datab, datac, datad);
else if (isum_lutc_input == 1) // cin
combout_tmp = lut4(lut_mask, dataa, datab, cin, datad);
cout_tmp = lut4(lut_mask, dataa, datab, cin, 'b0);
end
assign combout = combout_tmp;
assign cout = cout_tmp;
endmodule
// ----------------------------------------------------------------------
module cycloneiii_io_ibuf (i, ibar, o);
parameter differential_mode = "false";
parameter bus_hold = "false";
parameter simulate_z_as = "Z";
parameter lpm_type = "cycloneiii_io_ibuf";
input i, ibar;
output o;
assign o = i;
endmodule
// ----------------------------------------------------------------------
module cycloneiii_io_obuf (i, oe, seriesterminationcontrol, devoe, o, obar);
parameter open_drain_output = "false";
parameter bus_hold = "false";
parameter lpm_type = "cycloneiii_io_obuf";
input i, oe, devoe;
input [15:0] seriesterminationcontrol;
output o, obar;
assign o = i;
assign obar = ~i;
endmodule

41
tests/xsthammer/run-check.sh
View file

@ -1,6 +1,7 @@
#!/bin/bash
use_vivado=false
use_quartus=false
checkdir="check"
if [ "$1" = "-vivado" ]; then
@ -9,6 +10,12 @@ if [ "$1" = "-vivado" ]; then
shift
fi
if [ "$1" = "-quartus" ]; then
use_quartus=true
checkdir="check_quartus"
shift
fi
if [ $# -eq 0 ]; then
echo "Usage: $0 <job_id>" >&2
exit 1
@ -22,21 +29,23 @@ mkdir -p $checkdir check_temp/$job
cd check_temp/$job
{
echo "module ${job}_top(a, b, y_rtl, y_xst);"
sed -r '/^(input|output) / !d; /output/ { s/ y;/ y_rtl;/; p; }; s/ y_rtl;/ y_xst;/;' ../../rtl/$job.v
echo "module ${job}_top(a, b, y_rtl, y_syn);"
sed -r '/^(input|output) / !d; /output/ { s/ y;/ y_rtl;/; p; }; s/ y_rtl;/ y_syn;/;' ../../rtl/$job.v
echo "${job}_rtl rtl_variant (.a(a), .b(b), .y(y_rtl));"
echo "${job}_xst xst_variant (.a(a), .b(b), .y(y_xst));"
echo "${job}_syn syn_variant (.a(a), .b(b), .y(y_syn));"
echo "endmodule"
} > ${job}_top.v
for mode in nomap techmap; do
{
if $use_vivado; then
if $use_quartus; then
echo "read_verilog ../../quartus/$job.v"
elif $use_vivado; then
echo "read_verilog ../../vivado/$job.v"
else
echo "read_verilog -DGLBL ../../xst/$job.v"
fi
echo "rename $job ${job}_xst"
echo "rename $job ${job}_syn"
echo "read_verilog ../../rtl/$job.v"
echo "rename $job ${job}_rtl"
@ -45,18 +54,24 @@ for mode in nomap techmap; do
fi
echo "read_verilog ${job}_top.v"
echo "read_verilog ../../xl_cells.v"
if $use_quartus; then
echo "read_verilog ../../cy_cells.v"
else
echo "read_verilog ../../xl_cells.v"
fi
echo "hierarchy -top ${job}_top"
echo "flatten ${job}_xst"
echo "proc"
echo "flatten ${job}_syn"
echo "flatten ${job}_rtl"
echo "flatten ${job}_top"
echo "opt_clean"
echo "rename ${job}_xst ${job}_xst_${mode}"
echo "rename ${job}_syn ${job}_syn_${mode}"
echo "rename ${job}_rtl ${job}_rtl_${mode}"
echo "rename ${job}_top ${job}_top_${mode}"
echo "dump -outfile ${job}_top_${mode}.il ${job}_xst_${mode} ${job}_rtl_${mode} ${job}_top_${mode}"
echo "dump -outfile ${job}_top_${mode}.il ${job}_syn_${mode} ${job}_rtl_${mode} ${job}_top_${mode}"
} > ${job}_top_${mode}.ys
../../../../yosys -q ${job}_top_${mode}.ys
done
@ -64,11 +79,11 @@ done
{
echo "read_ilang ${job}_top_nomap.il"
echo "read_ilang ${job}_top_techmap.il"
echo "sat -timeout 60 -verify-no-timeout -show a,b,y_rtl,y_xst -prove y_rtl y_xst ${job}_top_nomap"
echo "sat -timeout 60 -verify-no-timeout -show a,b,y_rtl,y_xst -prove y_rtl y_xst ${job}_top_techmap"
echo "sat -timeout 60 -verify-no-timeout -show a,b,y_rtl,y_syn -prove y_rtl y_syn ${job}_top_nomap"
echo "sat -timeout 60 -verify-no-timeout -show a,b,y_rtl,y_syn -prove y_rtl y_syn ${job}_top_techmap"
if [[ $job != expression_* ]]; then
echo "eval -brute_force_equiv_checker ${job}_rtl_nomap ${job}_xst_nomap"
echo "eval -brute_force_equiv_checker ${job}_rtl_techmap ${job}_xst_techmap"
echo "eval -brute_force_equiv_checker ${job}_rtl_nomap ${job}_syn_nomap"
echo "eval -brute_force_equiv_checker ${job}_rtl_techmap ${job}_syn_techmap"
fi
} > ${job}_cmp.ys