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Merge pull request #1304 from YosysHQ/eddie/abc9_refactor

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Refactor abc9 to use port attributes, not module attributes
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Eddie Hung 2019-08-20 11:59:31 -07:00 • committed by GitHub
commit 14c03861b6
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6 changed files with 138 additions and 104 deletions
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10
techlibs/ice40/cells_sim.v
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@ -141,8 +141,14 @@ module SB_CARRY (output CO, input I0, I1, CI);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule
(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI);
(* abc_box_id = 1, lib_whitebox *)
module \$__ICE40_FULL_ADDER (
(* abc_carry *) output CO,
output O,
input A,
input B,
(* abc_carry *) input CI
);
SB_CARRY carry (
.I0(A),
.I1(B),