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Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
Refactor abc9 to use port attributes, not module attributes
This commit is contained in:
Eddie Hung
GitHub
commit
14c03861b6
6 changed files with 138 additions and 104 deletions
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@ -76,12 +76,11 @@ inline std::string remap_name(RTLIL::IdString abc_name)
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return stringf("$abc$%d$%s", map_autoidx, abc_name.c_str()+1);
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}
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void handle_loops(RTLIL::Design *design)
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void handle_loops(RTLIL::Design *design,
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const dict<IdString,pool<IdString>> &scc_break_inputs)
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{
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Pass::call(design, "scc -set_attr abc_scc_id {}");
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dict<IdString, vector<IdString>> abc_scc_break;
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// For every unique SCC found, (arbitrarily) find the first
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// cell in the component, and select (and mark) all its output
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// wires
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@ -116,44 +115,29 @@ void handle_loops(RTLIL::Design *design)
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cell->attributes.erase(it);
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}
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auto jt = abc_scc_break.find(cell->type);
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if (jt == abc_scc_break.end()) {
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std::vector<IdString> ports;
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RTLIL::Module* box_module = design->module(cell->type);
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if (box_module) {
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auto ports_csv = box_module->attributes.at(ID(abc_scc_break), RTLIL::Const::from_string("")).decode_string();
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for (const auto &port_name : split_tokens(ports_csv, ",")) {
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auto port_id = RTLIL::escape_id(port_name);
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auto kt = cell->connections_.find(port_id);
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if (kt == cell->connections_.end())
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log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", port_name.c_str(), log_id(box_module));
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ports.push_back(port_id);
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auto jt = scc_break_inputs.find(cell->type);
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if (jt != scc_break_inputs.end())
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for (auto port_name : jt->second) {
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RTLIL::SigSpec sig;
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auto &rhs = cell->connections_.at(port_name);
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for (auto b : rhs) {
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Wire *w = b.wire;
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if (!w) continue;
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w->port_output = true;
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w->set_bool_attribute(ID(abc_scc_break));
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w = module->wire(stringf("%s.abci", w->name.c_str()));
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if (!w) {
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w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
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w->port_input = true;
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}
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else {
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log_assert(b.offset < GetSize(w));
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log_assert(w->port_input);
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}
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sig.append(RTLIL::SigBit(w, b.offset));
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}
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rhs = sig;
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}
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jt = abc_scc_break.insert(std::make_pair(cell->type, std::move(ports))).first;
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}
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for (auto port_name : jt->second) {
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RTLIL::SigSpec sig;
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auto &rhs = cell->connections_.at(port_name);
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for (auto b : rhs) {
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Wire *w = b.wire;
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if (!w) continue;
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w->port_output = true;
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w->set_bool_attribute(ID(abc_scc_break));
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w = module->wire(stringf("%s.abci", w->name.c_str()));
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if (!w) {
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w = module->addWire(stringf("%s.abci", b.wire->name.c_str()), GetSize(b.wire));
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w->port_input = true;
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}
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else {
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log_assert(b.offset < GetSize(w));
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log_assert(w->port_input);
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}
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sig.append(RTLIL::SigBit(w, b.offset));
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}
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rhs = sig;
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}
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}
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module->fixup_ports();
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@ -288,7 +272,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
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bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
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bool show_tempdir, std::string box_file, std::string lut_file,
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std::string wire_delay, const dict<int,IdString> &box_lookup)
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std::string wire_delay, const dict<int,IdString> &box_lookup,
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const dict<IdString,pool<IdString>> &scc_break_inputs
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)
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{
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module = current_module;
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map_autoidx = autoidx++;
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@ -427,7 +413,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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RTLIL::Selection& sel = design->selection_stack.back();
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sel.select(module);
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handle_loops(design);
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handle_loops(design, scc_break_inputs);
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Pass::call(design, "aigmap");
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@ -1081,6 +1067,7 @@ struct Abc9Pass : public Pass {
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extra_args(args, argidx, design);
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dict<int,IdString> box_lookup;
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dict<IdString,pool<IdString>> scc_break_inputs;
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for (auto m : design->modules()) {
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auto it = m->attributes.find(ID(abc_box_id));
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if (it == m->attributes.end())
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@ -1093,6 +1080,56 @@ struct Abc9Pass : public Pass {
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log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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log_assert(r.second);
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RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
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for (auto p : m->ports) {
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auto w = m->wire(p);
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log_assert(w);
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if (w->port_input) {
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if (w->attributes.count(ID(abc_scc_break)))
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scc_break_inputs[m->name].insert(p);
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if (w->attributes.count(ID(abc_carry))) {
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if (carry_in)
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log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
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carry_in = w;
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}
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}
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if (w->port_output) {
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if (w->attributes.count(ID(abc_carry))) {
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if (carry_out)
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log_error("Module '%s' contains more than one 'abc_carry' input port.\n", log_id(m));
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carry_out = w;
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}
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}
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}
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if (carry_in || carry_out) {
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if (carry_in && !carry_out)
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log_error("Module '%s' contains an 'abc_carry' input port but no output port.\n", log_id(m));
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if (!carry_in && carry_out)
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log_error("Module '%s' contains an 'abc_carry' output port but no input port.\n", log_id(m));
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// Make carry_in the last PI, and carry_out the last PO
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// since ABC requires it this way
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auto &ports = m->ports;
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for (auto it = ports.begin(); it != ports.end(); ) {
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RTLIL::Wire* w = m->wire(*it);
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log_assert(w);
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if (w == carry_in || w == carry_out) {
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it = ports.erase(it);
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continue;
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}
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if (w->port_id > carry_in->port_id)
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--w->port_id;
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if (w->port_id > carry_out->port_id)
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--w->port_id;
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log_assert(w->port_input || w->port_output);
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log_assert(ports[w->port_id-1] == w->name);
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++it;
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}
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ports.push_back(carry_in->name);
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carry_in->port_id = ports.size();
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ports.push_back(carry_out->name);
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carry_out->port_id = ports.size();
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}
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}
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for (auto mod : design->selected_modules())
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@ -1110,7 +1147,7 @@ struct Abc9Pass : public Pass {
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if (!dff_mode || !clk_str.empty()) {
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abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
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delay_target, lutin_shared, fast_mode, show_tempdir,
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box_file, lut_file, wire_delay, box_lookup);
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box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
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continue;
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}
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@ -1256,7 +1293,7 @@ struct Abc9Pass : public Pass {
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en_sig = assign_map(std::get<3>(it.first));
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abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
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keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
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box_file, lut_file, wire_delay, box_lookup);
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box_file, lut_file, wire_delay, box_lookup, scc_break_inputs);
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assign_map.set(mod);
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}
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}
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