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yosys-smtbmc meminit support
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parent
209a3d9ffc
commit
14bfd3c5c1
4 changed files with 52 additions and 5 deletions
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@ -736,6 +736,26 @@ struct Smt2Worker
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std::string expr_d = stringf("(|%s#%d#%d| state)", get_id(module), arrayid, wr_ports);
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std::string expr_q = stringf("(|%s#%d#0| next_state)", get_id(module), arrayid);
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trans.push_back(stringf(" (= %s %s) ; %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell)));
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Const init_data = cell->getParam("\\INIT");
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int memsize = cell->getParam("\\SIZE").as_int();
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for (int i = 0; i < memsize; i++)
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{
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if (GetSize(init_data) < i*width)
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break;
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Const initword = init_data.extract(i*width, width, State::Sx);
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bool gen_init_constr = false;
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for (auto bit : initword.bits)
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if (bit == State::S0 || bit == State::S1)
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gen_init_constr = true;
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init_list.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
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get_id(module), arrayid, Const(i, abits).as_string().c_str(),
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initword.as_string().c_str(), get_id(cell), i));
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}
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}
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}
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}
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@ -864,8 +884,8 @@ struct Smt2Backend : public Backend {
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log(" this will print the recursive walk used to export the modules.\n");
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log("\n");
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log(" -nobv\n");
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log(" disable support for BitVec (FixedSizeBitVectors theory). with this\n");
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log(" option set multi-bit wires are represented using the BitVec sort and\n");
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log(" disable support for BitVec (FixedSizeBitVectors theory). without this\n");
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log(" option multi-bit wires are represented using the BitVec sort and\n");
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log(" support for coarse grain cells (incl. arithmetic) is enabled.\n");
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log("\n");
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log(" -nomem\n");
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@ -878,7 +898,7 @@ struct Smt2Backend : public Backend {
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log("\n");
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log(" -wires\n");
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log(" create '<mod>_n' functions for all public wires. by default only ports,\n");
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log(" registers, and wires with the 'keep' attribute set are exported.\n");
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log(" registers, and wires with the 'keep' attribute are exported.\n");
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log("\n");
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log(" -tpl <template_file>\n");
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log(" use the given template file. the line containing only the token '%%%%'\n");
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