mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

improved (fixed) conversion of real values to bit vectors

Browse source
This commit is contained in:
Clifford Wolf 2014-06-14 20:38:05 +02:00
parent 39eb347c67
commit 149fe83a8d
4 changed files with 30 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

18
frontends/ast/ast.cc
View file

@ -794,6 +794,24 @@ double AstNode::asReal(bool is_signed)
log_abort();
}
RTLIL::Const AstNode::realAsConst(int width)
{
double v = round(realvalue);
RTLIL::Const result;
if (!isfinite(v)) {
result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
} else {
bool is_negative = v < 0;
if (is_negative)
v *= -1;
for (int i = 0; i < width; i++, v /= 2)
result.bits.push_back((int(v) & 1) ? RTLIL::State::S1 : RTLIL::State::S0);
if (is_negative)
result = const_neg(result, result, false, false, result.bits.size());
}
return result;
}
// create a new AstModule from an AST_MODULE AST node
static AstModule* process_module(AstNode *ast, bool defer)
{

1
frontends/ast/ast.h
View file

@ -244,6 +244,7 @@ namespace AST
// helper functions for real valued const eval
int isConst(); // return '1' for AST_CONSTANT and '2' for AST_REALVALUE
double asReal(bool is_signed);
RTLIL::Const realAsConst(int width);
};
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code

8
frontends/ast/genrtlil.cc
View file

@ -915,10 +915,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_REALVALUE:
{
int intvalue = round(realvalue);
log("Warning: converting real value %e to integer %d at %s:%d.\n",
realvalue, intvalue, filename.c_str(), linenum);
return RTLIL::SigSpec(intvalue);
RTLIL::SigSpec sig = realAsConst(width_hint);
log("Warning: converting real value %e to binary %s at %s:%d.\n",
realvalue, log_signal(sig), filename.c_str(), linenum);
return sig;
}
// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node

18
frontends/ast/simplify.cc
View file

@ -527,18 +527,18 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
// trim/extend parameters
if (type == AST_PARAMETER || type == AST_LOCALPARAM) {
if (children.size() > 1 && children[1]->type == AST_RANGE) {
if (children[0]->type == AST_REALVALUE) {
int intvalue = round(children[0]->realvalue);
log("Warning: converting real value %e to integer %d at %s:%d.\n",
children[0]->realvalue, intvalue, filename.c_str(), linenum);
delete children[0];
children[0] = mkconst_int(intvalue, sign_hint);
did_something = true;
}
if (children[0]->type == AST_CONSTANT) {
if (!children[1]->range_valid)
log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum);
int width = children[1]->range_left - children[1]->range_right + 1;
if (children[0]->type == AST_REALVALUE) {
RTLIL::Const constvalue = children[0]->realAsConst(width);
log("Warning: converting real value %e to binary %s at %s:%d.\n",
realvalue, log_signal(constvalue), filename.c_str(), linenum);
delete children[0];
children[0] = mkconst_bits(constvalue.bits, sign_hint);
did_something = true;
}
if (children[0]->type == AST_CONSTANT) {
if (width != int(children[0]->bits.size())) {
RTLIL::SigSpec sig(children[0]->bits);
sig.extend_u0(width, children[0]->is_signed);