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	improved (fixed) conversion of real values to bit vectors
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					 4 changed files with 30 additions and 11 deletions
				
			
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					@ -794,6 +794,24 @@ double AstNode::asReal(bool is_signed)
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	log_abort();
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						log_abort();
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}
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					}
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					RTLIL::Const AstNode::realAsConst(int width)
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					{
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						double v = round(realvalue);
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						RTLIL::Const result;
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						if (!isfinite(v)) {
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							result.bits = std::vector<RTLIL::State>(width, RTLIL::State::Sx);
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						} else {
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							bool is_negative = v < 0;
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							if (is_negative)
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								v *= -1;
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							for (int i = 0; i < width; i++, v /= 2)
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								result.bits.push_back((int(v) & 1) ? RTLIL::State::S1 : RTLIL::State::S0);
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							if (is_negative)
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								result = const_neg(result, result, false, false, result.bits.size());
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						}
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						return result;
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					}
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// create a new AstModule from an AST_MODULE AST node
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					// create a new AstModule from an AST_MODULE AST node
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static AstModule* process_module(AstNode *ast, bool defer)
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					static AstModule* process_module(AstNode *ast, bool defer)
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{
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					{
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					@ -244,6 +244,7 @@ namespace AST
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		// helper functions for real valued const eval
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							// helper functions for real valued const eval
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		int isConst(); // return '1' for AST_CONSTANT and '2' for AST_REALVALUE
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							int isConst(); // return '1' for AST_CONSTANT and '2' for AST_REALVALUE
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		double asReal(bool is_signed);
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							double asReal(bool is_signed);
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							RTLIL::Const realAsConst(int width);
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	};
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						};
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	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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						// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
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					@ -915,10 +915,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
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	case AST_REALVALUE:
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						case AST_REALVALUE:
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		{
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							{
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			int intvalue = round(realvalue);
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								RTLIL::SigSpec sig = realAsConst(width_hint);
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			log("Warning: converting real value %e to integer %d at %s:%d.\n",
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								log("Warning: converting real value %e to binary %s at %s:%d.\n",
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					realvalue, intvalue, filename.c_str(), linenum);
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										realvalue, log_signal(sig), filename.c_str(), linenum);
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			return RTLIL::SigSpec(intvalue);
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								return sig;
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		}
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							}
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	// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
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						// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node
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					@ -527,18 +527,18 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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	// trim/extend parameters
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						// trim/extend parameters
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	if (type == AST_PARAMETER || type == AST_LOCALPARAM) {
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						if (type == AST_PARAMETER || type == AST_LOCALPARAM) {
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		if (children.size() > 1 && children[1]->type == AST_RANGE) {
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							if (children.size() > 1 && children[1]->type == AST_RANGE) {
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			if (children[0]->type == AST_REALVALUE) {
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				int intvalue = round(children[0]->realvalue);
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				log("Warning: converting real value %e to integer %d at %s:%d.\n",
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						children[0]->realvalue, intvalue, filename.c_str(), linenum);
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				delete children[0];
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				children[0] = mkconst_int(intvalue, sign_hint);
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				did_something = true;
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			}
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			if (children[0]->type == AST_CONSTANT) {
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			if (!children[1]->range_valid)
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								if (!children[1]->range_valid)
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				log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum);
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									log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum);
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			int width = children[1]->range_left - children[1]->range_right + 1;
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								int width = children[1]->range_left - children[1]->range_right + 1;
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								if (children[0]->type == AST_REALVALUE) {
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									RTLIL::Const constvalue = children[0]->realAsConst(width);
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									log("Warning: converting real value %e to binary %s at %s:%d.\n",
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											realvalue, log_signal(constvalue), filename.c_str(), linenum);
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									delete children[0];
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									children[0] = mkconst_bits(constvalue.bits, sign_hint);
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									did_something = true;
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								}
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								if (children[0]->type == AST_CONSTANT) {
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				if (width != int(children[0]->bits.size())) {
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									if (width != int(children[0]->bits.size())) {
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					RTLIL::SigSpec sig(children[0]->bits);
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										RTLIL::SigSpec sig(children[0]->bits);
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					sig.extend_u0(width, children[0]->is_signed);
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										sig.extend_u0(width, children[0]->is_signed);
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