mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 13:29:12 +00:00
Code Activity

Merge pull request #9 from alaindargelas/activity_clear

Browse source 
Activity clear pass
This commit is contained in:
Akash Levy 2024-10-17 11:06:28 -07:00 • committed by GitHub
commit 146e9effd0
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
1 changed files with 43 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

43
passes/cmds/activity.cc
View file

@ -126,6 +126,22 @@ struct ActivityProp {
}
};
struct ActivityClear {
Module *module;
ActivityClear(Module *module) : module(module)
{
for (Wire *wire : module->wires()) {
wire->set_string_attribute("$ACKT", "");
wire->set_string_attribute("$DUTY", "");
}
for (auto cell : module->cells()) {
cell->set_string_attribute("$ACKT:", "");
cell->set_string_attribute("$DUTY:", "");
}
}
};
struct ActivityPropPass : public Pass {
ActivityPropPass() : Pass("activity_prop", "Attaches wire activity to cell ports") {}
void help() override
@ -152,4 +168,31 @@ struct ActivityPropPass : public Pass {
}
} ActivityPropPass;
struct ActivityClearPass : public Pass {
ActivityClearPass() : Pass("activity_clear", "Clears activity attached to cells and wires") {}
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" activity_clear\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing Activity clearing pass\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
// No options currently. When adding in the future make sure to update docstring with [options]
break;
}
extra_args(args, argidx, design);
for (auto module : design->modules()) {
ActivityClear worker(module);
}
}
} ActivityClearPass;
PRIVATE_NAMESPACE_END