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remove cycloneive

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This commit is contained in:
Artur Swiderski 2020-11-14 18:05:14 +01:00
parent f8bcb78a32
commit 1452cd88e8
15 changed files with 24 additions and 333 deletions
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42
tests/arch/intel_le/mux.ys
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@ -11,16 +11,6 @@ select -assert-count 1 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
design -load read
hierarchy -top mux2
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
design -load read
hierarchy -top mux4
proc
@ -31,16 +21,6 @@ select -assert-count 3 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 3 t:MISTRAL_ALUT3
select -assert-none t:MISTRAL_ALUT3 %% t:* %D
design -load read
hierarchy -top mux8
proc
@ -52,17 +32,6 @@ select -assert-count 3 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 3 t:MISTRAL_ALUT3
select -assert-count 3 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
design -load read
hierarchy -top mux16
proc
@ -74,14 +43,3 @@ select -assert-max 6 t:MISTRAL_ALUT3
select -assert-max 7 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/intel_le/common/le_sim.v synth_intel_le -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 1 t:MISTRAL_ALUT2
select -assert-max 6 t:MISTRAL_ALUT3
select -assert-max 7 t:MISTRAL_ALUT4
select -assert-none t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 t:MISTRAL_ALUT4 %% t:* %D