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remove cycloneive

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This commit is contained in:
Artur Swiderski 2020-11-14 18:05:14 +01:00
parent f8bcb78a32
commit 1452cd88e8
15 changed files with 24 additions and 333 deletions
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26
techlibs/intel_le/common/dff_sim.v
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@ -1,10 +1,3 @@
// The four D flip-flops (DFFs) in a Cyclone V/10GX Adaptive Logic Module (ALM)
// act as one-bit memory cells that can be placed very flexibly (wherever there's
// an ALM); each flop is represented by a MISTRAL_FF cell.
//
// The flops in these chips are rather flexible in some ways, but in practice
// quite crippled by FPGA standards.
//
// What the flops can do
// ---------------------
// The core flop acts as a single-bit memory that initialises to zero at chip
@ -60,7 +53,7 @@ module MISTRAL_FF(
output reg Q
);
`ifdef cycloneiv
`ifdef cycloneiv
specify
if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
@ -75,23 +68,6 @@ specify
if (ACLR === 1'b0) (ACLR => Q) = 282;
endspecify
`endif
`ifdef cycloneive
specify
// TODO (long-term): investigate these numbers.
// It seems relying on the Quartus Timing Analyzer was not the best idea; it's too fiddly.
if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 219;
if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 219;
if (ENA && !SCLR && SLOAD) (posedge CLK => (Q : SDATA)) = 219;
$setup(DATAIN, posedge CLK, 268);
$setup(ENA, posedge CLK, 268);
$setup(SCLR, posedge CLK, 268);
$setup(SLOAD, posedge CLK, 268);
$setup(SDATA, posedge CLK, 268);
if (ACLR === 1'b0) (ACLR => Q) = 0;
endspecify
`endif
initial begin
// Altera flops initialise to zero.