Preparations for RTLIL::IdString redesign: cleanup of existing code

frontends/ast/ast.cc

@@ -325,7 +325,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
 	}
 
 	for (auto &it : attributes) {
-		fprintf(f, "%s" "(* %s = ", indent.c_str(), id2vl(it.first).c_str());
+		fprintf(f, "%s" "(* %s = ", indent.c_str(), id2vl(it.first.str()).c_str());
 		it.second->dumpVlog(f, "");
 		fprintf(f, " *)%s", indent.empty() ? "" : "\n");
 	}
@@ -958,7 +958,7 @@ AstModule::~AstModule()
 // create a new parametric module (when needed) and return the name of the generated module
 RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters)
 {
-	std::string stripped_name = name;
+	std::string stripped_name = name.str();
 
 	if (stripped_name.substr(0, 9) == "$abstract")
 		stripped_name = stripped_name.substr(9);

frontends/ast/simplify.cc

@@ -465,7 +465,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		size_t pos = str.rfind('.');
 		if (pos == std::string::npos)
 			log_error("Defparam `%s' does not contain a dot (module/parameter seperator) at %s:%d!\n",
-					RTLIL::id2cstr(str.c_str()), filename.c_str(), linenum);
+					RTLIL::id2cstr(str), filename.c_str(), linenum);
 		std::string modname = str.substr(0, pos), paraname = "\\" + str.substr(pos+1);
 		if (current_scope.count(modname) == 0 || current_scope.at(modname)->type != AST_CELL)
 			log_error("Can't find cell for defparam `%s . %s` at %s:%d!\n", RTLIL::id2cstr(modname), RTLIL::id2cstr(paraname), filename.c_str(), linenum);

kernel/celltypes.h

@@ -29,7 +29,7 @@
 
 struct CellTypes
 {
-	std::set<std::string> cell_types;
+	std::set<RTLIL::IdString> cell_types;
 	std::vector<const RTLIL::Design*> designs;
 
 	CellTypes()
@@ -168,7 +168,7 @@ struct CellTypes
 		designs.clear();
 	}
 
-	bool cell_known(std::string type)
+	bool cell_known(RTLIL::IdString type)
 	{
 		if (cell_types.count(type) > 0)
 			return true;
@@ -178,7 +178,7 @@ struct CellTypes
 		return false;
 	}
 
-	bool cell_output(std::string type, std::string port)
+	bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
 	{
 		if (cell_types.count(type) == 0) {
 			for (auto design : designs)
@@ -201,7 +201,7 @@ struct CellTypes
 		return false;
 	}
 
-	bool cell_input(std::string type, std::string port)
+	bool cell_input(RTLIL::IdString type, RTLIL::IdString port)
 	{
 		if (cell_types.count(type) == 0) {
 			for (auto design : designs)
@@ -219,7 +219,7 @@ struct CellTypes
 		return false;
 	}
 
-	static RTLIL::Const eval(std::string type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
+	static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 	{
 		if (type == "$sshr" && !signed1)
 			type = "$shr";

kernel/log.cc

@@ -203,12 +203,12 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
 	return string_buf.back().c_str();
 }
 
-const char *log_id(std::string str)
+const char *log_id(RTLIL::IdString str)
 {
 	if (str.size() > 1 && str[0] == '\\' && str[1] != '$')
 		string_buf.push_back(str.substr(1));
 	else
-		string_buf.push_back(str);
+		string_buf.push_back(str.str());
 	return string_buf.back().c_str();
 }
 

kernel/log.h

@@ -60,7 +60,7 @@ void log_reset_stack();
 void log_flush();
 
 const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);
-const char *log_id(std::string id);
+const char *log_id(RTLIL::IdString id);
 
 template<typename T> static inline const char *log_id(T *obj) {
 	return log_id(obj->name);

kernel/rtlil.h

@@ -72,9 +72,7 @@ namespace RTLIL
 
 	typedef std::pair<SigSpec, SigSpec> SigSig;
 
-#ifdef NDEBUG
+#if 1
-	typedef std::string IdString;
-#else
 	struct IdString : public std::string {
 		IdString() { }
 		IdString(std::string str) : std::string(str) {
@@ -100,30 +98,70 @@ namespace RTLIL
 		void check() const {
 			log_assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\')));
 		}
+		const std::string& str() const {
+			return *this;
+		}
 	};
+#else
+	struct IdString {
+		IdString();
+		IdString(const char *str);
+		IdString(const IdString &str);
+		IdString(const std::string &str);
+
+		void operator=(const char *rhs);
+		void operator=(const IdString &rhs);
+		void operator=(const std::string &rhs);
+
+		operator const char*() const;
+		const std::string& str() const;
+
+		bool operator<(const IdString &rhs) const;
+		bool operator==(const IdString &rhs) const;
+		bool operator!=(const IdString &rhs) const;
+		bool operator==(const char *rhs) const;
+		bool operator!=(const char *rhs) const;
+		std::string operator+(const char *other) const;
+
+		std::string::const_iterator begin() const;
+		std::string::const_iterator end() const;
+		char at(int i) const;
+		const char*c_str() const;
+		size_t find(char c) const;
+		std::string substr(size_t pos = 0, size_t len = std::string::npos) const;
+		size_t size() const;
+		bool empty() const;
+		void clear();
+	};
+
 #endif
 
-	static IdString escape_id(std::string str) __attribute__((unused));
+	static inline std::string escape_id(std::string str) {
-	static IdString escape_id(std::string str) {
 		if (str.size() > 0 && str[0] != '\\' && str[0] != '$')
 			return "\\" + str;
 		return str;
 	}
 
-	static std::string unescape_id(std::string str) __attribute__((unused));
+	static inline std::string unescape_id(std::string str) {
-	static std::string unescape_id(std::string str) {
 		if (str.size() > 1 && str[0] == '\\' && str[1] != '$')
 			return str.substr(1);
 		return str;
 	}
 
-	static const char *id2cstr(std::string str) __attribute__((unused));
+	static inline const char *id2cstr(std::string str) {
-	static const char *id2cstr(std::string str) {
 		if (str.size() > 1 && str[0] == '\\' && str[1] != '$')
 			return str.c_str() + 1;
 		return str.c_str();
 	}
 
+	static inline std::string unescape_id(RTLIL::IdString str) {
+		return unescape_id(str.str());
+	}
+
+	static inline const char *id2cstr(RTLIL::IdString str) {
+		return id2cstr(str.str());
+	}
+
 	template <typename T> struct sort_by_name {
 		bool operator()(T *a, T *b) const {
 			return a->name < b->name;

kernel/yosys.cc

@@ -445,7 +445,7 @@ static char *readline_obj_generator(const char *text, int state)
 		{
 			for (auto &it : design->modules_)
 				if (RTLIL::unescape_id(it.first).substr(0, len) == text)
-					obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
+					obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
 		}
 		else
 		if (design->modules_.count(design->selected_active_module) > 0)
@@ -454,19 +454,19 @@ static char *readline_obj_generator(const char *text, int state)
 
 			for (auto &it : module->wires_)
 				if (RTLIL::unescape_id(it.first).substr(0, len) == text)
-					obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
+					obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
 
 			for (auto &it : module->memories)
 				if (RTLIL::unescape_id(it.first).substr(0, len) == text)
-					obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
+					obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
 
 			for (auto &it : module->cells_)
 				if (RTLIL::unescape_id(it.first).substr(0, len) == text)
-					obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
+					obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
 
 			for (auto &it : module->processes)
 				if (RTLIL::unescape_id(it.first).substr(0, len) == text)
-					obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
+					obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
 		}
 
 		std::sort(obj_names.begin(), obj_names.end());

kernel/yosys.h

@@ -63,6 +63,7 @@
 YOSYS_NAMESPACE_BEGIN
 
 namespace RTLIL {
+	struct IdString;
 	struct SigSpec;
 	struct Wire;
 	struct Cell;

passes/abc/abc.cc

@@ -193,7 +193,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
 	}
 }
 
-static std::string remap_name(std::string abc_name)
+static std::string remap_name(RTLIL::IdString abc_name)
 {
 	std::stringstream sstr;
 	sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);

passes/cmds/delete.cc

@@ -64,7 +64,7 @@ struct DeletePass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		std::vector<std::string> delete_mods;
+		std::vector<RTLIL::IdString> delete_mods;
 
 		for (auto &mod_it : design->modules_)
 		{
@@ -92,8 +92,8 @@ struct DeletePass : public Pass {
 
 			std::set<RTLIL::Wire*> delete_wires;
 			std::set<RTLIL::Cell*> delete_cells;
-			std::set<std::string> delete_procs;
+			std::set<RTLIL::IdString> delete_procs;
-			std::set<std::string> delete_mems;
+			std::set<RTLIL::IdString> delete_mems;
 
 			for (auto &it : module->wires_)
 				if (design->selected(module, it.second))

passes/cmds/design.cc

@@ -192,7 +192,7 @@ struct DesignPass : public Pass {
 
 			for (auto mod : copy_src_modules)
 			{
-				std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name);
+				std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name);
 
 				if (copy_to_design->modules_.count(trg_name))
 					delete copy_to_design->modules_.at(trg_name);

passes/cmds/select.cc

@@ -547,7 +547,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
 		return;
 	}
 
-	std::vector<std::string> del_list;
+	std::vector<RTLIL::IdString> del_list;
 	for (auto mod_name : sel.selected_modules)
 		if (mod_name != design->selected_active_module)
 			del_list.push_back(mod_name);
@@ -1322,7 +1322,7 @@ struct CdPass : public Pass {
 template<typename T>
 static int log_matches(const char *title, std::string pattern, T list)
 {
-	std::vector<std::string> matches;
+	std::vector<RTLIL::IdString> matches;
 
 	for (auto &it : list)
 		if (pattern.empty() || match_ids(it.first, pattern))