mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-08 12:11:24 +00:00
Code Activity

Preparations for RTLIL::IdString redesign: cleanup of existing code

Browse source
This commit is contained in:
Clifford Wolf 2014-08-02 00:45:25 +02:00
parent 75ffd1643c
commit 14412e6c95
12 changed files with 71 additions and 32 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/select.cc
View file

@ -547,7 +547,7 @@ static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &se
return;
}
std::vector<std::string> del_list;
std::vector<RTLIL::IdString> del_list;
for (auto mod_name : sel.selected_modules)
if (mod_name != design->selected_active_module)
del_list.push_back(mod_name);
@ -1322,7 +1322,7 @@ struct CdPass : public Pass {
template<typename T>
static int log_matches(const char *title, std::string pattern, T list)
{
std::vector<std::string> matches;
std::vector<RTLIL::IdString> matches;
for (auto &it : list)
if (pattern.empty() || match_ids(it.first, pattern))