3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-31 00:13:18 +00:00

Preparations for RTLIL::IdString redesign: cleanup of existing code

This commit is contained in:
Clifford Wolf 2014-08-02 00:45:25 +02:00
parent 75ffd1643c
commit 14412e6c95
12 changed files with 71 additions and 32 deletions

View file

@ -64,7 +64,7 @@ struct DeletePass : public Pass {
}
extra_args(args, argidx, design);
std::vector<std::string> delete_mods;
std::vector<RTLIL::IdString> delete_mods;
for (auto &mod_it : design->modules_)
{
@ -92,8 +92,8 @@ struct DeletePass : public Pass {
std::set<RTLIL::Wire*> delete_wires;
std::set<RTLIL::Cell*> delete_cells;
std::set<std::string> delete_procs;
std::set<std::string> delete_mems;
std::set<RTLIL::IdString> delete_procs;
std::set<RTLIL::IdString> delete_mems;
for (auto &it : module->wires_)
if (design->selected(module, it.second))