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Various improvements in sat_solve pass and SAT generator

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Clifford Wolf 2013-06-08 14:11:50 +02:00
parent 99957a825f
commit 1434312fdd
4 changed files with 155 additions and 41 deletions
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6
passes/sat/example.ys
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@ -1,3 +1,5 @@
read_verilog example.v
techmap; opt; abc; opt
sat_solve -set y 1'b1
proc; opt_clean
sat_solve -set y 1'b1 example001
sat_solve -set y 1'b1 example002
sat_solve -set y 1'b1 example003