mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-22 13:53:40 +00:00
Code Activity

Various improvements in sat_solve pass and SAT generator

Browse source
This commit is contained in:
Clifford Wolf 2013-06-08 14:11:50 +02:00
parent 99957a825f
commit 1434312fdd
4 changed files with 155 additions and 41 deletions
Download patch file Download diff file Expand all files Collapse all files

62
passes/sat/example.v
View file

@ -1,5 +1,5 @@
module example(a, y);
module example001(a, y);
input [15:0] a;
output y;
@ -10,3 +10,63 @@ assign y = !gt && !lt;
endmodule
// ------------------------------------
module example002(a, y);
input [3:0] a;
output y;
reg [1:0] t1, t2;
always @* begin
casex (a)
16'b1xxx:
t1 <= 1;
16'bx1xx:
t1 <= 2;
16'bxx1x:
t1 <= 3;
16'bxxx1:
t1 <= 4;
default:
t1 <= 0;
endcase
casex (a)
16'b1xxx:
t2 <= 1;
16'b01xx:
t2 <= 2;
16'b001x:
t2 <= 3;
16'b0001:
t2 <= 4;
default:
t2 <= 0;
endcase
end
assign y = t1 != t2;
endmodule
// ------------------------------------
module example003(clk, rst, y);
input clk, rst;
output y;
reg [3:0] counter;
always @(posedge clk)
case (1)
rst, counter == 9:
counter <= 0;
default:
counter <= counter+1;
endcase
assign y = counter == 12;
endmodule