From 13f9d65b6fc09af76330c02ab420324b50db61da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 00:29:45 -0700
Subject: [PATCH] abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to
remove it
---
passes/techmap/abc9_ops.cc | 18 +-----------------
techlibs/common/abc9_map.v | 4 ++--
techlibs/common/abc9_unmap.v | 5 ++---
tests/various/abc9.ys | 11 ++++++++---
4 files changed, 13 insertions(+), 25 deletions(-)
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 41a11e9a7..03a3c5583 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1101,17 +1101,6 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
map_autoidx = autoidx++;
- // TODO: Get rid of this expensive lookup
- dict<SigBit,vector<SigBit>> sig2inits;
- SigMap sigmap(module);
- for (auto w : module->wires()) {
- auto it = w->attributes.find(ID::init);
- if (it == w->attributes.end())
- continue;
- for (const auto &b : SigSpec(w))
- sig2inits[sigmap(b)].emplace_back(b);
- }
-
RTLIL::Module *mapped_mod = design->module(stringf("%s$abc9", module->name.c_str()));
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `%s$abc'.\n", log_id(module));
@@ -1164,12 +1153,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// Short out $_DFF_[NP]_ cells since the flop box already has
// all the information we need to reconstruct cell
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
- SigBit Q = cell->getPort(ID::Q);
- auto it = sig2inits.find(Q);
- if (it != sig2inits.end())
- for (const auto &b : it->second)
- b.wire->attributes.at(ID::init)[b.offset] = State::Sx;
- module->connect(Q, cell->getPort(ID::D));
+ module->connect(cell->getPort(ID::Q), cell->getPort(ID::D));
module->remove(cell);
}
else if (cell->type.in(ID($_AND_), ID($_NOT_)))
diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v
index 182915842..bb2b4a4b1 100644
--- a/techlibs/common/abc9_map.v
+++ b/techlibs/common/abc9_map.v
@@ -3,14 +3,14 @@
module $_DFF_x_(input C, D, output Q);
parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
parameter _TECHMAP_CELLTYPE_ = "";
- (* init=_TECHMAP_WIREINIT_Q_ *) wire D_;
+ wire D_;
generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin
if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
$__DFF_N__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
$_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
end
else
- $__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));// hide from abc9 using $__ prefix
+ $__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix
end
else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin
if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v
index d628a73ac..b765356d8 100644
--- a/techlibs/common/abc9_unmap.v
+++ b/techlibs/common/abc9_unmap.v
@@ -1,6 +1,5 @@
(* techmap_celltype = "$__DFF_N__$abc9_flop $__DFF_P__$abc9_flop" *)
-module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1);
- parameter [0:0] INIT = 1'bx;
+module $__DFF_x__$abc9_flop (input C, D, Q, output n1);
parameter _TECHMAP_CELLTYPE_ = "";
generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N__$abc9_flop")
$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
@@ -12,7 +11,7 @@ module $__DFF_x__$abc9_flop (input C, D, Q, (* init = INIT *) output n1);
endmodule
(* techmap_celltype = "$__DFF_N_ $__DFF_P_" *)
-module $__DFF_N__$abc9_flop (input C, D, output Q);
+module $__DFF_x_ (input C, D, output Q);
parameter _TECHMAP_CELLTYPE_ = "";
generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N_")
$_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 9586091c4..ac714665f 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -78,18 +78,23 @@ abc9
design -reset
read_verilog -icells <<EOT
-module abc9_test038(input clk, output w, x, y);
+module abc9_test038(input clk, output w, x, y, z);
(* init=1'b1 *) wire w;
$_DFF_N_ ff1(.C(clk), .D(1'b1), .Q(w));
(* init=1'bx *) wire x;
$_DFF_N_ ff2(.C(clk), .D(1'b0), .Q(x));
(* init=1'b0 *) wire y;
$_DFF_N_ ff3(.C(clk), .D(1'b0), .Q(y));
+(* init=1'b0 *) wire z;
+$_DFF_N_ ff4(.C(clk), .D(1'b1), .Q(z));
endmodule
EOT
simplemap
equiv_opt abc9 -lut 4 -dff
design -load postopt
cd abc9_test038
-select -assert-count 2 t:$_DFF_N_
-select -assert-none c:ff1 c:ff2 %% c:* %D
+select -assert-count 3 t:$_DFF_N_
+select -assert-none c:ff1 c:ff2 c:ff4 %% c:* %D
+clean
+select -assert-count 2 a:init
+select -assert-none w:w w:z %% a:init %D