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RIP $safe_pmux
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parent
28cf48e31f
commit
13f2f36884
16 changed files with 21 additions and 98 deletions
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@ -42,7 +42,7 @@ struct WreduceConfig
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supported_cell_types << "$shl" << "$shr" << "$sshl" << "$sshr" << "$shift" << "$shiftx";
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supported_cell_types << "$lt" << "$le" << "$eq" << "$ne" << "$eqx" << "$nex" << "$ge" << "$gt";
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supported_cell_types << "$add" << "$sub"; // << "$mul" << "$div" << "$mod" << "$pow"
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supported_cell_types << "$mux" << "$pmux" << "$safe_pmux";
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supported_cell_types << "$mux" << "$pmux";
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}
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};
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@ -172,7 +172,7 @@ struct WreduceWorker
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if (!cell->type.in(config->supported_cell_types))
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return;
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if (cell->type.in("$mux", "$pmux", "$safe_pmux"))
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if (cell->type.in("$mux", "$pmux"))
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return run_cell_mux(cell);
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@ -50,7 +50,7 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
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std::set<sig2driver_entry_t> cellport_list;
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sig2driver.find(sig, cellport_list);
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for (auto &cellport : cellport_list) {
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if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux" && cellport.first->type != "$safe_pmux") || cellport.second != "\\Y")
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if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != "\\Y")
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return false;
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RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort("\\A"));
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RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort("\\B"));
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@ -42,7 +42,7 @@ struct FsmExpand
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bool is_cell_merge_candidate(RTLIL::Cell *cell)
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{
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if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
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if (cell->type == "$mux" || cell->type == "$pmux")
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if (cell->getPort("\\A").size() < 2)
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return true;
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@ -55,7 +55,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
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for (auto &cellport : cellport_list)
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{
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") {
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if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != "\\Y") {
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log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
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return false;
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}
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@ -84,7 +84,7 @@ struct OptMuxtreeWorker
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// .const_activated
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for (auto cell : module->cells())
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{
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if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
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if (cell->type == "$mux" || cell->type == "$pmux")
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{
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RTLIL::SigSpec sig_a = cell->getPort("\\A");
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RTLIL::SigSpec sig_b = cell->getPort("\\B");
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@ -312,7 +312,7 @@ struct OptReduceWorker
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std::vector<RTLIL::Cell*> cells;
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for (auto &it : module->cells_)
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if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second))
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if ((it.second->type == "$mux" || it.second->type == "$pmux") && design->selected(module, it.second))
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cells.push_back(it.second);
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for (auto cell : cells)
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@ -224,7 +224,6 @@ struct OptShareWorker
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if (mode_nomux) {
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ct.cell_types.erase("$mux");
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ct.cell_types.erase("$pmux");
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ct.cell_types.erase("$safe_pmux");
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}
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log("Finding identical cells in module `%s'.\n", module->name.c_str());
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@ -176,7 +176,6 @@ struct TestCellPass : public Pass {
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// cell_types["$pmux"] = "A";
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// cell_types["$slice"] = "A";
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// cell_types["$concat"] = "A";
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// cell_types["$safe_pmux"] = "A";
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// cell_types["$lut"] = "A";
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// cell_types["$assert"] = "A";
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