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Update CHANGELOG

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This commit is contained in:
Eddie Hung 2019-06-14 12:50:30 -07:00
parent b63b2a0bd4
commit 13e2e8df11
1 changed files with 3 additions and 2 deletions
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CHANGELOG
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@ -17,12 +17,13 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "rename -src" - Added "rename -src"
- Added "equiv_opt" pass - Added "equiv_opt" pass
- Added "read_aiger" frontend - Added "read_aiger" frontend
- Added "shregmap -tech xilinx"
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental) - Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental) - Added "synth -abc9" (experimental)
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
- "synth_xilinx" to now infer wide multiplexers - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
Yosys 0.7 .. Yosys 0.8 Yosys 0.7 .. Yosys 0.8