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genrtlil: even fastererer removeSignalFromCaseTree
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7982102143
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1 changed files with 32 additions and 9 deletions
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@ -566,17 +566,40 @@ struct AST_INTERNAL::ProcessGenerator
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// the third assignment.
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// the third assignment.
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void removeSignalFromCaseTree(const pool<RTLIL::SigBit> &pattern_bits, const pool<RTLIL::Wire*> &pattern_wires, RTLIL::CaseRule *cs)
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void removeSignalFromCaseTree(const pool<RTLIL::SigBit> &pattern_bits, const pool<RTLIL::Wire*> &pattern_wires, RTLIL::CaseRule *cs)
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{
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{
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for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
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// If pattern only uses one wire, we can check more efficiently
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// Quick check: if the lvalue doesn't reference any pattern wires, skip
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if (pattern_wires.size() == 1) {
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bool may_overlap = false;
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RTLIL::Wire *pattern_wire = *pattern_wires.begin();
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for (auto &chunk : it->first.chunks()) {
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for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
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if (chunk.wire != NULL && pattern_wires.count(chunk.wire)) {
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// Quick check using first/last bit heuristic
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may_overlap = true;
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int sz = it->first.size();
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break;
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if (sz == 0) continue;
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RTLIL::Wire *first_wire = it->first[0].wire;
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if (first_wire == pattern_wire ||
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(sz > 1 && it->first[sz-1].wire == pattern_wire)) {
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it->first.remove2(pattern_bits, &it->second);
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} else if (first_wire != it->first[sz > 1 ? sz-1 : 0].wire) {
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// Multiple wires - need full check
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for (auto &chunk : it->first.chunks()) {
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if (chunk.wire == pattern_wire) {
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it->first.remove2(pattern_bits, &it->second);
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break;
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}
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}
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}
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}
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}
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}
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if (may_overlap)
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} else {
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it->first.remove2(pattern_bits, &it->second);
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for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
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// Quick check: if the lvalue doesn't reference any pattern wires, skip
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bool may_overlap = false;
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for (auto &chunk : it->first.chunks()) {
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if (chunk.wire != NULL && pattern_wires.count(chunk.wire)) {
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may_overlap = true;
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break;
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}
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}
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if (may_overlap)
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it->first.remove2(pattern_bits, &it->second);
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}
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}
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}
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for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
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for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
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