mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
Merge remote-tracking branch 'origin' into xc7srl
This commit is contained in:
Eddie Hung
commit
13ad19482f
15 changed files with 192 additions and 103 deletions
2
Makefile
2
Makefile
|
|
@ -111,7 +111,7 @@ OBJS = kernel/version_$(GIT_REV).o
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|||
# is just a symlink to your actual ABC working directory, as 'make mrproper'
|
||||
# will remove the 'abc' directory and you do not want to accidentally
|
||||
# delete your work on ABC..
|
||||
ABCREV = 2ddc57d
|
||||
ABCREV = 3709744
|
||||
ABCPULL = 1
|
||||
ABCURL ?= https://github.com/berkeley-abc/abc
|
||||
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
|
||||
|
|
|
|||
|
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@ -312,10 +312,10 @@ Verilog Attributes and non-standard features
|
|||
passes to identify input and output ports of cells. The Verilog backend
|
||||
also does not output blackbox modules on default.
|
||||
|
||||
- The ``dynports'' attribute is used by the Verilog front-end to mark modules
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||||
- The ``dynports`` attribute is used by the Verilog front-end to mark modules
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||||
that have ports with a width that depends on a parameter.
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||||
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||||
- The ``hdlname'' attribute is used by some passes to document the original
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||||
- The ``hdlname`` attribute is used by some passes to document the original
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||||
(HDL) name of a module when renaming a module.
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||||
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- The ``keep`` attribute on cells and wires is used to mark objects that should
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@ -340,7 +340,7 @@ struct BtorWorker
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if (cell->type == "$lt") btor_op = "lt";
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if (cell->type == "$le") btor_op = "lte";
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if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
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if (cell->type.in("$ne", "$nex")) btor_op = "ne";
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if (cell->type.in("$ne", "$nex")) btor_op = "neq";
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if (cell->type == "$ge") btor_op = "gte";
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if (cell->type == "$gt") btor_op = "gt";
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log_assert(!btor_op.empty());
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|
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@ -237,15 +237,34 @@ struct ShowWorker
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int idx = single_idx_count++;
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for (int rep, i = int(sig.chunks().size())-1; i >= 0; i -= rep) {
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const RTLIL::SigChunk &c = sig.chunks().at(i);
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if (!driver && c.wire == nullptr) {
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RTLIL::State s1 = c.data.front();
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for (auto s2 : c.data)
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if (s1 != s2)
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goto not_const_stream;
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net.clear();
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} else {
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not_const_stream:
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net = gen_signode_simple(c, false);
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log_assert(!net.empty());
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}
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for (rep = 1; i-rep >= 0 && c == sig.chunks().at(i-rep); rep++) {}
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std::string repinfo = rep > 1 ? stringf("%dx ", rep) : "";
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if (driver) {
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log_assert(!net.empty());
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label_string += stringf("<s%d> %d:%d - %s%d:%d |", i, pos, pos-c.width+1, repinfo.c_str(), c.offset+c.width-1, c.offset);
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net_conn_map[net].in.insert(stringf("x%d:s%d", idx, i));
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net_conn_map[net].bits = rep*c.width;
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net_conn_map[net].color = nextColor(c, net_conn_map[net].color);
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} else
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if (net.empty()) {
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log_assert(rep == 1);
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label_string += stringf("%c -> %d:%d |",
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c.data.front() == State::S0 ? '0' :
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c.data.front() == State::S1 ? '1' :
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c.data.front() == State::Sx ? 'X' :
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c.data.front() == State::Sz ? 'Z' : '?',
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pos, pos-rep*c.width+1);
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} else {
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label_string += stringf("<s%d> %s%d:%d - %d:%d |", i, repinfo.c_str(), c.offset+c.width-1, c.offset, pos, pos-rep*c.width+1);
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net_conn_map[net].out.insert(stringf("x%d:s%d", idx, i));
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|
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@ -744,6 +744,7 @@ grow_read_ports:;
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if (clken) {
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clock_domains[pi.clocks] = clkdom;
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clock_polarities[pi.clkpol] = clkdom.second;
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if (!pi.make_transp)
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read_transp[pi.transp] = transp;
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pi.sig_clock = clkdom.first;
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pi.sig_en = rd_en[cell_port_i];
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||||
|
|
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@ -83,8 +83,8 @@ They are declared like state variables, just using the `udata` statement:
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udata <int> min_data_width max_data_width
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udata <IdString> data_port_name
|
||||
|
||||
They are atomatically initialzed to the default constructed value of their type
|
||||
when ther pattern matcher object is constructed.
|
||||
They are automatically initialized to the default constructed value of their type
|
||||
when the pattern matcher object is constructed.
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||||
|
||||
Embedded C++ code
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||||
-----------------
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||||
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@ -158,7 +158,7 @@ Finally, `filter <expression>` narrows down the remaining list of cells. For
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performance reasons `filter` statements should only be used for things that
|
||||
can't be done using `select` and `index`.
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||||
|
||||
The `optional` statement marks optional matches. I.e. the matcher will also
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||||
The `optional` statement marks optional matches. That is, the matcher will also
|
||||
explore the case where `mul` is set to `nullptr`. Without the `optional`
|
||||
statement a match may only be assigned nullptr when one of the `if` expressions
|
||||
evaluates to `false`.
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||||
|
|
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@ -108,6 +108,7 @@ struct SigSnippets
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struct SnippetSwCache
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{
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dict<RTLIL::SwitchRule*, pool<RTLIL::SigBit>, hash_ptr_ops> full_case_bits_cache;
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dict<RTLIL::SwitchRule*, pool<int>, hash_ptr_ops> cache;
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const SigSnippets *snippets;
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int current_snippet;
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@ -268,6 +269,49 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve
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last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort("\\S").size();
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}
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const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)
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{
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if (!swcache.full_case_bits_cache.count(sw))
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{
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pool<SigBit> bits;
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if (sw->get_bool_attribute("\\full_case"))
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{
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bool first_case = true;
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for (auto cs : sw->cases)
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{
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pool<SigBit> case_bits;
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for (auto it : cs->actions) {
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for (auto bit : it.first)
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case_bits.insert(bit);
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}
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for (auto it : cs->switches) {
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for (auto bit : get_full_case_bits(swcache, it))
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case_bits.insert(bit);
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}
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||||
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if (first_case) {
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first_case = false;
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bits = case_bits;
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||||
} else {
|
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pool<SigBit> new_bits;
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for (auto bit : bits)
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if (case_bits.count(bit))
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new_bits.insert(bit);
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bits.swap(new_bits);
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}
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}
|
||||
}
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bits.swap(swcache.full_case_bits_cache[sw]);
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}
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return swcache.full_case_bits_cache.at(sw);
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||||
}
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RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, dict<RTLIL::SwitchRule*, bool, hash_ptr_ops> &swpara,
|
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RTLIL::CaseRule *cs, const RTLIL::SigSpec &sig, const RTLIL::SigSpec &defval, bool ifxmode)
|
||||
{
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||||
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@ -337,10 +381,15 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
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}
|
||||
}
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// mask default bits that are irrelevant because the output is driven by a full case
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const pool<SigBit> &full_case_bits = get_full_case_bits(swcache, sw);
|
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for (int i = 0; i < GetSize(sig); i++)
|
||||
if (full_case_bits.count(sig[i]))
|
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result[i] = State::Sx;
|
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|
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// evaluate in reverse order to give the first entry the top priority
|
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RTLIL::SigSpec initial_val = result;
|
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RTLIL::Cell *last_mux_cell = NULL;
|
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bool shiftx = initial_val.is_fully_undef();
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for (size_t i = 0; i < sw->cases.size(); i++) {
|
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int case_idx = sw->cases.size() - i - 1;
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RTLIL::CaseRule *cs2 = sw->cases[case_idx];
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@ -349,22 +398,9 @@ RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, SnippetSwCache &swcache, d
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append_pmux(mod, sw->signal, cs2->compare, value, last_mux_cell, sw, ifxmode);
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else
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result = gen_mux(mod, sw->signal, cs2->compare, value, result, last_mux_cell, sw, ifxmode);
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// Ignore output values which are entirely don't care
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if (shiftx && !value.is_fully_undef()) {
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// Keep checking if case condition is the same as the current case index
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if (cs2->compare.size() == 1 && cs2->compare.front().is_fully_const())
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shiftx = (cs2->compare.front().as_int() == case_idx);
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else
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shiftx = false;
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}
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}
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// Mark this pmux as being $shiftx compatible
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if (shiftx && last_mux_cell && last_mux_cell->type == "$pmux")
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last_mux_cell->set_bool_attribute("\\shiftx_compatible");
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}
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return result;
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}
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|
|
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@ -28,7 +28,7 @@
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|||
USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
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void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter)
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{
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BitPatternPool pool(sw->signal);
|
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|
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|
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@ -56,11 +56,16 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
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}
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for (auto switch_it : sw->cases[i]->switches)
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proc_rmdead(switch_it, counter);
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proc_rmdead(switch_it, counter, full_case_counter);
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|
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if (is_default)
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pool.take_all();
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}
|
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|
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if (pool.empty() && !sw->get_bool_attribute("\\full_case")) {
|
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sw->set_bool_attribute("\\full_case");
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full_case_counter++;
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}
|
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}
|
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|
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struct ProcRmdeadPass : public Pass {
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|
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@ -87,12 +92,15 @@ struct ProcRmdeadPass : public Pass {
|
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for (auto &proc_it : mod->processes) {
|
||||
if (!design->selected(mod, proc_it.second))
|
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continue;
|
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int counter = 0;
|
||||
int counter = 0, full_case_counter = 0;
|
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for (auto switch_it : proc_it.second->root_case.switches)
|
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proc_rmdead(switch_it, counter);
|
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proc_rmdead(switch_it, counter, full_case_counter);
|
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if (counter > 0)
|
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log("Removed %d dead cases from process %s in module %s.\n", counter,
|
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proc_it.first.c_str(), log_id(mod));
|
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log_id(proc_it.first), log_id(mod));
|
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if (full_case_counter > 0)
|
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log("Marked %d switch rules as full_case in process %s in module %s.\n",
|
||||
full_case_counter, log_id(proc_it.first), log_id(mod));
|
||||
total_counter += counter;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,17 +29,17 @@
|
|||
// Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
|
||||
// http://en.wikipedia.org/wiki/Topological_sorting
|
||||
|
||||
#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
|
||||
#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
|
||||
#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2"
|
||||
#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}"
|
||||
#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put"
|
||||
#define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put"
|
||||
#define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p"
|
||||
#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; if; mfs2"
|
||||
#define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; dch -f; cover {I} {P}"
|
||||
#define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; retime {D}; strash; &get -n; &dch -f; &nf {D}; &put"
|
||||
|
||||
#define ABC_FAST_COMMAND_LIB "strash; dretime; map {D}"
|
||||
#define ABC_FAST_COMMAND_CTR "strash; dretime; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
|
||||
#define ABC_FAST_COMMAND_LUT "strash; dretime; if"
|
||||
#define ABC_FAST_COMMAND_SOP "strash; dretime; cover -I {I} -P {P}"
|
||||
#define ABC_FAST_COMMAND_DFL "strash; dretime; map"
|
||||
#define ABC_FAST_COMMAND_LIB "strash; dretime; retime {D}; map {D}"
|
||||
#define ABC_FAST_COMMAND_CTR "strash; dretime; retime {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
|
||||
#define ABC_FAST_COMMAND_LUT "strash; dretime; retime {D}; if"
|
||||
#define ABC_FAST_COMMAND_SOP "strash; dretime; retime {D}; cover -I {I} -P {P}"
|
||||
#define ABC_FAST_COMMAND_DFL "strash; dretime; retime {D}; map"
|
||||
|
||||
#include "kernel/register.h"
|
||||
#include "kernel/sigtools.h"
|
||||
|
|
@ -331,8 +331,11 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
|
|||
{
|
||||
std::string abc_sname = abc_name.substr(1);
|
||||
if (abc_sname.substr(0, 5) == "ys__n") {
|
||||
int sid = std::stoi(abc_sname.substr(5));
|
||||
bool inv = abc_sname.back() == 'v';
|
||||
if (inv) abc_sname.pop_back();
|
||||
abc_sname.erase(0, 5);
|
||||
if (abc_sname.find_last_not_of("012345689") == std::string::npos) {
|
||||
int sid = std::stoi(abc_sname);
|
||||
for (auto sig : signal_list) {
|
||||
if (sig.id == sid && sig.bit.wire != nullptr) {
|
||||
std::stringstream sstr;
|
||||
|
|
@ -347,6 +350,7 @@ std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullp
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
std::stringstream sstr;
|
||||
sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
|
||||
return sstr.str();
|
||||
|
|
@ -731,10 +735,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
|
|||
else
|
||||
abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
|
||||
|
||||
if (script_file.empty() && !delay_target.empty())
|
||||
for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
|
||||
abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
|
||||
|
||||
for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
|
||||
abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
|
||||
|
||||
|
|
@ -1674,8 +1674,6 @@ struct AbcPass : public Pass {
|
|||
}
|
||||
if (arg == "-dff") {
|
||||
dff_mode = true;
|
||||
if (delay_target.empty())
|
||||
delay_target = "-D 1";
|
||||
continue;
|
||||
}
|
||||
if (arg == "-clk" && argidx+1 < args.size()) {
|
||||
|
|
|
|||
|
|
@ -71,9 +71,9 @@ struct PmuxtreePass : public Pass {
|
|||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" pmuxtree [options] [selection]\n");
|
||||
log(" pmuxtree [selection]\n");
|
||||
log("\n");
|
||||
log("This pass transforms $pmux cells to a trees of $mux cells.\n");
|
||||
log("This pass transforms $pmux cells to trees of $mux cells.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
|
|
|
|||
|
|
@ -85,7 +85,7 @@ module cyclonev_lcell_comb
|
|||
begin
|
||||
upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
|
||||
lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
|
||||
lut5 = (datae) ? upper_mask_value : lower_mask_value;
|
||||
lut5 = (datae) ? upper_lut_value : lower_lut_value;
|
||||
end
|
||||
endfunction // lut5
|
||||
|
||||
|
|
@ -95,15 +95,16 @@ module cyclonev_lcell_comb
|
|||
input dataa, datab, datac, datad, datae, dataf;
|
||||
reg upper_lut_value;
|
||||
reg lower_lut_value;
|
||||
reg out_0, out_1, out_2, out_3;
|
||||
begin
|
||||
upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
|
||||
lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
|
||||
lut6 = (dataf) ? upper_mask_value : lower_mask_value;
|
||||
lut6 = (dataf) ? upper_lut_value : lower_lut_value;
|
||||
end
|
||||
endfunction // lut6
|
||||
|
||||
assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
|
||||
|
||||
`ifdef ADVANCED_ALM
|
||||
always @(*) begin
|
||||
if(extended_lut == "on")
|
||||
shared_lut_alm = datag;
|
||||
|
|
@ -115,6 +116,11 @@ module cyclonev_lcell_comb
|
|||
out_2 = lut4(mask_c, dataa, datab, datac, datad);
|
||||
out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);
|
||||
end
|
||||
`else
|
||||
`ifdef DEBUG
|
||||
initial $display("Advanced ALM lut combine is not implemented yet");
|
||||
`endif
|
||||
`endif
|
||||
endmodule // cyclonev_lcell_comb
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -30,10 +30,15 @@ module GND(output G);
|
|||
endmodule
|
||||
|
||||
module IBUF(output O, input I);
|
||||
parameter IOSTANDARD = "default";
|
||||
parameter IBUF_LOW_PWR = 0;
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module OBUF(output O, input I);
|
||||
parameter IOSTANDARD = "default";
|
||||
parameter DRIVE = 12;
|
||||
parameter SLEW = "SLOW";
|
||||
assign O = I;
|
||||
endmodule
|
||||
|
||||
|
|
@ -41,6 +46,42 @@ module BUFG(output O, input I);
|
|||
assign O = I;
|
||||
endmodule
|
||||
|
||||
module BUFGCTRL(
|
||||
output O,
|
||||
input I0, input I1,
|
||||
input S0, input S1,
|
||||
input CE0, input CE1,
|
||||
input IGNORE0, input IGNORE1);
|
||||
|
||||
parameter [0:0] INIT_OUT = 1'b0;
|
||||
parameter PRESELECT_I0 = "FALSE";
|
||||
parameter PRESELECT_I1 = "FALSE";
|
||||
parameter [0:0] IS_CE0_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CE1_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S0_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S1_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
|
||||
|
||||
wire I0_internal = ((CE0 ^ IS_CE0_INVERTED) ? I0 : INIT_OUT);
|
||||
wire I1_internal = ((CE1 ^ IS_CE1_INVERTED) ? I1 : INIT_OUT);
|
||||
wire S0_true = (S0 ^ IS_S0_INVERTED);
|
||||
wire S1_true = (S1 ^ IS_S1_INVERTED);
|
||||
|
||||
assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
|
||||
|
||||
endmodule
|
||||
|
||||
module BUFHCE(output O, input I, input CE);
|
||||
|
||||
parameter [0:0] INIT_OUT = 1'b0;
|
||||
parameter CE_TYPE = "SYNC";
|
||||
parameter [0:0] IS_CE_INVERTED = 1'b0;
|
||||
|
||||
assign O = ((CE ^ IS_CE_INVERTED) ? I : INIT_OUT);
|
||||
|
||||
endmodule
|
||||
|
||||
// module OBUFT(output O, input I, T);
|
||||
// assign O = T ? 1'bz : I;
|
||||
// endmodule
|
||||
|
|
@ -98,6 +139,22 @@ module LUT6(output O, input I0, I1, I2, I3, I4, I5);
|
|||
assign O = I0 ? s1[1] : s1[0];
|
||||
endmodule
|
||||
|
||||
module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
|
||||
parameter [63:0] INIT = 0;
|
||||
wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0];
|
||||
wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0];
|
||||
wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0];
|
||||
wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
|
||||
wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
|
||||
assign O6 = I0 ? s1[1] : s1[0];
|
||||
|
||||
wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
|
||||
wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
|
||||
wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
|
||||
wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
|
||||
assign O5 = I0 ? s5_1[1] : s5_1[0];
|
||||
endmodule
|
||||
|
||||
module MUXCY(output O, input CI, DI, S);
|
||||
assign O = S ? CI : DI;
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -28,12 +28,12 @@ function xtract_cell_decl()
|
|||
# xtract_cell_decl BUFG
|
||||
xtract_cell_decl BUFGCE
|
||||
xtract_cell_decl BUFGCE_1
|
||||
xtract_cell_decl BUFGCTRL
|
||||
#xtract_cell_decl BUFGCTRL
|
||||
xtract_cell_decl BUFGMUX
|
||||
xtract_cell_decl BUFGMUX_1
|
||||
xtract_cell_decl BUFGMUX_CTRL
|
||||
xtract_cell_decl BUFH
|
||||
xtract_cell_decl BUFHCE
|
||||
#xtract_cell_decl BUFHCE
|
||||
xtract_cell_decl BUFIO
|
||||
xtract_cell_decl BUFMR
|
||||
xtract_cell_decl BUFMRCE
|
||||
|
|
@ -92,7 +92,7 @@ function xtract_cell_decl()
|
|||
# xtract_cell_decl LUT4
|
||||
# xtract_cell_decl LUT5
|
||||
# xtract_cell_decl LUT6
|
||||
xtract_cell_decl LUT6_2
|
||||
#xtract_cell_decl LUT6_2
|
||||
xtract_cell_decl MMCME2_ADV
|
||||
xtract_cell_decl MMCME2_BASE
|
||||
# xtract_cell_decl MUXF7
|
||||
|
|
|
|||
|
|
@ -30,29 +30,6 @@ module BUFGCE_1 (...);
|
|||
input CE, I;
|
||||
endmodule
|
||||
|
||||
module BUFGCTRL (...);
|
||||
output O;
|
||||
input CE0;
|
||||
input CE1;
|
||||
input I0;
|
||||
input I1;
|
||||
input IGNORE0;
|
||||
input IGNORE1;
|
||||
input S0;
|
||||
input S1;
|
||||
parameter integer INIT_OUT = 0;
|
||||
parameter PRESELECT_I0 = "FALSE";
|
||||
parameter PRESELECT_I1 = "FALSE";
|
||||
parameter [0:0] IS_CE0_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_CE1_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_I0_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_I1_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S0_INVERTED = 1'b0;
|
||||
parameter [0:0] IS_S1_INVERTED = 1'b0;
|
||||
endmodule
|
||||
|
||||
module BUFGMUX (...);
|
||||
parameter CLK_SEL_TYPE = "SYNC";
|
||||
output O;
|
||||
|
|
@ -77,15 +54,6 @@ module BUFH (...);
|
|||
input I;
|
||||
endmodule
|
||||
|
||||
module BUFHCE (...);
|
||||
parameter CE_TYPE = "SYNC";
|
||||
parameter integer INIT_OUT = 0;
|
||||
parameter [0:0] IS_CE_INVERTED = 1'b0;
|
||||
output O;
|
||||
input CE;
|
||||
input I;
|
||||
endmodule
|
||||
|
||||
module BUFIO (...);
|
||||
output O;
|
||||
input I;
|
||||
|
|
@ -2420,12 +2388,6 @@ module LDPE (...);
|
|||
input D, G, GE, PRE;
|
||||
endmodule
|
||||
|
||||
module LUT6_2 (...);
|
||||
parameter [63:0] INIT = 64'h0000000000000000;
|
||||
input I0, I1, I2, I3, I4, I5;
|
||||
output O5, O6;
|
||||
endmodule
|
||||
|
||||
module MMCME2_ADV (...);
|
||||
parameter BANDWIDTH = "OPTIMIZED";
|
||||
parameter real CLKFBOUT_MULT_F = 5.000;
|
||||
|
|
|
|||
2
tests/aiger/.gitignore
vendored
Normal file
2
tests/aiger/.gitignore
vendored
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
*.log
|
||||
*.out
|
||||
Loading…
Add table
Add a link
Reference in a new issue