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https://github.com/YosysHQ/yosys
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simplify logic of handling flip-flops and latches
This commit is contained in:
Miodrag Milanovic
parent
61752b255f
commit
13a5c28459
1 changed files with 46 additions and 122 deletions
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@ -479,136 +479,60 @@ struct SimInstance
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ff_state_t &ff = it.second;
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ff_state_t &ff = it.second;
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FfData &ff_data = ff.data;
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FfData &ff_data = ff.data;
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Const current_q = get_state(ff.data.sig_q);
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if (ff_data.has_clk) {
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if (ff_data.has_clk) {
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// flip-flops
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// flip-flops
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State current_clk = get_state(ff_data.sig_clk)[0];
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State current_clk = get_state(ff_data.sig_clk)[0];
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if (ff_data.pol_clk ? (ff.past_clk == State::S0 && current_clk != State::S0) :
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// handle set/reset
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(ff.past_clk == State::S1 && current_clk != State::S1)) {
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if (ff.data.has_sr) {
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bool ce = ff.past_ce == (ff_data.pol_ce ? State::S1 : State::S0);
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Const current_q = get_state(ff.data.sig_q);
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Const current_clr = get_state(ff.data.sig_clr);
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Const current_set = get_state(ff.data.sig_set);
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for(int i=0;i<ff.past_d.size();i++) {
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if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
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current_q[i] = State::S0;
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}
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else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
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current_q[i] = State::S1;
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} else {
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// all below is in sync with clk
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if (ff_data.pol_clk ? (ff.past_clk == State::S1 || current_clk != State::S1) :
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(ff.past_clk == State::S0 || current_clk != State::S0))
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continue;
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if (ff_data.has_ce) {
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if (ff.past_ce == (ff_data.pol_ce ? State::S1 : State::S0))
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current_q[i] = ff.past_d[i];
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} else {
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current_q[i] = ff.past_d[i];
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}
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}
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}
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if (set_state(ff_data.sig_q, current_q))
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did_something = true;
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} else {
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// async reset
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if (ff_data.has_arst) {
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State current_arst = get_state(ff_data.sig_arst)[0];
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if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff_data.val_arst))
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did_something = true;
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continue;
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}
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}
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// async load
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if (ff_data.has_aload) {
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff.past_ad))
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did_something = true;
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continue;
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}
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}
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// all below is in sync with clk
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if (ff_data.pol_clk ? (ff.past_clk == State::S1 || current_clk != State::S1) :
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(ff.past_clk == State::S0 || current_clk != State::S0))
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continue;
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// chip enable priority over reset
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// chip enable priority over reset
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if (ff_data.ce_over_srst && ff_data.has_ce) {
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if (ff_data.ce_over_srst && ff_data.has_ce && !ce) continue;
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if (ff.past_ce != (ff_data.pol_ce ? State::S1 : State::S0))
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// set if no ce, or ce is enabled
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continue;
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if (!ff_data.has_ce || (ff_data.has_ce && ce)) {
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current_q = ff.past_d;
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}
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}
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// override if sync reset
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// handle sync reset
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if ((ff_data.has_srst) && (ff.past_srst == (ff_data.pol_srst ? State::S1 : State::S0))) {
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if (ff_data.has_srst) {
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current_q = ff_data.val_srst;
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if (ff.past_srst == (ff_data.pol_srst ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff_data.val_srst))
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did_something = true;
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continue;
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}
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}
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}
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// reset had priority over chip enable
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if (!ff_data.ce_over_srst && ff_data.has_ce) {
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if (ff.past_ce != (ff_data.pol_ce ? State::S1 : State::S0))
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continue;
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}
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if (set_state(ff_data.sig_q, ff.past_d))
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did_something = true;
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}
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} else {
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// handle set/reset
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if (ff.data.has_sr) {
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Const current_q = get_state(ff.data.sig_q);
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Const current_clr = get_state(ff.data.sig_clr);
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Const current_set = get_state(ff.data.sig_set);
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for(int i=0;i<current_q.size();i++) {
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if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
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current_q[i] = State::S0;
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}
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else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
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current_q[i] = State::S1;
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} else {
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if (ff_data.has_aload) {
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Const current_ad = get_state(ff.data.sig_ad);
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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current_q[i] = current_ad[i];
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}
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}
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}
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}
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if (set_state(ff_data.sig_q, current_q))
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did_something = true;
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}
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// async load is true for all latches
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else if (ff_data.has_aload) {
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// async reset
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if (ff_data.has_arst) {
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State current_arst = get_state(ff_data.sig_arst)[0];
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if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, ff_data.val_arst))
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did_something = true;
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continue;
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}
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}
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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if (set_state(ff_data.sig_q, get_state(ff.data.sig_ad)))
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did_something = true;
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}
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} else if (ff_data.has_gclk) {
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// $ff
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if (set_state(ff_data.sig_q, ff.past_d))
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did_something = true;
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}
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}
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}
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}
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// async load
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if (ff_data.has_aload) {
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State current_aload = get_state(ff_data.sig_aload)[0];
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if (current_aload == (ff_data.pol_aload ? State::S1 : State::S0)) {
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current_q = ff_data.has_clk ? ff.past_ad : get_state(ff.data.sig_ad);
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}
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}
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// async reset
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if (ff_data.has_arst) {
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State current_arst = get_state(ff_data.sig_arst)[0];
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if (current_arst == (ff_data.pol_arst ? State::S1 : State::S0)) {
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current_q = ff_data.val_arst;
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}
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}
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// handle set/reset
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if (ff.data.has_sr) {
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Const current_clr = get_state(ff.data.sig_clr);
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Const current_set = get_state(ff.data.sig_set);
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for(int i=0;i<ff.past_d.size();i++) {
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if (current_clr[i] == (ff_data.pol_clr ? State::S1 : State::S0)) {
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current_q[i] = State::S0;
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}
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else if (current_set[i] == (ff_data.pol_set ? State::S1 : State::S0)) {
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current_q[i] = State::S1;
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}
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}
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}
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if (ff_data.has_gclk) {
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// $ff
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current_q = ff.past_d;
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}
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if (set_state(ff_data.sig_q, current_q))
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did_something = true;
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}
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}
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for (auto &it : mem_database)
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for (auto &it : mem_database)
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