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https://github.com/YosysHQ/yosys
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Get rid of normalize_to_width.
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parent
c44d24d9fd
commit
135c2a4113
3 changed files with 8 additions and 27 deletions
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@ -43,23 +43,6 @@ std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpe
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return {sum, carry};
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return {sum, carry};
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}
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}
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SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
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{
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// Zero/sign-extend to width
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if (GetSize(sig) < width) {
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SigBit pad;
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if (is_signed && GetSize(sig) > 0)
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pad = sig[GetSize(sig) - 1];
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else
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pad = State::S0;
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sig.append(SigSpec(pad, width - GetSize(sig)));
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}
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// Truncate to width
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if (GetSize(sig) > width)
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sig = sig.extract(0, width);
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return sig;
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}
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std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
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std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
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int width_a = GetSize(a);
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int width_a = GetSize(a);
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int width_b = GetSize(b);
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int width_b = GetSize(b);
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@ -72,7 +55,7 @@ std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSp
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// b_shifted = (0_i ## b)
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// b_shifted = (0_i ## b)
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SigSpec b_shifted = SigSpec(State::S0, i);
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SigSpec b_shifted = SigSpec(State::S0, i);
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b_shifted.append(b);
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b_shifted.append(b);
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b_shifted = normalize_to_width(b_shifted, false, width);
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b_shifted.extend_u0(width, false);
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// row = b_shifted & replicate(a[i], width)
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// row = b_shifted & replicate(a[i], width)
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SigSpec ai_rep = SigSpec(ai, width);
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SigSpec ai_rep = SigSpec(ai, width);
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@ -333,8 +316,8 @@ FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode) {
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case FinalMode::PREFIX: return FinalAdder::PARALLEL_PREFIX;
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case FinalMode::PREFIX: return FinalAdder::PARALLEL_PREFIX;
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case FinalMode::AUTO:
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case FinalMode::AUTO:
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default: {
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default: {
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bool wide = width >= RIPPLE_PREFIX_THRESHOLD;
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bool wide = width >= RIPPLE_PREFIX_WIDTH_THRESHOLD;
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bool deep = final_depth >= PREFIX_DEPTH_THRESHOLD;
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bool deep = final_depth >= RIPPLE_PREFIX_DEPTH_THRESHOLD;
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return (wide && deep) ? FinalAdder::PARALLEL_PREFIX : FinalAdder::DEFAULT;
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return (wide && deep) ? FinalAdder::PARALLEL_PREFIX : FinalAdder::DEFAULT;
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}
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}
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}
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}
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@ -30,8 +30,8 @@ namespace CompressorTree
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{
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{
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// Width and depth thresholds below which a ripple is preferred over parallel-prefix
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// Width and depth thresholds below which a ripple is preferred over parallel-prefix
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constexpr int RIPPLE_PREFIX_THRESHOLD = 16;
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constexpr int RIPPLE_PREFIX_WIDTH_THRESHOLD = 16;
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constexpr int PREFIX_DEPTH_THRESHOLD = 5;
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constexpr int RIPPLE_PREFIX_DEPTH_THRESHOLD = 5;
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enum class Strategy {
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enum class Strategy {
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FA_ONLY, // 3:2 compressors
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FA_ONLY, // 3:2 compressors
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@ -59,8 +59,6 @@ enum class FinalMode {
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std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
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std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
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std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
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std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
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SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width);
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/**
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/**
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* generate_partial_products() - Generate partial products for FMA concat
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* generate_partial_products() - Generate partial products for FMA concat
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* @module:The Yosys module to which the compressors will be added
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* @module:The Yosys module to which the compressors will be added
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@ -304,10 +304,10 @@ struct ArithTreeWorker {
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for (auto &op : operands) {
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for (auto &op : operands) {
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if (GetSize(op.factor_b) == 0) {
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if (GetSize(op.factor_b) == 0) {
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// Additive operand
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// Additive operand
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SigSpec s = CompressorTree::normalize_to_width(op.sig, op.is_signed, width);
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op.sig.extend_u0(width, op.is_signed);
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if (op.negate)
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if (op.negate)
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s = module->Not(NEW_ID, s);
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op.sig = module->Not(NEW_ID, op.sig);
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pool.push_back({s, 0});
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pool.push_back({op.sig, 0});
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} else {
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} else {
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// Multiplicative operand
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// Multiplicative operand
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auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
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auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
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