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Added GP_PGA cell

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Andrew Zonenberg 2016-04-27 23:07:21 -07:00
parent 0d2923cccd
commit 134e093e4e
1 changed files with 11 additions and 0 deletions
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11
techlibs/greenpak4/cells_sim.v
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@ -153,6 +153,17 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
endmodule endmodule
module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
parameter GAIN = 1;
parameter INPUT_MODE = "SINGLE";
initial VOUT = 0;
//cannot simulate mixed signal IP
endmodule
module GP_POR(output reg RST_DONE); module GP_POR(output reg RST_DONE);
parameter POR_TIME = 500; parameter POR_TIME = 500;