3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-12 14:11:00 +00:00

Add tests for ecp5 architecture.

This commit is contained in:
SergeyDegtyar 2019-08-27 18:12:18 +03:00
parent aad9bad326
commit 134d3fea90
31 changed files with 865 additions and 0 deletions

8
tests/ecp5/add_sub.ys Normal file
View file

@ -0,0 +1,8 @@
read_verilog add_sub.v
hierarchy -top top
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 10 t:LUT4
select -assert-none t:LUT4 %% t:* %D