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https://github.com/YosysHQ/yosys
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Initial implementation of synthesizable assertions
This commit is contained in:
Miodrag Milanovic
parent
4c334b905f
commit
131b557727
2 changed files with 231 additions and 0 deletions
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@ -19,3 +19,4 @@ OBJS += passes/sat/fminit.o
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ifeq ($(DISABLE_SPAWN),0)
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OBJS += passes/sat/qbfsat.o
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endif
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OBJS += passes/sat/synthprop.o
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230
passes/sat/synthprop.cc
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230
passes/sat/synthprop.cc
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@ -0,0 +1,230 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Miodrag Milanovic <micko@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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YOSYS_NAMESPACE_BEGIN
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struct TrackingItem
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{
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pool<Cell*> assertion_cells;
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std::vector<std::string> names;
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};
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typedef dict<RTLIL::Module*, TrackingItem> TrackingData;
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struct SynthPropWorker
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{
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// pointer to main design
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RTLIL::Design *design;
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RTLIL::IdString top_name;
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RTLIL::Module *module;
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std::string map_file;
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bool or_outputs;
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IdString port_name;
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// basic contrcutor
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SynthPropWorker(RTLIL::Design *design) : design(design), or_outputs(false), port_name(RTLIL::escape_id("assertions")) {}
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void tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path);
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void run();
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};
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void SynthPropWorker::tracing(RTLIL::Module *mod, int depth, TrackingData &tracing_data, std::string hier_path)
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{
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log("%*sTracing in module %s..\n", 2*depth, "", log_id(mod));
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tracing_data[mod] = TrackingItem();
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int cnt = 0;
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for (auto cell : mod->cells()) {
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if (cell->type == ID($assert)) {
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log("%*sFound assert %s..\n", 2*(depth+1), "", log_id(cell));
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tracing_data[mod].assertion_cells.emplace(cell);
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if (!or_outputs) {
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tracing_data[mod].names.push_back(hier_path + "." + log_id(cell));
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}
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cnt++;
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}
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else if (RTLIL::Module *submod = design->module(cell->type)) {
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tracing(submod, depth+1, tracing_data, hier_path + "." + log_id(cell));
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if (!or_outputs) {
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for (size_t i = 0; i < tracing_data[submod].names.size(); i++)
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tracing_data[mod].names.push_back(tracing_data[submod].names[i]);
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} else {
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cnt += tracing_data[submod].names.size();
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}
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}
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}
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if (or_outputs && (cnt > 0)) {
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tracing_data[mod].names.push_back("merged_asserts");
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}
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}
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void SynthPropWorker::run()
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{
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if (!module->get_bool_attribute(ID::top))
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log_error("Module is not TOP module\n");
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TrackingData tracing_data;
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tracing(module, 0, tracing_data, log_id(module->name));
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for (auto &data : tracing_data) {
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if (data.second.names.size() == 0) continue;
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RTLIL::Wire *wire = data.first->addWire(port_name, data.second.names.size());
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wire->port_output = true;
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data.first->fixup_ports();
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}
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for (auto &data : tracing_data) {
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int num = 0;
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RTLIL::Wire *port_wire = data.first->wire(port_name);
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pool<Wire*> connected;
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for (auto cell : data.second.assertion_cells) {
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if (cell->type == ID($assert)) {
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RTLIL::Wire *neg_wire = data.first->addWire(NEW_ID);
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RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
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data.first->addNot(NEW_ID, cell->getPort(ID::A), neg_wire);
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data.first->addAnd(NEW_ID, cell->getPort(ID::EN), neg_wire, result_wire);
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if (!or_outputs) {
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data.first->connect(SigBit(port_wire,num), result_wire);
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} else {
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connected.emplace(result_wire);
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}
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num++;
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}
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}
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for (auto cell : data.first->cells()) {
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if (RTLIL::Module *submod = design->module(cell->type)) {
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if (tracing_data[submod].names.size() > 0) {
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if (!or_outputs) {
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cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size()));
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} else {
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RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
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cell->setPort(port_name, result_wire);
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connected.emplace(result_wire);
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}
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num += tracing_data[submod].names.size();
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}
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}
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}
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if (or_outputs && connected.size() > 0) {
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RTLIL::Wire *prev_wire = nullptr;
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for (auto wire : connected ) {
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if (!prev_wire) {
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prev_wire = wire;
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} else {
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RTLIL::Wire *result = data.first->addWire(NEW_ID);
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data.first->addOr(NEW_ID, prev_wire, wire, result);
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prev_wire = result;
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}
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}
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data.first->connect(port_wire, prev_wire);
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}
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}
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if (!map_file.empty()) {
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std::ofstream fout;
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fout.open(map_file, std::ios::out | std::ios::trunc);
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if (!fout.is_open())
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log_error("Could not open file \"%s\" with write access.\n", map_file.c_str());
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for (auto name : tracing_data[module].names) {
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fout << name << std::endl;
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}
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}
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}
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struct SyntProperties : public Pass {
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SyntProperties() : Pass("synthprop", "synthesize SVA properties") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synthprop [options]\n");
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log("\n");
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log("This creates synthesizable properties for selected module.\n");
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log("\n");
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log("\n");
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log(" -name <port_name>\n");
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log("\n");
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log("Name output port for assertions (default: assertions).\n");
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log("\n");
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log("\n");
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log(" -map <filename>\n");
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log("\n");
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log("Write port mapping for synthesizable properties.\n");
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log("\n");
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log("\n");
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log(" -or_outputs\n");
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log("\n");
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log("Or all outputs together to create a single output that goes high when any\n");
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log("property is violated, instead of generating individual output bits.\n");
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log("\n");
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log("\n");
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log(" -latch <reset_signal_name> <polarity>\n");
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log("\n");
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log("Latch a high state on the generated outputs until an asynchronous top-level\n");
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log("reset input is activated.\n");
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log("\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design* design)
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{
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log_header(design, "Executing SYNTHPROP pass.\n");
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SynthPropWorker worker(design);
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-name" && argidx+1 < args.size()) {
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worker.port_name = RTLIL::escape_id(args[++argidx]);
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continue;
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}
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if (args[argidx] == "-map" && argidx+1 < args.size()) {
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worker.map_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-latch" && argidx+2 < args.size()) {
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continue;
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}
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if (args[argidx] == "-or_outputs") {
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worker.or_outputs = true;
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continue;
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}
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break;
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}
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if (args.size() != argidx)
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cmd_error(args, argidx, "Extra argument.");
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auto *top = design->top_module();
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if (top == nullptr)
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log_cmd_error("Can't find top module in current design!\n");
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worker.module = top;
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worker.run();
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}
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} SyntProperties;
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YOSYS_NAMESPACE_END
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