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example_synth: more on hierarchy and stat

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Krystine Sherwin 2024-01-13 17:46:04 +13:00
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docs/source/code_examples/fifo/fifo.stat Normal file
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yosys> stat
2. Printing statistics.
=== fifo ===
Number of wires: 28
Number of wire bits: 219
Number of public wires: 9
Number of public wire bits: 45
Number of memories: 1
Number of memory bits: 2048
Number of processes: 3
Number of cells: 9
$add 1
$logic_and 2
$logic_not 2
$memrd 1
$sub 1
addr_gen 2
=== addr_gen ===
Number of wires: 8
Number of wire bits: 60
Number of public wires: 4
Number of public wire bits: 11
Number of memories: 0
Number of memory bits: 0
Number of processes: 2
Number of cells: 2
$add 1
$eq 1
yosys> stat -top fifo
16. Printing statistics.
=== fifo ===
Number of wires: 97
Number of wire bits: 268
Number of public wires: 97
Number of public wire bits: 268
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 138
SB_CARRY 26
SB_DFF 26
SB_DFFER 25
SB_LUT4 60
SB_RAM40_4K 1