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example_synth: more on hierarchy and stat

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Krystine Sherwin 2024-01-13 17:46:04 +13:00
parent a3255fd8d3
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3 changed files with 102 additions and 4 deletions
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56
docs/source/code_examples/fifo/fifo.stat Normal file
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@ -0,0 +1,56 @@
yosys> stat
2. Printing statistics.
=== fifo ===
Number of wires: 28
Number of wire bits: 219
Number of public wires: 9
Number of public wire bits: 45
Number of memories: 1
Number of memory bits: 2048
Number of processes: 3
Number of cells: 9
$add 1
$logic_and 2
$logic_not 2
$memrd 1
$sub 1
addr_gen 2
=== addr_gen ===
Number of wires: 8
Number of wire bits: 60
Number of public wires: 4
Number of public wire bits: 11
Number of memories: 0
Number of memory bits: 0
Number of processes: 2
Number of cells: 2
$add 1
$eq 1
yosys> stat -top fifo
16. Printing statistics.
=== fifo ===
Number of wires: 97
Number of wire bits: 268
Number of public wires: 97
Number of public wire bits: 268
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 138
SB_CARRY 26
SB_DFF 26
SB_DFFER 25
SB_LUT4 60
SB_RAM40_4K 1

7
docs/source/code_examples/fifo/fifo_map.ys
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@ -1,4 +1,7 @@
read_verilog fifo.v
echo on
tee -o fifo.stat stat
echo off
synth_ice40 -top fifo -run begin:map_ram
# this point should be the same as rdata_coarse
@ -45,3 +48,7 @@ show -color maroon3 t:SB_CARRY -color cornflowerblue t:$lut -notitle -format dot
synth_ice40 -top fifo -run map_cells:
select -set rdata_path t:SB_RAM40_4K %ci*:-SB_RAM40_4K[WCLKE,WDATA,WADDR,WE] t:SB_RAM40_4K %co* %%
show -color maroon3 t:SB_LUT* -notitle -format dot -prefix rdata_map_cells @rdata_path
echo on
tee -a fifo.stat stat -top fifo
echo off