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xilinx: improve specify functionality
This commit is contained in:
Eddie Hung
parent
46a89d7264
commit
12d70ca8fb
8 changed files with 547 additions and 466 deletions
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@ -398,8 +398,8 @@ module RAM32X1D (
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4),
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.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4)
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);
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$__ABC9_LUT6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
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$__ABC9_LUT6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
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$__ABC9_RAM6 spo (.A($SPO), .S({1'b1, A4, A3, A2, A1, A0}), .Y(SPO));
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$__ABC9_RAM6 dpo (.A($DPO), .S({1'b1, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
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endmodule
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module RAM64X1D (
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@ -421,8 +421,8 @@ module RAM64X1D (
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5),
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.DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .DPRA4(DPRA4), .DPRA5(DPRA5)
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);
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$__ABC9_LUT6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
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$__ABC9_LUT6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
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$__ABC9_RAM6 spo (.A($SPO), .S({A5, A4, A3, A2, A1, A0}), .Y(SPO));
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$__ABC9_RAM6 dpo (.A($DPO), .S({DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}), .Y(DPO));
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endmodule
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module RAM128X1D (
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@ -443,8 +443,8 @@ module RAM128X1D (
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.A(A),
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.DPRA(DPRA)
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);
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$__ABC9_LUT7 spo (.A($SPO), .S(A), .Y(SPO));
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$__ABC9_LUT7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
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$__ABC9_RAM7 spo (.A($SPO), .S(A), .Y(SPO));
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$__ABC9_RAM7 dpo (.A($DPO), .S(DPRA), .Y(DPO));
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endmodule
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module RAM32M (
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@ -478,14 +478,14 @@ module RAM32M (
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.ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
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.DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
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);
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$__ABC9_LUT6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
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$__ABC9_LUT6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
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$__ABC9_LUT6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
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$__ABC9_LUT6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
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$__ABC9_LUT6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
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$__ABC9_LUT6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
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$__ABC9_LUT6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
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$__ABC9_LUT6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
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$__ABC9_RAM6 doa0 (.A($DOA[0]), .S({1'b1, ADDRA}), .Y(DOA[0]));
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$__ABC9_RAM6 doa1 (.A($DOA[1]), .S({1'b1, ADDRA}), .Y(DOA[1]));
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$__ABC9_RAM6 dob0 (.A($DOB[0]), .S({1'b1, ADDRB}), .Y(DOB[0]));
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$__ABC9_RAM6 dob1 (.A($DOB[1]), .S({1'b1, ADDRB}), .Y(DOB[1]));
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$__ABC9_RAM6 doc0 (.A($DOC[0]), .S({1'b1, ADDRC}), .Y(DOC[0]));
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$__ABC9_RAM6 doc1 (.A($DOC[1]), .S({1'b1, ADDRC}), .Y(DOC[1]));
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$__ABC9_RAM6 dod0 (.A($DOD[0]), .S({1'b1, ADDRD}), .Y(DOD[0]));
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$__ABC9_RAM6 dod1 (.A($DOD[1]), .S({1'b1, ADDRD}), .Y(DOD[1]));
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endmodule
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module RAM64M (
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@ -519,10 +519,25 @@ module RAM64M (
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.ADDRA(ADDRA), .ADDRB(ADDRB), .ADDRC(ADDRC), .ADDRD(ADDRD),
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.DIA(DIA), .DIB(DIB), .DIC(DIC), .DID(DID)
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);
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$__ABC9_LUT6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
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$__ABC9_LUT6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
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$__ABC9_LUT6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
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$__ABC9_LUT6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
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$__ABC9_RAM6 doa (.A($DOA), .S(ADDRA), .Y(DOA));
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$__ABC9_RAM6 dob (.A($DOB), .S(ADDRB), .Y(DOB));
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$__ABC9_RAM6 doc (.A($DOC), .S(ADDRC), .Y(DOC));
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$__ABC9_RAM6 dod (.A($DOD), .S(ADDRD), .Y(DOD));
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endmodule
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module SRL16 (
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output Q,
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(* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
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);
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parameter [15:0] INIT = 16'h0000;
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wire $Q;
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SRL16 #(
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.INIT(INIT),
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) _TECHMAP_REPLACE_ (
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.Q($Q),
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
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);
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$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
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endmodule
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module SRL16E (
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@ -538,7 +553,38 @@ module SRL16E (
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.Q($Q),
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
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);
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$__ABC9_LUT6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
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$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
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endmodule
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module SRLC16 (
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output Q, Q15,
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(* techmap_autopurge *) input A0, A1, A2, A3, CLK, D
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);
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parameter [15:0] INIT = 16'h0000;
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wire $Q;
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SRLC16 #(
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.INIT(INIT),
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) _TECHMAP_REPLACE_ (
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.Q($Q), .Q(Q15),
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CLK(CLK), .D(D)
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);
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$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
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endmodule
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module SRLC16E (
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output Q, Q15,
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(* techmap_autopurge *) input A0, A1, A2, A3, CE, CLK, D
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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wire $Q;
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SRLC16E #(
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.INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
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) _TECHMAP_REPLACE_ (
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.Q($Q), .Q(Q15),
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.A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
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);
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$__ABC9_RAM6 q (.A($Q), .S({1'b1, A3, A2, A1, A0, 1'b1}), .Y(Q));
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endmodule
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module SRLC32E (
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@ -556,7 +602,7 @@ module SRLC32E (
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.Q($Q), .Q31(Q31),
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.A(A), .CE(CE), .CLK(CLK), .D(D)
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);
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$__ABC9_LUT6 q (.A($Q), .S({1'b1, A}), .Y(Q));
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$__ABC9_RAM6 q (.A($Q), .S({1'b1, A}), .Y(Q));
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endmodule
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module DSP48E1 (
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@ -55,6 +55,7 @@ module \$__ABC9_ASYNC0 (input A, S, output Y);
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assign Y = S ? 1'b0 : A;
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specify
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(A => Y) = 0;
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// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
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(S => Y) = 764;
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endspecify
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endmodule
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@ -65,6 +66,7 @@ module \$__ABC9_ASYNC1 (input A, S, output Y);
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assign Y = S ? 1'b1 : A;
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specify
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(A => Y) = 0;
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// https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270
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(S => Y) = 764;
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endspecify
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endmodule
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@ -76,7 +78,7 @@ endmodule
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// To model the combinatorial path, such cells have to be split
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// into comb and seq parts, with this box modelling only the former.
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(* abc9_box *)
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module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
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module \$__ABC9_RAM6 (input A, input [5:0] S, output Y);
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specify
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(S[0] => Y) = 642;
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(S[1] => Y) = 631;
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@ -88,7 +90,7 @@ module \$__ABC9_LUT6 (input A, input [5:0] S, output Y);
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endmodule
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// Box to emulate comb/seq behaviour of RAM128
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(* abc9_box *)
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module \$__ABC9_LUT7 (input A, input [6:0] S, output Y);
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module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
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specify
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(S[0] => Y) = 1028;
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(S[1] => Y) = 1017;
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@ -29,10 +29,10 @@ module $__ABC9_FF_(input D, output Q);
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assign Q = D;
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endmodule
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module $__ABC9_LUT6(input A, input [5:0] S, output Y);
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module $__ABC9_RAM6(input A, input [5:0] S, output Y);
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assign Y = A;
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endmodule
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module $__ABC9_LUT7(input A, input [6:0] S, output Y);
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module $__ABC9_RAM7(input A, input [6:0] S, output Y);
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assign Y = A;
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endmodule
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File diff suppressed because it is too large
Load diff
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@ -619,8 +619,8 @@ struct SynthXilinxPass : public ScriptPass
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if (dff_mode)
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techmap_args += " -D DFF_MODE";
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run("techmap " + techmap_args);
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run("read_verilog -icells -specify -lib +/xilinx/abc9_model.v");
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std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
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run("read_verilog -icells -lib -specify +/xilinx/abc9_model.v");
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std::string abc9_opts;
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auto k = stringf("synth_xilinx.abc9.%s.W", family.c_str());
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if (active_design->scratchpad.count(k))
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abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
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