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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"

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This reverts commit c851dc1310, reversing
changes made to f54bf1631f.
This commit is contained in:
Eddie Hung 2019-08-12 12:06:45 -07:00
parent 78b30bbb11
commit 12c692f6ed
20 changed files with 181 additions and 181 deletions
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tests/opt/opt_rmdff.ys Normal file
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read_verilog -icells opt_rmdff.v
prep
design -stash gold
read_verilog -icells opt_rmdff.v
proc
opt_rmdff
select -assert-count 0 c:remove*
select -assert-min 7 c:keep*
select -assert-count 0 t:$dffe 7:$_DFFE_* %u c:noenable* %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
equiv_make gold gate equiv
hierarchy -top equiv
equiv_simple -undef
equiv_status -assert
design -load gold
stat
design -load gate
stat