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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commitc851dc1310, reversing changes made tof54bf1631f.
This commit is contained in:
Eddie Hung
parent
78b30bbb11
commit
12c692f6ed
20 changed files with 181 additions and 181 deletions
223
tests/opt/opt_expr.ys
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223
tests/opt/opt_expr.ys
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read_verilog <<EOT
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module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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dump
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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endmodule
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EOT
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alumacc
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opt_expr -fine
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
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assign o = 5'b00010 - i;
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endmodule
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EOT
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wreduce
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
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assign o = 5'b00010 - i;
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endmodule
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EOT
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wreduce
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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