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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commitc851dc1310, reversing changes made tof54bf1631f.
This commit is contained in:
Eddie Hung
parent
78b30bbb11
commit
12c692f6ed
20 changed files with 181 additions and 181 deletions
223
tests/opt/opt_expr.ys
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223
tests/opt/opt_expr.ys
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@ -0,0 +1,223 @@
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read_verilog <<EOT
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module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = (i << 4) + j;
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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dump
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
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assign o = j - (i << 4);
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endmodule
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EOT
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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endmodule
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EOT
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
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assign o = (i << 4) - j;
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endmodule
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EOT
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alumacc
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opt_expr -fine
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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##########
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
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assign o = 5'b00010 - i;
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endmodule
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EOT
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wreduce
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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##########
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# alumacc version of above
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design -reset
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read_verilog <<EOT
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module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
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assign o = 5'b00010 - i;
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endmodule
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EOT
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wreduce
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alumacc
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt -assert opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
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###########
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design -reset
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read_verilog -icells <<EOT
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module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
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\$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
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endmodule
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EOT
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check
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
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@ -1,21 +0,0 @@
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module top(
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input clk,
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input rst,
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input [2:0] a,
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output [1:0] b
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);
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reg [2:0] b_reg;
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initial begin
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b_reg <= 3'b0;
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end
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assign b = b_reg[1:0];
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always @(posedge clk or posedge rst) begin
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if(rst) begin
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b_reg <= 3'b0;
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end else begin
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b_reg <= a;
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end
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end
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endmodule
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@ -1,3 +0,0 @@
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read_verilog opt_ff.v
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synth_ice40
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ice40_unlut
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@ -1,4 +1,2 @@
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read_verilog opt_lut.v
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synth_ice40
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ice40_unlut
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equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
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equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40
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50
tests/opt/opt_rmdff.v
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50
tests/opt/opt_rmdff.v
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module opt_rmdff_test (input C, input D, input E, output [29:0] Q);
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove0 (.CLK(C), .D(D), .EN(1'b0), .Q(Q[0])); // EN is never active
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(* init = "1'b1" *) wire Q1; assign Q[1] = Q1;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove1 (.CLK(C), .D(D), .EN(1'b0), .Q(Q1)); // EN is never active
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove2 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[2])); // EN is don't care
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep3 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[3])); // EN is always active
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(* init = "1'b0" *) wire Q4; assign Q[4] = Q4;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) keep4 (.CLK(C), .D(D), .EN(1'b1), .Q(Q4)); // EN is always active
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove5 (.CLK(C), .D(D), .EN(1'b1), .Q(Q[5])); // EN is never active
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove6 (.CLK(C), .D(D), .EN(1'bx), .Q(Q[6])); // EN is don't care
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(* init = "1'b0" *) wire Q7; assign Q[7] = Q7;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(0)) keep7 (.CLK(C), .D(D), .EN(E), .Q(Q7)); // EN is non constant
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\$_DFFE_PP_ remove8 (.C(C), .D(D), .E(1'b0), .Q(Q[8])); // EN is never active
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(* init = "1'b1" *) wire Q9; assign Q[9] = Q9;
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\$_DFFE_PP_ remove9 (.C(C), .D(D), .E(1'b0), .Q(Q9)); // EN is never active
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\$_DFFE_PP_ remove10 (.C(C), .D(D), .E(1'bx), .Q(Q[10])); // EN is don't care
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\$_DFFE_PP_ keep11 (.C(C), .D(D), .E(1'b1), .Q(Q[11])); // EN is always active
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(* init = "1'b0" *) wire Q12; assign Q[12] = Q12;
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\$_DFFE_PP_ keep12 (.C(C), .D(D), .E(1'b1), .Q(Q12)); // EN is always active
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\$_DFFE_NN_ remove13 (.C(C), .D(D), .E(1'b1), .Q(Q[13])); // EN is never active
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(* init = "1'b1" *) wire Q14; assign Q[14] = Q14;
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\$_DFFE_NN_ remove14 (.C(C), .D(D), .E(1'b1), .Q(Q14)); // EN is never active
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\$_DFFE_NN_ remove15 (.C(C), .D(D), .E(1'bx), .Q(Q[15])); // EN is don't care
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\$_DFFE_NN_ keep16 (.C(C), .D(D), .E(1'b0), .Q(Q[16])); // EN is always active
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(* init = "1'b0" *) wire Q17; assign Q[17] = Q17;
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\$_DFFE_NN_ keep17 (.C(C), .D(D), .E(1'b0), .Q(Q17)); // EN is always active
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove18 (.CLK(1'b0), .D(D), .EN(E), .Q(Q[18])); // CLK is constant
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(* init = "1'b1" *) wire Q19; assign Q[19] = Q19;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove19 (.CLK(1'b1), .D(D), .EN(E), .Q(Q19)); // CLK is constant
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove20 (.CLK(C), .D(1'bx), .EN(E), .Q(Q[20])); // D is undriven, Q has no initial value
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(* init = "1'b0" *) wire Q21; assign Q[21] = Q21;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep21 (.CLK(C), .D(1'bx), .EN(E), .Q(Q21)); // D is undriven, Q has initial value
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//\$dffe #(.WIDTH(1), .CLK_POLARITY(0), .EN_POLARITY(1)) remove22 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q[22])); // D is constant, no initial Q value, EN is always active
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// // (TODO, Q starts with 1'bx and becomes 1'b0)
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(* init = "1'b0" *) wire Q23; assign Q[23] = Q23;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) noenable23 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q23)); // D is constant, initial Q value same as D, EN is always active
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(* init = "1'b1" *) wire Q24; assign Q[24] = Q24;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) keep24 (.CLK(C), .D(1'b0), .EN(1'b0), .Q(Q24)); // D is constant, initial Q value NOT same as D, EN is always active
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(* init = "1'b1" *) wire Q25; assign Q[25] = Q25;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove25 (.CLK(C), .D(1'b0), .EN(1'b1), .Q(Q25)); // D is constant, EN is never active
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) remove26 (.CLK(C), .D(Q[26]), .EN(1'b1), .Q(Q[26])); // D is Q, EN is always active
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove27 (.CLK(C), .D(Q[27]), .EN(1'b1), .Q(Q[27])); // D is Q, EN is never active, but no initial value
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(0)) remove28 (.CLK(C), .D(Q[28]), .EN(E), .Q(Q[28])); // EN is nonconst, but no initial value
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(* init = "1'b1" *) wire Q29; assign Q[29] = Q29;
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\$dffe #(.WIDTH(1), .CLK_POLARITY(1), .EN_POLARITY(1)) keep29 (.CLK(C), .D(Q[29]), .EN(1'b1), .Q(Q29)); // EN is always active, but with initial value
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endmodule
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26
tests/opt/opt_rmdff.ys
Normal file
26
tests/opt/opt_rmdff.ys
Normal file
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@ -0,0 +1,26 @@
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read_verilog -icells opt_rmdff.v
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prep
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design -stash gold
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read_verilog -icells opt_rmdff.v
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proc
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opt_rmdff
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select -assert-count 0 c:remove*
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select -assert-min 7 c:keep*
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select -assert-count 0 t:$dffe 7:$_DFFE_* %u c:noenable* %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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equiv_make gold gate equiv
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hierarchy -top equiv
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equiv_simple -undef
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equiv_status -assert
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design -load gold
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stat
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design -load gate
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stat
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@ -1,4 +1,4 @@
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read_verilog opt_ff_sat.v
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read_verilog opt_rmdff_sat.v
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prep -flatten
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opt_rmdff -sat
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synth
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