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Support param. default values in JSON FE and SV BE

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This commit is contained in:
Gus Smith 2022-06-22 10:57:46 -07:00
parent e3db8fee6f
commit 12ace45b89
3 changed files with 15 additions and 1 deletions
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11
backends/verilog/verilog_backend.cc
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@ -421,6 +421,14 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
}
}
void dump_parameter(std::ostream &f, std::string indent, RTLIL::IdString id_string, RTLIL::Const parameter)
{
f << stringf("%sparameter %s", indent.c_str(), id(id_string).c_str());
f << stringf(" = ");
dump_const(f, parameter);
f << stringf(";\n");
}
void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
{
dump_attributes(f, indent, wire->attributes, "\n", /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name));
@ -2438,6 +2446,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
}
for (auto p : module->parameter_default_values)
dump_parameter(f, indent + " ", p.first, p.second);
// first dump input / output according to their order in module->ports
for (auto port : module->ports)
dump_wire(f, indent + " ", module->wire(port));