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Fix handling of Verilog ~& and ~| operators

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Clifford Wolf 2017-06-01 12:43:21 +02:00
parent 0290b68a44
commit 129984e115
1 changed files with 8 additions and 0 deletions
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8
frontends/verilog/verilog_parser.y
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@ -1537,10 +1537,18 @@ basic_expr:
$$ = new AstNode(AST_BIT_AND, $1, $4); $$ = new AstNode(AST_BIT_AND, $1, $4);
append_attr($$, $3); append_attr($$, $3);
} | } |
basic_expr OP_NAND attr basic_expr {
$$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_AND, $1, $4));
append_attr($$, $3);
} |
basic_expr '|' attr basic_expr { basic_expr '|' attr basic_expr {
$$ = new AstNode(AST_BIT_OR, $1, $4); $$ = new AstNode(AST_BIT_OR, $1, $4);
append_attr($$, $3); append_attr($$, $3);
} | } |
basic_expr OP_NOR attr basic_expr {
$$ = new AstNode(AST_BIT_NOT, new AstNode(AST_BIT_OR, $1, $4));
append_attr($$, $3);
} |
basic_expr '^' attr basic_expr { basic_expr '^' attr basic_expr {
$$ = new AstNode(AST_BIT_XOR, $1, $4); $$ = new AstNode(AST_BIT_XOR, $1, $4);
append_attr($$, $3); append_attr($$, $3);