mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-18 13:15:46 +00:00
Code Activity

fix compilation err

Browse source
This commit is contained in:
Stan Lee 2026-04-17 10:29:13 -07:00
parent e7ffe7a7df
commit 1298607d95
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/sat/sim.cc
View file

@ -1285,7 +1285,7 @@ struct SimInstance
Const vcd_val = Const::from_string(shared->fst->valueOf(item.second));
Const sim_val = get_state(wire);
if (sim_val != vcd_val) {
if (debug)
if (shared->debug)
log_warning("Register mismatch at time %lu%s for %s.%s: "
"sim=%s vcd=%s, overwriting...\n",
(unsigned long)time,