mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-08 23:23:25 +00:00
Code Activity

Added read_verilog -norestrict -assume-asserts

Browse source
This commit is contained in:
Clifford Wolf 2016-08-26 23:35:27 +02:00
parent 17233b11e1
commit 1276c87a56
4 changed files with 40 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

18
frontends/verilog/verilog_frontend.cc
View file

@ -63,9 +63,15 @@ struct VerilogFrontend : public Frontend {
log(" of SystemVerilog is supported)\n");
log("\n");
log(" -formal\n");
log(" enable support for assert() and assume() from SystemVerilog\n");
log(" enable support for SystemVerilog assertions and some Yosys extensions\n");
log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
log("\n");
log(" -norestrict\n");
log(" ignore restrict() assertions\n");
log("\n");
log(" -assume-asserts\n");
log(" treat all assert() statements like assume() statements\n");
log("\n");
log(" -dump_ast1\n");
log(" dump abstract syntax tree (before simplification)\n");
log("\n");
@ -190,6 +196,8 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yydebug = false;
sv_mode = false;
formal_mode = false;
norestrict_mode = false;
assume_asserts_mode = false;
lib_mode = false;
default_nettype_wire = true;
@ -208,6 +216,14 @@ struct VerilogFrontend : public Frontend {
formal_mode = true;
continue;
}
if (arg == "-norestrict") {
norestrict_mode = true;
continue;
}
if (arg == "-assume-asserts") {
assume_asserts_mode = true;
continue;
}
if (arg == "-dump_ast1") {
flag_dump_ast1 = true;
continue;