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Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"

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Clifford Wolf 2016-05-06 14:32:32 +02:00
parent aadca148da
commit 126da0ad3d
1 changed files with 15 additions and 3 deletions
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18
techlibs/ice40/ice40_opt.cc
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@ -26,7 +26,7 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
static void run_ice40_opts(Module *module) static void run_ice40_opts(Module *module, bool unlut_mode)
{ {
pool<SigBit> optimized_co; pool<SigBit> optimized_co;
vector<Cell*> sb_lut_cells; vector<Cell*> sb_lut_cells;
@ -84,6 +84,9 @@ static void run_ice40_opts(Module *module)
inbits.append(cell->getPort("\\I3")); inbits.append(cell->getPort("\\I3"));
sigmap.apply(inbits); sigmap.apply(inbits);
if (unlut_mode)
goto remap_lut;
if (optimized_co.count(inbits[0])) goto remap_lut; if (optimized_co.count(inbits[0])) goto remap_lut;
if (optimized_co.count(inbits[1])) goto remap_lut; if (optimized_co.count(inbits[1])) goto remap_lut;
if (optimized_co.count(inbits[2])) goto remap_lut; if (optimized_co.count(inbits[2])) goto remap_lut;
@ -101,7 +104,7 @@ static void run_ice40_opts(Module *module)
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT")); cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT"); cell->unsetParam("\\LUT_INIT");
cell->setPort("\\A", SigSpec({cell->getPort("\\I0"), cell->getPort("\\I1"), cell->getPort("\\I2"), cell->getPort("\\I3")})); cell->setPort("\\A", SigSpec({cell->getPort("\\I3"), cell->getPort("\\I2"), cell->getPort("\\I1"), cell->getPort("\\I0")}));
cell->setPort("\\Y", cell->getPort("\\O")); cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\I0"); cell->unsetPort("\\I0");
cell->unsetPort("\\I1"); cell->unsetPort("\\I1");
@ -133,10 +136,15 @@ struct Ice40OptPass : public Pass {
log(" opt_clean\n"); log(" opt_clean\n");
log(" while <changed design>\n"); log(" while <changed design>\n");
log("\n"); log("\n");
log("When called with the option -unlut, this command will transform all already\n");
log("mapped SB_LUT4 cells back to logic.\n");
log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
string opt_expr_args = "-mux_undef -undriven"; string opt_expr_args = "-mux_undef -undriven";
bool unlut_mode = false;
log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n"); log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
log_push(); log_push();
@ -146,6 +154,10 @@ struct Ice40OptPass : public Pass {
opt_expr_args += " -full"; opt_expr_args += " -full";
continue; continue;
} }
if (args[argidx] == "-unlut") {
unlut_mode = true;
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -156,7 +168,7 @@ struct Ice40OptPass : public Pass {
log_header(design, "Running ICE40 specific optimizations.\n"); log_header(design, "Running ICE40 specific optimizations.\n");
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
run_ice40_opts(module); run_ice40_opts(module, unlut_mode);
Pass::call(design, "opt_expr " + opt_expr_args); Pass::call(design, "opt_expr " + opt_expr_args);
Pass::call(design, "opt_merge"); Pass::call(design, "opt_merge");