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semi cleanup

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This commit is contained in:
Emil J. Tywoniak 2025-05-23 21:13:02 +02:00
parent 91503e07dc
commit 125797bbb3
5 changed files with 3 additions and 17 deletions
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4
backends/rtlil/rtlil_backend.cc
View file

@ -410,17 +410,13 @@ void RTLIL_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool onl
f << stringf("autoidx %d\n", autoidx); f << stringf("autoidx %d\n", autoidx);
} }
log("dumping %zu modules\n", design->modules().size());
log("selected is .%s. %d\n", design->selected_active_module.c_str(), only_selected);
for (auto module : design->modules()) { for (auto module : design->modules()) {
log("dumping module %s %d\n", module->name.c_str(), design->selected(module));
if (!only_selected || design->selected(module)) { if (!only_selected || design->selected(module)) {
if (only_selected) if (only_selected)
f << stringf("\n"); f << stringf("\n");
dump_module(f, "", module, design, only_selected, flag_m, flag_n); dump_module(f, "", module, design, only_selected, flag_m, flag_n);
} }
} }
log("dumped modules\n");
log_assert(init_autoidx == autoidx); log_assert(init_autoidx == autoidx);
} }

5
frontends/ast/ast.cc
View file

@ -1403,7 +1403,6 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
log_assert(current_ast->type == AST_DESIGN); log_assert(current_ast->type == AST_DESIGN);
for (const auto& child : current_ast->children) for (const auto& child : current_ast->children)
{ {
child->dumpAst(stdout, "child: ");
if (child->type == AST_MODULE || child->type == AST_INTERFACE) if (child->type == AST_MODULE || child->type == AST_INTERFACE)
{ {
for (auto& n : design->verilog_globals) for (auto& n : design->verilog_globals)
@ -1461,10 +1460,6 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
process_module(design, child.get(), defer_local); process_module(design, child.get(), defer_local);
current_ast_mod = nullptr; current_ast_mod = nullptr;
log("built this:\n");
log_module(design->module(child->str));
log("here:\n");
Pass::call(design, "dump");
} }
else if (child->type == AST_PACKAGE) { else if (child->type == AST_PACKAGE) {
// process enum/other declarations // process enum/other declarations

3
frontends/verilog/verilog_frontend.cc
View file

@ -546,9 +546,6 @@ struct VerilogFrontend : public Frontend {
AST::process(design, parse_state.current_ast, flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, AST::process(design, parse_state.current_ast, flag_nodisplay, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, parse_mode.lib, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, parse_state.default_nettype_wire); flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, parse_mode.lib, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, parse_state.default_nettype_wire);
log("Got this:\n");
Pass::call(design, "dump");
if (!flag_nopp) if (!flag_nopp)
delete parse_state.lexin; delete parse_state.lexin;

5
kernel/rtlil.cc
View file

@ -821,19 +821,14 @@ bool RTLIL::Selection::selected_module(const RTLIL::IdString &mod_name) const
bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) const bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) const
{ {
log("one\n");
if (complete_selection) if (complete_selection)
return true; return true;
log("two\n");
if (!selects_boxes && boxed_module(mod_name)) if (!selects_boxes && boxed_module(mod_name))
return false; return false;
log("three\n");
if (full_selection) if (full_selection)
return true; return true;
log("four\n");
if (selected_modules.count(mod_name) > 0) if (selected_modules.count(mod_name) > 0)
return true; return true;
log("five\n");
return false; return false;
} }

3
passes/proc/proc_rmdead.cc
View file

@ -148,11 +148,14 @@ struct ProcRmdeadPass : public Pass {
int total_counter = 0; int total_counter = 0;
for (auto mod : design->modules()) { for (auto mod : design->modules()) {
log("sniff %s\n", mod->name.c_str());
if (!design->selected(mod)) if (!design->selected(mod))
continue; continue;
log("selected\n");
for (auto &proc_it : mod->processes) { for (auto &proc_it : mod->processes) {
if (!design->selected(mod, proc_it.second)) if (!design->selected(mod, proc_it.second))
continue; continue;
log("module %s is selected\n", log_id(mod));
int counter = 0, full_case_counter = 0; int counter = 0, full_case_counter = 0;
for (auto switch_it : proc_it.second->root_case.switches) for (auto switch_it : proc_it.second->root_case.switches)
proc_rmdead(switch_it, counter, full_case_counter); proc_rmdead(switch_it, counter, full_case_counter);