Tests: Prefer single quotes for regex

Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes).  Necessitates also changing single quotes to `.`, i.e match any.
For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.

tests/various/printattr.ys

@@ -1,5 +1,5 @@
 logger -expect log ".*cells_not_processed=[01]* .*" 1
-logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+logger -expect log '.*src=.<<EOT:1\.1-9\.10. .*' 1
 read_verilog <<EOT
 module mux2(a, b, s, y);
 	input a, b, s;

tests/various/src.ys

@@ -1,5 +1,5 @@
-logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
-logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
+logger -expect warning 'wire .\\o. is assigned in a block at <<EOT:2.11-2.17' 1
+logger -expect warning 'wire .\\p. is assigned in a block at <<EOT:3.11-3.16' 1
 read_verilog <<EOT
 module top(input i, output o, p);
 always @* o <= i;

tests/various/sta.ys

@@ -11,7 +11,7 @@ buffer b(.i(i), .o(w));
 endmodule
 EOT
 
-logger -expect warning "Critical-path does not terminate in a recognised endpoint\." 1
+logger -expect warning "Critical-path does not terminate in a recognised endpoint." 1
 sta
 
 
@@ -22,7 +22,7 @@ assign o = i;
 endmodule
 EOT
 
-logger -expect log "No timing paths found\." 1
+logger -expect log "No timing paths found." 1
 sta
 
 
@@ -56,7 +56,7 @@ const0 c(.o(p));
 endmodule
 EOT
 
-logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
+logger -expect warning "Cell type 'const0' not recognised! Ignoring." 1
 sta
 
 

tests/various/stat.ys

@@ -9,7 +9,7 @@ module \top
   end
 end
 EOT
-logger -expect log "Chip area for module '\\top': 9.072000" 1
+logger -expect log 'Chip area for module .\\top.: 9.072000' 1
 logger -expect-no-warnings
 logger -expect log "        1    9.072 cells" 1
 logger -expect log "        1    9.072   sg13g2_and2_1" 1
@@ -70,7 +70,7 @@ module \child
 
 end
 EOT
-logger -expect log "Chip area for top module '\\top': 112.492800" 1
+logger -expect log 'Chip area for top module .\\top.: 112.492800' 1
 logger -expect log "of which used for sequential elements: 94.348800" 1
 logger -expect log "2   18.144 cells" 1 
 logger -expect log "4  112.493 cells" 1

tests/various/stat_high_level.ys

@@ -82,9 +82,9 @@ module \child
 
 end
 EOT
-logger -expect log "Chip area for top module '\\top': 66.000000" 1
+logger -expect log 'Chip area for top module .\\top.: 66.000000' 1
 logger -expect log "3     30.5        3     30.5 cells" 1
-logger -expect log "2       51        -        -   \$reduce_xor" 2
+logger -expect log "2       51        -        -   \\$reduce_xor" 2
 logger -expect log "8       66        2        5 cells" 2
 logger -expect-no-warnings
 stat -liberty ./stat_area_by_width.lib -top \top -hierarchy

tests/various/stat_high_level2.ys

@@ -81,8 +81,8 @@ module \child
 end
 EOT
 
-logger -expect log "Chip area for top module '\\top': 80.000000" 1
-logger -expect log "1       12        1       12   \$bmux" 1
+logger -expect log 'Chip area for top module .\\top.: 80.000000' 1
+logger -expect log "1       12        1       12   \\$bmux" 1
 logger -expect log "3     37.5        3     37.5 cells" 1
 logger -expect log "8       80        2        5 cells" 2
 logger -expect-no-warnings

tests/various/sv_defines_mismatch.ys

@@ -1,5 +1,5 @@
 # Check that we spot mismatched brackets
-logger -expect error "Mismatched brackets in macro argument: \[ and }." 1
+logger -expect error "Mismatched brackets in macro argument: \\[ and }." 1
 read_verilog <<EOT
 `define foo(x=[1,2})
 EOT

tests/various/sv_defines_too_few.ys

@@ -1,6 +1,6 @@
 # Check that we don't allow passing too few arguments (and, while we're at it, check that passing "no"
 # arguments actually passes 1 empty argument).
-logger -expect error "Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\)." 1
+logger -expect error 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' 1
 read_verilog <<EOT
 `define foo(x=1, y)
 `foo()