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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 6cd77a9af6
commit 1210d8e117
203 changed files with 4581 additions and 4487 deletions

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@ -38,7 +38,7 @@ struct Test1Pass : public Pass {
y->port_output = true;
y->port_id = 2;
RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
RTLIL::Wire *a_inv = module->addWire(NEW_TWINE, 4);
module->addNeg(NEW_ID, a, a_inv, true);
module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);