diff --git a/.github/workflows/prepare-docs.yml b/.github/workflows/prepare-docs.yml
new file mode 100644
index 000000000..9233e6295
--- /dev/null
+++ b/.github/workflows/prepare-docs.yml
@@ -0,0 +1,52 @@
+name: Build docs artifact with Verific
+
+on: push
+
+jobs:
+ prepare-docs:
+ # docs builds are needed for anything on main, any tagged versions, and any tag
+ # or branch starting with docs-preview
+ if: ${{ github.ref == 'refs/heads/main' || startsWith(github.ref, 'refs/heads/docs-preview') || startsWith(github.ref, 'refs/tags/') }}
+ runs-on: [self-hosted, linux, x64, fast]
+ steps:
+ - name: Checkout Yosys
+ uses: actions/checkout@v4
+ with:
+ persist-credentials: false
+ submodules: true
+
+ - name: Runtime environment
+ run: |
+ echo "procs=$(nproc)" >> $GITHUB_ENV
+
+ - name: Build Yosys
+ run: |
+ make config-clang
+ echo "ENABLE_VERIFIC := 1" >> Makefile.conf
+ echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
+ echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
+ echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
+ echo "ENABLE_CCACHE := 1" >> Makefile.conf
+ make -j${{ env.procs }} ENABLE_LTO=1
+
+ - name: Prepare docs
+ shell: bash
+ run:
+ make docs/prep TARGETS= EXTRA_TARGETS=
+
+ - name: Upload artifact
+ uses: actions/upload-artifact@v4
+ with:
+ name: cmd-ref-${{ github.sha }}
+ path: |
+ docs/source/cmd
+ docs/source/generated
+ docs/source/_images
+ docs/source/code_examples
+
+ - name: Trigger RTDs build
+ uses: dfm/rtds-action@v1.1.0
+ with:
+ webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}
+ webhook_token: ${{ secrets.RTDS_WEBHOOK_TOKEN }}
+ commit_ref: ${{ github.ref }}
diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml
index 627a70d47..43b68e06d 100644
--- a/.github/workflows/test-verific.yml
+++ b/.github/workflows/test-verific.yml
@@ -11,13 +11,11 @@ jobs:
- id: skip_check
uses: fkirc/skip-duplicate-actions@v5
with:
- paths_ignore: '["**/README.md"]'
- # don't cancel previous builds
+ paths_ignore: '["**/README.md", "docs/**", "guidelines/**"]'
+ # cancel previous builds if a new commit is pushed
cancel_others: 'true'
# only run on push *or* pull_request, not both
concurrent_skipping: 'same_content_newer'
- # we have special actions when running on main, so this should be off
- skip_after_successful_duplicate: 'false'
test-verific:
needs: pre-job
@@ -70,51 +68,3 @@ jobs:
if: ${{ github.ref == 'refs/heads/main' }}
run: |
make -C sby run_ci
-
- prepare-docs:
- name: Generate docs artifact
- needs: [pre-job, test-verific]
- if: needs.pre-job.outputs.should_skip != 'true'
- runs-on: [self-hosted, linux, x64, fast]
- steps:
- - name: Checkout Yosys
- uses: actions/checkout@v4
- with:
- persist-credentials: false
- submodules: true
- - name: Runtime environment
- run: |
- echo "procs=$(nproc)" >> $GITHUB_ENV
-
- - name: Build Yosys
- run: |
- make config-clang
- echo "ENABLE_VERIFIC := 1" >> Makefile.conf
- echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
- echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
- echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
- echo "ENABLE_CCACHE := 1" >> Makefile.conf
- make -j${{ env.procs }} ENABLE_LTO=1
-
- - name: Prepare docs
- shell: bash
- run:
- make docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs TARGETS= EXTRA_TARGETS=
-
- - name: Upload artifact
- uses: actions/upload-artifact@v4
- with:
- name: cmd-ref-${{ github.sha }}
- path: |
- docs/source/cmd
- docs/source/generated
- docs/source/_images
- docs/source/code_examples
-
- - name: Trigger RTDs build
- if: ${{ github.ref == 'refs/heads/main' }}
- uses: dfm/rtds-action@v1.1.0
- with:
- webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}
- webhook_token: ${{ secrets.RTDS_WEBHOOK_TOKEN }}
- commit_ref: ${{ github.ref }}
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index cb700dc1c..4a04219de 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -13,6 +13,7 @@ formats:
sphinx:
configuration: docs/source/conf.py
+ fail_on_warning: true
python:
install:
diff --git a/CHANGELOG b/CHANGELOG
index 3d22bfe60..03bf5ac57 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,9 +2,17 @@
List of major changes and improvements between releases
=======================================================
-Yosys 0.44 .. Yosys 0.45-dev
+Yosys 0.45 .. Yosys 0.46-dev
--------------------------
+Yosys 0.44 .. Yosys 0.45
+--------------------------
+ * Various
+ - Added cell types help messages.
+
+ * New back-ends
+ - Added initial NG-Ultra support. ( synth_nanoxplore )
+
Yosys 0.43 .. Yosys 0.44
--------------------------
* Various
diff --git a/Makefile b/Makefile
index 67990ca10..5f0c99bbd 100644
--- a/Makefile
+++ b/Makefile
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE
endif
-YOSYS_VER := 0.44+60
+YOSYS_VER := 0.45+3
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -169,7 +169,7 @@ endif
OBJS = kernel/version_$(GIT_REV).o
bumpversion:
- sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 80ba43d.. | wc -l`/;" Makefile
+ sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 9ed031d.. | wc -l`/;" Makefile
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
@@ -893,6 +893,7 @@ endif
+cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT)
+cd tests/arch/gowin && bash run-test.sh $(SEEDOPT)
+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
+ +cd tests/arch/nanoxplore && bash run-test.sh $(SEEDOPT)
+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
+cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT)
+cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT)
@@ -1025,8 +1026,11 @@ docs/usage: $(addprefix docs/source/generated/,$(DOCS_USAGE_STDOUT) $(DOCS_USAGE
docs/reqs:
$(Q) $(MAKE) -C docs reqs
+.PHONY: docs/prep
+docs/prep: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage
+
DOC_TARGET ?= html
-docs: docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs
+docs: docs/prep
$(Q) $(MAKE) -C docs $(DOC_TARGET)
clean:
diff --git a/README.md b/README.md
index 7437bb283..d215d8442 100644
--- a/README.md
+++ b/README.md
@@ -629,11 +629,21 @@ following are used for building the website:
$ sudo apt install pdf2svg faketime
+Or for MacOS, using homebrew:
+
+ $ brew install pdf2svg libfaketime
+
PDFLaTeX, included with most LaTeX distributions, is also needed during the
build process for the website. Or, run the following:
$ sudo apt install texlive-latex-base texlive-latex-extra latexmk
+Or for MacOS, using homebrew:
+
+ $ brew install basictex
+ $ sudo tlmgr update --self
+ $ sudo tlmgr install collection-latexextra latexmk tex-gyre
+
The Python package, Sphinx, is needed along with those listed in
`docs/source/requirements.txt`:
diff --git a/docs/Makefile b/docs/Makefile
index 701157ee6..8be970391 100644
--- a/docs/Makefile
+++ b/docs/Makefile
@@ -250,6 +250,7 @@ test-macros:
.PHONY: images
images:
$(MAKE) -C source/_images
+ $(MAKE) -C source/_images convert
.PHONY: reqs
reqs:
diff --git a/docs/source/_images/Makefile b/docs/source/_images/Makefile
index 955805f9c..26cc47284 100644
--- a/docs/source/_images/Makefile
+++ b/docs/source/_images/Makefile
@@ -8,24 +8,22 @@ FAKETIME := TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001'
CODE_EXAMPLES := ../code_examples/*/Makefile
examples: $(CODE_EXAMPLES)
-# target to convert specified dot file(s)
+# target to convert all dot files
+# needs to be run *after* examples, otherwise no dot files will be found
.PHONY: convert
-TARG_DOT ?=
-convert: $(TARG_DOT:.dot=.pdf) $(TARG_DOT:.dot=.svg)
+DOT_FILES := $(shell find . -name *.dot)
+convert: $(DOT_FILES:.dot=.pdf) $(DOT_FILES:.dot=.svg)
-# use empty FORCE target because .PHONY ignores % expansion, using find allows
-# us to generate everything in one pass, since we don't know all of the possible
-# outputs until the sub-makes run
+# use empty FORCE target because .PHONY ignores % expansion
FORCE:
../%/Makefile: FORCE
@make -C $(@D) dots
@mkdir -p $*
- @find $(@D) -name *.dot -exec cp -u {} -t $* \;
- @find $* -name *.dot -printf "%p " | xargs -i make --no-print-directory convert TARG_DOT="{}"
+ @find $(@D) -name *.dot -exec rsync -t {} $* \;
# find and build all tex files
.PHONY: all_tex
-TEX_FILES := $(wildcard **/*.tex)
+TEX_FILES := $(shell find . -name *.tex)
all_tex: $(TEX_FILES:.tex=.pdf) $(TEX_FILES:.tex=.svg)
%.pdf: %.dot
diff --git a/docs/source/code_examples/opt/Makefile b/docs/source/code_examples/opt/Makefile
index 4cb51e90b..12c1c93b1 100644
--- a/docs/source/code_examples/opt/Makefile
+++ b/docs/source/code_examples/opt/Makefile
@@ -13,7 +13,7 @@ dots: $(DOTS)
$(YOSYS) $<
%.dot: %_full.dot
- gvpack -u $*_full.dot -o $@
+ gvpack -u -o $@ $*_full.dot
.PHONY: clean
clean:
diff --git a/docs/source/conf.py b/docs/source/conf.py
index 23efe2b43..4371b79f1 100644
--- a/docs/source/conf.py
+++ b/docs/source/conf.py
@@ -5,7 +5,7 @@ import os
project = 'YosysHQ Yosys'
author = 'YosysHQ GmbH'
copyright ='2024 YosysHQ GmbH'
-yosys_ver = "0.44"
+yosys_ver = "0.45"
# select HTML theme
html_theme = 'furo'
@@ -41,23 +41,44 @@ html_static_path = ['_static', "_images"]
pygments_style = 'colorful'
highlight_language = 'none'
-extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex', 'rtds_action']
+extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex']
-# rtds_action
-rtds_action_github_repo = "YosysHQ/yosys"
-rtds_action_path = "."
-rtds_action_artifact_prefix = "cmd-ref-"
-rtds_action_github_token = os.environ["GITHUB_TOKEN"]
+if os.getenv("READTHEDOCS"):
+ # Use rtds_action if we are building on read the docs and have a github token env var
+ if os.getenv("GITHUB_TOKEN"):
+ extensions += ['rtds_action']
+ rtds_action_github_repo = "YosysHQ/yosys"
+ rtds_action_path = "."
+ rtds_action_artifact_prefix = "cmd-ref-"
+ rtds_action_github_token = os.environ["GITHUB_TOKEN"]
+ else:
+ # We're on read the docs but have no github token, this is probably a PR preview build
+ html_theme_options["announcement"] = 'Missing content? Check PR preview limitations.'
+ html_theme_options["light_css_variables"]["color-announcement-background"] = "var(--color-admonition-title-background--caution)"
+ html_theme_options["light_css_variables"]["color-announcement-text"] = "var(--color-content-foreground)"
# Ensure that autosectionlabel will produce unique names
autosectionlabel_prefix_document = True
autosectionlabel_maxdepth = 1
+# include todos for previews
+extensions.append('sphinx.ext.todo')
+
# set version
-if os.getenv("READTHEDOCS") and os.getenv("READTHEDOCS_VERSION") == "latest":
- release = yosys_ver + "-dev"
+if os.getenv("READTHEDOCS"):
+ rtds_version = os.getenv("READTHEDOCS_VERSION")
+ if rtds_version == "latest":
+ release = yosys_ver + "-dev"
+ todo_include_todos = False
+ elif rtds_version.startswith("docs"):
+ release = rtds_version
+ todo_include_todos = True
+ else:
+ release = yosys_ver
+ todo_include_todos = False
else:
release = yosys_ver
+ todo_include_todos = True
# assign figure numbers
numfig = True
@@ -72,10 +93,6 @@ latex_elements = {
'''
}
-# include todos during rewrite
-extensions.append('sphinx.ext.todo')
-todo_include_todos = False
-
# custom cmd-ref parsing/linking
sys.path += [os.path.dirname(__file__) + "/../"]
extensions.append('util.cmdref')
diff --git a/docs/source/using_yosys/more_scripting/index.rst b/docs/source/using_yosys/more_scripting/index.rst
index 490a5a7ad..090b9e0b9 100644
--- a/docs/source/using_yosys/more_scripting/index.rst
+++ b/docs/source/using_yosys/more_scripting/index.rst
@@ -3,6 +3,8 @@ More scripting
.. todo:: brief overview for the more scripting index
+.. todo:: troubleshooting document(?)
+
.. toctree::
:maxdepth: 3
diff --git a/docs/source/using_yosys/more_scripting/troubleshooting.rst b/docs/source/using_yosys/more_scripting/troubleshooting.rst
deleted file mode 100644
index a17a552d2..000000000
--- a/docs/source/using_yosys/more_scripting/troubleshooting.rst
+++ /dev/null
@@ -1,6 +0,0 @@
-Troubleshooting
-~~~~~~~~~~~~~~~
-
-.. todo:: troubleshooting document(?)
-
-See :doc:`/cmd/bugpoint`
diff --git a/docs/source/using_yosys/synthesis/cell_libs.rst b/docs/source/using_yosys/synthesis/cell_libs.rst
index 92b6dab3f..4e800bdf2 100644
--- a/docs/source/using_yosys/synthesis/cell_libs.rst
+++ b/docs/source/using_yosys/synthesis/cell_libs.rst
@@ -90,8 +90,10 @@ Mapping to hardware
For this example, we are using a Liberty file to describe a cell library which
our internal cell library will be mapped to:
+.. todo:: find a Liberty pygments style?
+
.. literalinclude:: /code_examples/intro/mycells.lib
- :language: Liberty
+ :language: text
:linenos:
:name: mycells-lib
:caption: :file:`mycells.lib`
diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index b20517bd3..2585ebae4 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -81,8 +81,10 @@ The following features, along with their corresponding Yosys build parameters,
are required for the Yosys-Verific patch:
* RTL elaboration with
- * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
- * VHDL support with ``ENABLE_VERIFIC_VHDL``.
+
+ * SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
+ * VHDL support with ``ENABLE_VERIFIC_VHDL``.
+
* Hierarchy tree support and static elaboration with
``ENABLE_VERIFIC_HIER_TREE``.
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index dda0fefaf..5fc475a91 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -17,6 +17,7 @@ OBJS += passes/cmds/splitnets.o
OBJS += passes/cmds/splitcells.o
OBJS += passes/cmds/splitfanout.o
OBJS += passes/cmds/stat.o
+OBJS += passes/cmds/internal_stats.o
OBJS += passes/cmds/setattr.o
OBJS += passes/cmds/copy.o
OBJS += passes/cmds/splice.o
diff --git a/passes/cmds/internal_stats.cc b/passes/cmds/internal_stats.cc
new file mode 100644
index 000000000..fe27bee5e
--- /dev/null
+++ b/passes/cmds/internal_stats.cc
@@ -0,0 +1,120 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Claire Xenia Wolf
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include
+#include
+#include
+
+#include "kernel/yosys.h"
+#include "kernel/celltypes.h"
+#include "passes/techmap/libparse.h"
+#include "kernel/cost.h"
+#include "libs/json11/json11.hpp"
+
+#if defined(__APPLE__) && defined(__MACH__)
+#include
+#include
+#endif
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+std::optional current_mem_bytes() {
+
+#if defined(__APPLE__)
+ task_basic_info_64_data_t basicInfo;
+ mach_msg_type_number_t count = TASK_BASIC_INFO_64_COUNT;
+ kern_return_t error = task_info(mach_task_self(), TASK_BASIC_INFO_64, (task_info_t)&basicInfo, &count);
+ if (error != KERN_SUCCESS) {
+ return {}; // Error getting task information
+ }
+ return basicInfo.resident_size; // Return RSS in KB
+
+#elif defined(__linux__)
+ // Not all linux distributions have to have this file
+ std::ifstream statusFile("/proc/self/status");
+ std::string line;
+ while (std::getline(statusFile, line)) {
+ if (line.find("VmRSS:") == 0) {
+ std::istringstream iss(line);
+ std::string token;
+ // Skip prefix
+ iss >> token;
+ uint64_t rss;
+ iss >> rss;
+ return rss * 1024;
+ }
+ }
+ // Error reading /proc/self/status
+ return {};
+
+#else
+ return {};
+#endif
+}
+
+struct InternalStatsPass : public Pass {
+ InternalStatsPass() : Pass("internal_stats", "print some internal statistics") { }
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n"); // TODO
+ }
+ void execute(std::vector args, RTLIL::Design *design) override
+ {
+ bool json_mode = false;
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-json") {
+ json_mode = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if(!json_mode)
+ log_header(design, "Printing internal statistics.\n");
+
+ log_experimental("internal_stats");
+
+ if (json_mode) {
+ log("{\n");
+ log(" \"creator\": %s,\n", json11::Json(yosys_version_str).dump().c_str());
+ std::stringstream invocation;
+ std::copy(args.begin(), args.end(), std::ostream_iterator(invocation, " "));
+ log(" \"invocation\": %s,\n", json11::Json(invocation.str()).dump().c_str());
+ if (auto mem = current_mem_bytes()) {
+ log(" \"memory_now\": %s,\n", std::to_string(*mem).c_str());
+ }
+ }
+
+ // stats go here
+
+ if (json_mode) {
+ log("\n");
+ log("}\n");
+ }
+
+ }
+} InternalStatsPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index fd56786f2..3aad9ac1c 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -54,90 +54,35 @@ RTLIL::SigSpec find_any_lvalue(const RTLIL::Process *proc)
}
void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, RTLIL::SigSpec clk, bool clk_polarity,
- std::map> &async_rules, RTLIL::Process *proc)
+ std::vector> &async_rules, RTLIL::Process *proc)
{
+ // A signal should be set/cleared if there is a load trigger that is enabled
+ // such that the load value is 1/0 and it is the highest priority trigger
RTLIL::SigSpec sig_sr_set = RTLIL::SigSpec(0, sig_d.size());
RTLIL::SigSpec sig_sr_clr = RTLIL::SigSpec(0, sig_d.size());
- for (auto &it : async_rules)
+ // Reverse iterate through the rules as the first ones are the highest priority
+ // so need to be at the top of the mux trees
+ for (auto it = async_rules.crbegin(); it != async_rules.crend(); it++)
{
- RTLIL::SigSpec sync_value = it.first;
- RTLIL::SigSpec sync_value_inv;
- RTLIL::SigSpec sync_high_signals;
- RTLIL::SigSpec sync_low_signals;
+ const auto& [sync_value, rule] = *it;
+ const auto pos_trig = rule->type == RTLIL::SyncType::ST1 ? rule->signal : mod->Not(NEW_ID, rule->signal);
- for (auto &it2 : it.second)
- if (it2->type == RTLIL::SyncType::ST0)
- sync_low_signals.append(it2->signal);
- else if (it2->type == RTLIL::SyncType::ST1)
- sync_high_signals.append(it2->signal);
- else
- log_abort();
+ // If pos_trig is true, we have priority at this point in the tree so
+ // set a bit if sync_value has a set bit. Otherwise, defer to the rest
+ // of the priority tree
+ sig_sr_set = mod->Mux(NEW_ID, sig_sr_set, sync_value, pos_trig);
- if (sync_low_signals.size() > 1) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
- cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
- cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
- cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
- cell->setPort(ID::A, sync_low_signals);
- cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
- }
-
- if (sync_low_signals.size() > 0) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not));
- cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
- cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
- cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
- cell->setPort(ID::A, sync_low_signals);
- cell->setPort(ID::Y, mod->addWire(NEW_ID));
- sync_high_signals.append(cell->getPort(ID::Y));
- }
-
- if (sync_high_signals.size() > 1) {
- RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
- cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
- cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size());
- cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
- cell->setPort(ID::A, sync_high_signals);
- cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
- }
-
- RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not));
- inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
- inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size());
- inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size());
- inv_cell->setPort(ID::A, sync_value);
- inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
-
- RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux));
- mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
- mux_set_cell->setPort(ID::A, sig_sr_set);
- mux_set_cell->setPort(ID::B, sync_value);
- mux_set_cell->setPort(ID::S, sync_high_signals);
- mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
-
- RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux));
- mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
- mux_clr_cell->setPort(ID::A, sig_sr_clr);
- mux_clr_cell->setPort(ID::B, sync_value_inv);
- mux_clr_cell->setPort(ID::S, sync_high_signals);
- mux_clr_cell->setPort(ID::Y, sig_sr_clr = mod->addWire(NEW_ID, sig_d.size()));
+ // Same deal with clear bit
+ const auto sync_value_inv = mod->Not(NEW_ID, sync_value);
+ sig_sr_clr = mod->Mux(NEW_ID, sig_sr_clr, sync_value_inv, pos_trig);
}
std::stringstream sstr;
sstr << "$procdff$" << (autoidx++);
- RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
+ RTLIL::Cell *cell = mod->addDffsr(sstr.str(), clk, sig_sr_set, sig_sr_clr, sig_d, sig_q, clk_polarity);
cell->attributes = proc->attributes;
- cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
- cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
- cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
- cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
- cell->setPort(ID::D, sig_d);
- cell->setPort(ID::Q, sig_q);
- cell->setPort(ID::CLK, clk);
- cell->setPort(ID::SET, sig_sr_set);
- cell->setPort(ID::CLR, sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@@ -204,7 +149,6 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
while (1)
{
RTLIL::SigSpec sig = find_any_lvalue(proc);
- bool free_sync_level = false;
if (sig.size() == 0)
break;
@@ -213,13 +157,17 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
mod->name.c_str(), log_signal(sig), mod->name.c_str(), proc->name.c_str());
RTLIL::SigSpec insig = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
- RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
- RTLIL::SyncRule *sync_level = NULL;
RTLIL::SyncRule *sync_edge = NULL;
RTLIL::SyncRule *sync_always = NULL;
bool global_clock = false;
- std::map> many_async_rules;
+ // A priority ordered set of rules, pairing the value to be assigned for
+ // that rule to the rule
+ std::vector> async_rules;
+
+ // Needed when the async rules are collapsed into one as async_rules
+ // works with pointers to SyncRule
+ RTLIL::SyncRule single_async_rule;
for (auto sync : proc->syncs)
for (auto &action : sync->actions)
@@ -228,14 +176,9 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
continue;
if (sync->type == RTLIL::SyncType::ST0 || sync->type == RTLIL::SyncType::ST1) {
- if (sync_level != NULL && sync_level != sync) {
- // log_error("Multiple level sensitive events found for this signal!\n");
- many_async_rules[rstval].insert(sync_level);
- rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
- }
- rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
+ RTLIL::SigSpec rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
sig.replace(action.first, action.second, &rstval);
- sync_level = sync;
+ async_rules.emplace_back(rstval, sync);
}
else if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) {
if (sync_edge != NULL && sync_edge != sync)
@@ -260,59 +203,51 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
action.first.remove2(sig, &action.second);
}
- if (many_async_rules.size() > 0)
+ // If all async rules assign the same value, priority ordering between
+ // them doesn't matter so they can be collapsed together into one rule
+ // with the disjunction of triggers
+ if (!async_rules.empty() &&
+ std::all_of(async_rules.begin(), async_rules.end(), [&](auto& p) {
+ return p.first == async_rules.front().first;
+ }))
{
- many_async_rules[rstval].insert(sync_level);
- if (many_async_rules.size() == 1)
- {
- sync_level = new RTLIL::SyncRule;
- sync_level->type = RTLIL::SyncType::ST1;
- sync_level->signal = mod->addWire(NEW_ID);
- sync_level->actions.push_back(RTLIL::SigSig(sig, rstval));
- free_sync_level = true;
+ const auto rstval = async_rules.front().first;
- RTLIL::SigSpec inputs, compare;
- for (auto &it : many_async_rules[rstval]) {
- inputs.append(it->signal);
- compare.append(it->type == RTLIL::SyncType::ST0 ? RTLIL::State::S1 : RTLIL::State::S0);
- }
- log_assert(inputs.size() == compare.size());
+ // The trigger is the disjunction of existing triggers
+ // (with appropriate negation)
+ RTLIL::SigSpec triggers;
+ for (const auto &[_, it] : async_rules)
+ triggers.append(it->type == RTLIL::SyncType::ST1 ? it->signal : mod->Not(NEW_ID, it->signal));
- RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($ne));
- cell->parameters[ID::A_SIGNED] = RTLIL::Const(false, 1);
- cell->parameters[ID::B_SIGNED] = RTLIL::Const(false, 1);
- cell->parameters[ID::A_WIDTH] = RTLIL::Const(inputs.size());
- cell->parameters[ID::B_WIDTH] = RTLIL::Const(inputs.size());
- cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
- cell->setPort(ID::A, inputs);
- cell->setPort(ID::B, compare);
- cell->setPort(ID::Y, sync_level->signal);
+ // Put this into the dummy sync rule so it can be treated the same
+ // as ones coming from the module
+ single_async_rule.type = RTLIL::SyncType::ST1;
+ single_async_rule.signal = mod->ReduceOr(NEW_ID, triggers);
+ single_async_rule.actions.push_back(RTLIL::SigSig(sig, rstval));
- many_async_rules.clear();
- }
- else
- {
- rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
- sync_level = NULL;
- }
+ // Replace existing rules with this new rule
+ async_rules.clear();
+ async_rules.emplace_back(rstval, &single_async_rule);
}
SigSpec sig_q = sig;
ce.assign_map.apply(insig);
- ce.assign_map.apply(rstval);
ce.assign_map.apply(sig);
- if (rstval == sig && sync_level) {
- if (sync_level->type == RTLIL::SyncType::ST1)
- insig = mod->Mux(NEW_ID, insig, sig, sync_level->signal);
+ // If the reset value assigns the reg to itself, add this as part of
+ // the input signal and delete the rule
+ if (async_rules.size() == 1 && async_rules.front().first == sig) {
+ const auto& [_, rule] = async_rules.front();
+ if (rule->type == RTLIL::SyncType::ST1)
+ insig = mod->Mux(NEW_ID, insig, sig, rule->signal);
else
- insig = mod->Mux(NEW_ID, sig, insig, sync_level->signal);
- rstval = RTLIL::SigSpec(RTLIL::State::Sz, sig.size());
- sync_level = NULL;
+ insig = mod->Mux(NEW_ID, sig, insig, rule->signal);
+
+ async_rules.clear();
}
if (sync_always) {
- if (sync_edge || sync_level || many_async_rules.size() > 0)
+ if (sync_edge || !async_rules.empty())
log_error("Mixed always event with edge and/or level sensitive events!\n");
log(" created direct connection (no actual register cell created).\n");
mod->connect(RTLIL::SigSig(sig, insig));
@@ -322,28 +257,34 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
if (!sync_edge && !global_clock)
log_error("Missing edge-sensitive event for this signal!\n");
- if (many_async_rules.size() > 0)
+ // More than one reset value so we derive a dffsr formulation
+ if (async_rules.size() > 1)
{
log_warning("Complex async reset for dff `%s'.\n", log_signal(sig));
- gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, many_async_rules, proc);
+ gen_dffsr_complex(mod, insig, sig, sync_edge->signal, sync_edge->type == RTLIL::SyncType::STp, async_rules, proc);
+ return;
}
- else if (!rstval.is_fully_const() && !ce.eval(rstval))
+
+ // If there is a reset condition in the async rules, use it
+ SigSpec rstval = async_rules.empty() ? RTLIL::SigSpec(RTLIL::State::Sz, sig.size()) : async_rules.front().first;
+ RTLIL::SyncRule* sync_level = async_rules.empty() ? nullptr : async_rules.front().second;
+ ce.assign_map.apply(rstval);
+
+ if (!rstval.is_fully_const() && !ce.eval(rstval))
{
log_warning("Async reset value `%s' is not constant!\n", log_signal(rstval));
gen_aldff(mod, insig, rstval, sig_q,
sync_edge->type == RTLIL::SyncType::STp,
sync_level && sync_level->type == RTLIL::SyncType::ST1,
sync_edge->signal, sync_level->signal, proc);
+ return;
}
- else
- gen_dff(mod, insig, rstval.as_const(), sig_q,
- sync_edge && sync_edge->type == RTLIL::SyncType::STp,
- sync_level && sync_level->type == RTLIL::SyncType::ST1,
- sync_edge ? sync_edge->signal : SigSpec(),
- sync_level ? &sync_level->signal : NULL, proc);
- if (free_sync_level)
- delete sync_level;
+ gen_dff(mod, insig, rstval.as_const(), sig_q,
+ sync_edge && sync_edge->type == RTLIL::SyncType::STp,
+ sync_level && sync_level->type == RTLIL::SyncType::ST1,
+ sync_edge ? sync_edge->signal : SigSpec(),
+ sync_level ? &sync_level->signal : NULL, proc);
}
}
diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
new file mode 100644
index 000000000..807cf36a4
--- /dev/null
+++ b/techlibs/nanoxplore/Makefile.inc
@@ -0,0 +1,31 @@
+
+OBJS += techlibs/nanoxplore/synth_nanoxplore.o
+OBJS += techlibs/nanoxplore/nx_carry.o
+
+# Techmap
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/arith_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_init.vh))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/brams.txt))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_bb_u.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim_u.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_init.vh))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_l.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_m.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_map_u.v))
diff --git a/techlibs/nanoxplore/arith_map.v b/techlibs/nanoxplore/arith_map.v
new file mode 100644
index 000000000..39d03229d
--- /dev/null
+++ b/techlibs/nanoxplore/arith_map.v
@@ -0,0 +1,76 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2024 Miodrag Milanovic
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ (* force_downto *)
+ input [A_WIDTH-1:0] A;
+ (* force_downto *)
+ input [B_WIDTH-1:0] B;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] X, Y;
+
+ input CI, BI;
+ (* force_downto *)
+ output [Y_WIDTH-1:0] CO;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] COx;
+
+ wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+
+ genvar i;
+ generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+ NX_CY_1BIT #(.first(i==0))
+ alu_i (
+ .CI(i==0 ? CI : COx[i-1]),
+ .A(AA[i]),
+ .B(BB[i]),
+ .S(Y[i]),
+ .CO(COx[i])
+ );
+
+ end: slice
+ endgenerate
+
+ NX_CY_1BIT alu_cout(
+ .CI(COx[Y_WIDTH-1]),
+ .A(1'b0),
+ .B(1'b0),
+ .S(CO[Y_WIDTH-1])
+ );
+
+ /* End implementation */
+ assign X = AA ^ BB;
+endmodule
diff --git a/techlibs/nanoxplore/brams.txt b/techlibs/nanoxplore/brams.txt
new file mode 100644
index 000000000..d151cffa4
--- /dev/null
+++ b/techlibs/nanoxplore/brams.txt
@@ -0,0 +1,50 @@
+ram block $__NX_RAM_ {
+ option "STD_MODE" "NOECC_48kx1" {
+ # only 32k used
+ abits 15;
+ widths 1 per_port;
+ }
+ option "STD_MODE" "NOECC_24kx2" {
+ # only 16k used
+ abits 14;
+ widths 2 per_port;
+ }
+ ifndef IS_NG_MEDIUM {
+ option "STD_MODE" "NOECC_16kx3" {
+ abits 14;
+ widths 3 per_port;
+ }
+ }
+ option "STD_MODE" "NOECC_12kx4" {
+ # only 8k used
+ abits 13;
+ widths 4 per_port;
+ }
+ ifndef IS_NG_MEDIUM {
+ option "STD_MODE" "NOECC_8kx6" {
+ abits 13;
+ widths 6 per_port;
+ }
+ }
+ option "STD_MODE" "NOECC_6kx8" {
+ # only 4k used
+ abits 12;
+ widths 8 per_port;
+ }
+ option "STD_MODE" "NOECC_4kx12" {
+ abits 12;
+ widths 12 per_port;
+ }
+ option "STD_MODE" "NOECC_2kx24" {
+ abits 11;
+ widths 24 per_port;
+ }
+ cost 64;
+ init no_undef;
+ port srsw "A" "B" {
+ clock anyedge;
+ clken;
+ rdwr no_change;
+ rdinit none;
+ }
+}
\ No newline at end of file
diff --git a/techlibs/nanoxplore/brams_init.vh b/techlibs/nanoxplore/brams_init.vh
new file mode 100644
index 000000000..b93839c5a
--- /dev/null
+++ b/techlibs/nanoxplore/brams_init.vh
@@ -0,0 +1,23 @@
+function [409600-1:0] bram_init_to_string;
+ input [49152-1:0] array;
+ input integer blocks;
+ input integer width;
+ reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
+ reg [24-1:0] temp2;
+ integer i;
+ integer j;
+begin
+ temp = "";
+ for (i = 0; i < 2048; i = i + 1) begin
+ if (i != 0) begin
+ temp = {temp, ","};
+ end
+ temp2 = 24'b0;
+ for (j = 0; j < blocks; j = j + 1) begin
+ temp2[j*width +: width] = array[{j, i[10:0]}*width +: width];
+ end
+ temp = {temp, $sformatf("%b",temp2[23:0])};
+ end
+ bram_init_to_string = temp;
+end
+endfunction
diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
new file mode 100644
index 000000000..506e2dd0b
--- /dev/null
+++ b/techlibs/nanoxplore/brams_map.v
@@ -0,0 +1,84 @@
+module $__NX_RAM_ (...);
+
+parameter INIT = 0;
+parameter OPTION_STD_MODE = "NOECC_24kx2";
+
+parameter PORT_A_WIDTH = 24;
+parameter PORT_B_WIDTH = 24;
+
+parameter PORT_A_CLK_POL = 1;
+
+input PORT_A_CLK;
+input PORT_A_CLK_EN;
+input PORT_A_WR_EN;
+input [15:0] PORT_A_ADDR;
+input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
+wire [24-1:0] A_DATA;
+output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
+
+parameter PORT_B_CLK_POL = 1;
+
+input PORT_B_CLK;
+input PORT_B_CLK_EN;
+input PORT_B_WR_EN;
+input [15:0] PORT_B_ADDR;
+input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
+wire [24-1:0] B_DATA;
+output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+`include "brams_init.vh"
+
+localparam raw_config1_val = OPTION_STD_MODE == "NOECC_48kx1" ? 16'b0000000000000000:
+ OPTION_STD_MODE == "NOECC_24kx2" ? 16'b0000001001001001:
+ OPTION_STD_MODE == "NOECC_16kx3" ? 16'b0000110110110110:
+ OPTION_STD_MODE == "NOECC_12kx4" ? 16'b0000010010010010:
+ OPTION_STD_MODE == "NOECC_8kx6" ? 16'b0000111111111111:
+ OPTION_STD_MODE == "NOECC_6kx8" ? 16'b0000011011011011:
+ OPTION_STD_MODE == "NOECC_4kx12" ? 16'b0000100100100100:
+ OPTION_STD_MODE == "NOECC_2kx24" ? 16'b0000101101101101:
+ 16'bx;
+
+localparam A_REPEAT = 24 / PORT_A_WIDTH;
+localparam B_REPEAT = 24 / PORT_B_WIDTH;
+
+assign A_DATA = {A_REPEAT{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
+assign B_DATA = {B_REPEAT{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
+
+NX_RAM_WRAP #(
+ .std_mode(OPTION_STD_MODE),
+ .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
+ .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
+ .pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
+ .pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
+ .raw_config0(4'b0000),
+ .raw_config1(raw_config1_val[15:0]),
+ .mem_ctxt($sformatf("%s",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))),
+) _TECHMAP_REPLACE_ (
+ .ACK(PORT_A_CLK),
+ //.ACKS(PORT_A_CLK),
+ //.ACKD(), // Not used in Non-ECC modes
+ //.ACKR(),
+ //.AR(),
+ //.ACOR(),
+ //.AERR(),
+ .ACS(PORT_A_CLK_EN),
+ .AWE(PORT_A_WR_EN),
+
+ .AA(PORT_A_ADDR),
+ .AI(A_DATA),
+ .AO(PORT_A_RD_DATA),
+
+ .BCK(PORT_B_CLK),
+ //.BCKC(PORT_B_CLK),
+ //.BCKD(), // Not used in Non-ECC modes
+ //.BCKR()
+ //.BR(),
+ //.BCOR(),
+ //.BERR(),
+ .BCS(PORT_B_CLK_EN),
+ .BWE(PORT_B_WR_EN),
+ .BA(PORT_B_ADDR),
+ .BI(B_DATA),
+ .BO(PORT_B_RD_DATA)
+);
+endmodule
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
new file mode 100644
index 000000000..919a02f82
--- /dev/null
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -0,0 +1,127 @@
+// NX_RAM related
+(* blackbox *)
+module NX_ECC(CKD, CHK, COR, ERR);
+ input CHK;
+ input CKD;
+ output COR;
+ output ERR;
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
+ input [1:0] DS;
+ input GS;
+ output [2:0] GVDN;
+ output [2:0] GVIN;
+ output [2:0] GVON;
+ input [5:0] LA;
+ output [3:0] PA;
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
+ input DCK;
+ output [5:0] DID;
+ input [5:0] DRA;
+ input [5:0] DRI;
+ input DRL;
+ output [5:0] DRO;
+ input [1:0] DS;
+ input FCK;
+ input [4:0] I;
+ output IO;
+ input R;
+ input SCK;
+ parameter data_size = 5;
+ parameter differential = "";
+ parameter drive = "";
+ parameter location = "";
+ parameter locked = 1'b0;
+ parameter outputCapacity = "";
+ parameter outputDelayLine = "";
+ parameter slewRate = "";
+ parameter spath_dynamic = 1'b0;
+ parameter standard = "";
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID);
+ input DCK;
+ output [5:0] DID;
+ input DIG;
+ input [5:0] DRA;
+ input [5:0] DRI;
+ input DRL;
+ output [5:0] DRO;
+ input [1:0] DS;
+ input FCK;
+ output FLD;
+ output FLG;
+ input FZ;
+ input IO;
+ output [4:0] O;
+ input R;
+ input SCK;
+ parameter data_size = 5;
+ parameter differential = "";
+ parameter dpath_dynamic = 1'b0;
+ parameter drive = "";
+ parameter inputDelayLine = "";
+ parameter inputSignalSlope = "";
+ parameter location = "";
+ parameter locked = 1'b0;
+ parameter standard = "";
+ parameter termination = "";
+ parameter terminationReference = "";
+ parameter turbo = "";
+ parameter weakTermination = "";
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO
+, DID);
+ input CCK;
+ input CI;
+ input CL;
+ input CR;
+ input DCK;
+ output [5:0] DID;
+ input DIG;
+ input [5:0] DRA;
+ input [5:0] DRI;
+ input DRL;
+ output [5:0] DRO;
+ input [1:0] DS;
+ input FCK;
+ output FLD;
+ output FLG;
+ input FZ;
+ input [4:0] I;
+ inout IO;
+ output [4:0] O;
+ input RRX;
+ input RTX;
+ input SCK;
+ parameter cpath_registered = 1'b0;
+ parameter data_size = 5;
+ parameter differential = "";
+ parameter dpath_dynamic = 1'b0;
+ parameter drive = "";
+ parameter inputDelayLine = "";
+ parameter inputSignalSlope = "";
+ parameter location = "";
+ parameter locked = 1'b0;
+ parameter outputCapacity = "";
+ parameter outputDelayLine = "";
+ parameter slewRate = "";
+ parameter spath_dynamic = 1'b0;
+ parameter standard = "";
+ parameter termination = "";
+ parameter terminationReference = "";
+ parameter turbo = "";
+ parameter weakTermination = "";
+endmodule
diff --git a/techlibs/nanoxplore/cells_bb_l.v b/techlibs/nanoxplore/cells_bb_l.v
new file mode 100644
index 000000000..376e524ce
--- /dev/null
+++ b/techlibs/nanoxplore/cells_bb_l.v
@@ -0,0 +1,2156 @@
+(* blackbox *)
+module NX_CKS(CKI, CMD, CKO);
+ input CKI;
+ output CKO;
+ input CMD;
+ parameter ck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CDC_L(CK1, CK2, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BI1, BI2, BI3, BI4, BI5, BI6, BO1
+, BO2, BO3, BO4, BO5, BO6, CI1, CI2, CI3, CI4, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DI1, DI2, DI3, DI4
+, DI5, DI6, DO1, DO2, DO3, DO4, DO5, DO6);
+ input AI1;
+ input AI2;
+ input AI3;
+ input AI4;
+ input AI5;
+ input AI6;
+ output AO1;
+ output AO2;
+ output AO3;
+ output AO4;
+ output AO5;
+ output AO6;
+ input BI1;
+ input BI2;
+ input BI3;
+ input BI4;
+ input BI5;
+ input BI6;
+ output BO1;
+ output BO2;
+ output BO3;
+ output BO4;
+ output BO5;
+ output BO6;
+ input CI1;
+ input CI2;
+ input CI3;
+ input CI4;
+ input CI5;
+ input CI6;
+ input CK1;
+ input CK2;
+ output CO1;
+ output CO2;
+ output CO3;
+ output CO4;
+ output CO5;
+ output CO6;
+ input DI1;
+ input DI2;
+ input DI3;
+ input DI4;
+ input DI5;
+ input DI6;
+ output DO1;
+ output DO2;
+ output DO3;
+ output DO4;
+ output DO5;
+ output DO6;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter cck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter dck_sel = 1'b0;
+ parameter gt0_bypass_reg1 = 1'b0;
+ parameter gt0_bypass_reg2 = 1'b0;
+ parameter gt1_bypass_reg1 = 1'b0;
+ parameter gt1_bypass_reg2 = 1'b0;
+ parameter link_BA = 1'b0;
+ parameter link_CB = 1'b0;
+ parameter link_DC = 1'b0;
+ parameter mode = 0;
+ parameter use_adest_arst = 2'b00;
+ parameter use_asrc_arst = 2'b00;
+ parameter use_bdest_arst = 2'b00;
+ parameter use_bsrc_arst = 2'b00;
+ parameter use_cdest_arst = 2'b00;
+ parameter use_csrc_arst = 2'b00;
+ parameter use_ddest_arst = 2'b00;
+ parameter use_dsrc_arst = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_DSP_L(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3
+, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24
+, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3
+, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37
+, CO57, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20
+, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41
+, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6
+, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27
+, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48
+, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13
+, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12
+, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33
+, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54
+, Z55, Z56);
+ input A1;
+ input A10;
+ input A11;
+ input A12;
+ input A13;
+ input A14;
+ input A15;
+ input A16;
+ input A17;
+ input A18;
+ input A19;
+ input A2;
+ input A20;
+ input A21;
+ input A22;
+ input A23;
+ input A24;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input A7;
+ input A8;
+ input A9;
+ input B1;
+ input B10;
+ input B11;
+ input B12;
+ input B13;
+ input B14;
+ input B15;
+ input B16;
+ input B17;
+ input B18;
+ input B2;
+ input B3;
+ input B4;
+ input B5;
+ input B6;
+ input B7;
+ input B8;
+ input B9;
+ input C1;
+ input C10;
+ input C11;
+ input C12;
+ input C13;
+ input C14;
+ input C15;
+ input C16;
+ input C17;
+ input C18;
+ input C19;
+ input C2;
+ input C20;
+ input C21;
+ input C22;
+ input C23;
+ input C24;
+ input C25;
+ input C26;
+ input C27;
+ input C28;
+ input C29;
+ input C3;
+ input C30;
+ input C31;
+ input C32;
+ input C33;
+ input C34;
+ input C35;
+ input C36;
+ input C4;
+ input C5;
+ input C6;
+ input C7;
+ input C8;
+ input C9;
+ input CAI1;
+ input CAI10;
+ input CAI11;
+ input CAI12;
+ input CAI13;
+ input CAI14;
+ input CAI15;
+ input CAI16;
+ input CAI17;
+ input CAI18;
+ input CAI19;
+ input CAI2;
+ input CAI20;
+ input CAI21;
+ input CAI22;
+ input CAI23;
+ input CAI24;
+ input CAI3;
+ input CAI4;
+ input CAI5;
+ input CAI6;
+ input CAI7;
+ input CAI8;
+ input CAI9;
+ output CAO1;
+ output CAO10;
+ output CAO11;
+ output CAO12;
+ output CAO13;
+ output CAO14;
+ output CAO15;
+ output CAO16;
+ output CAO17;
+ output CAO18;
+ output CAO19;
+ output CAO2;
+ output CAO20;
+ output CAO21;
+ output CAO22;
+ output CAO23;
+ output CAO24;
+ output CAO3;
+ output CAO4;
+ output CAO5;
+ output CAO6;
+ output CAO7;
+ output CAO8;
+ output CAO9;
+ input CBI1;
+ input CBI10;
+ input CBI11;
+ input CBI12;
+ input CBI13;
+ input CBI14;
+ input CBI15;
+ input CBI16;
+ input CBI17;
+ input CBI18;
+ input CBI2;
+ input CBI3;
+ input CBI4;
+ input CBI5;
+ input CBI6;
+ input CBI7;
+ input CBI8;
+ input CBI9;
+ output CBO1;
+ output CBO10;
+ output CBO11;
+ output CBO12;
+ output CBO13;
+ output CBO14;
+ output CBO15;
+ output CBO16;
+ output CBO17;
+ output CBO18;
+ output CBO2;
+ output CBO3;
+ output CBO4;
+ output CBO5;
+ output CBO6;
+ output CBO7;
+ output CBO8;
+ output CBO9;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO;
+ output CO37;
+ output CO57;
+ input CZI1;
+ input CZI10;
+ input CZI11;
+ input CZI12;
+ input CZI13;
+ input CZI14;
+ input CZI15;
+ input CZI16;
+ input CZI17;
+ input CZI18;
+ input CZI19;
+ input CZI2;
+ input CZI20;
+ input CZI21;
+ input CZI22;
+ input CZI23;
+ input CZI24;
+ input CZI25;
+ input CZI26;
+ input CZI27;
+ input CZI28;
+ input CZI29;
+ input CZI3;
+ input CZI30;
+ input CZI31;
+ input CZI32;
+ input CZI33;
+ input CZI34;
+ input CZI35;
+ input CZI36;
+ input CZI37;
+ input CZI38;
+ input CZI39;
+ input CZI4;
+ input CZI40;
+ input CZI41;
+ input CZI42;
+ input CZI43;
+ input CZI44;
+ input CZI45;
+ input CZI46;
+ input CZI47;
+ input CZI48;
+ input CZI49;
+ input CZI5;
+ input CZI50;
+ input CZI51;
+ input CZI52;
+ input CZI53;
+ input CZI54;
+ input CZI55;
+ input CZI56;
+ input CZI6;
+ input CZI7;
+ input CZI8;
+ input CZI9;
+ output CZO1;
+ output CZO10;
+ output CZO11;
+ output CZO12;
+ output CZO13;
+ output CZO14;
+ output CZO15;
+ output CZO16;
+ output CZO17;
+ output CZO18;
+ output CZO19;
+ output CZO2;
+ output CZO20;
+ output CZO21;
+ output CZO22;
+ output CZO23;
+ output CZO24;
+ output CZO25;
+ output CZO26;
+ output CZO27;
+ output CZO28;
+ output CZO29;
+ output CZO3;
+ output CZO30;
+ output CZO31;
+ output CZO32;
+ output CZO33;
+ output CZO34;
+ output CZO35;
+ output CZO36;
+ output CZO37;
+ output CZO38;
+ output CZO39;
+ output CZO4;
+ output CZO40;
+ output CZO41;
+ output CZO42;
+ output CZO43;
+ output CZO44;
+ output CZO45;
+ output CZO46;
+ output CZO47;
+ output CZO48;
+ output CZO49;
+ output CZO5;
+ output CZO50;
+ output CZO51;
+ output CZO52;
+ output CZO53;
+ output CZO54;
+ output CZO55;
+ output CZO56;
+ output CZO6;
+ output CZO7;
+ output CZO8;
+ output CZO9;
+ input D1;
+ input D10;
+ input D11;
+ input D12;
+ input D13;
+ input D14;
+ input D15;
+ input D16;
+ input D17;
+ input D18;
+ input D2;
+ input D3;
+ input D4;
+ input D5;
+ input D6;
+ input D7;
+ input D8;
+ input D9;
+ output OVF;
+ input R;
+ input RZ;
+ input WE;
+ output Z1;
+ output Z10;
+ output Z11;
+ output Z12;
+ output Z13;
+ output Z14;
+ output Z15;
+ output Z16;
+ output Z17;
+ output Z18;
+ output Z19;
+ output Z2;
+ output Z20;
+ output Z21;
+ output Z22;
+ output Z23;
+ output Z24;
+ output Z25;
+ output Z26;
+ output Z27;
+ output Z28;
+ output Z29;
+ output Z3;
+ output Z30;
+ output Z31;
+ output Z32;
+ output Z33;
+ output Z34;
+ output Z35;
+ output Z36;
+ output Z37;
+ output Z38;
+ output Z39;
+ output Z4;
+ output Z40;
+ output Z41;
+ output Z42;
+ output Z43;
+ output Z44;
+ output Z45;
+ output Z46;
+ output Z47;
+ output Z48;
+ output Z49;
+ output Z5;
+ output Z50;
+ output Z51;
+ output Z52;
+ output Z53;
+ output Z54;
+ output Z55;
+ output Z56;
+ output Z6;
+ output Z7;
+ output Z8;
+ output Z9;
+ parameter raw_config0 = 20'b00000000000000000000;
+ parameter raw_config1 = 19'b0000000000000000000;
+ parameter raw_config2 = 13'b0000000000000;
+ parameter raw_config3 = 7'b0000000;
+ parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_PLL_L(REF, FBK, R, VCO, LDFO, REFO, DIVO1, DIVO2, DIVP1, DIVP2, DIVP3, OSC, PLL_LOCKED, CAL_LOCKED);
+ output CAL_LOCKED;
+ output DIVO1;
+ output DIVO2;
+ output DIVP1;
+ output DIVP2;
+ output DIVP3;
+ input FBK;
+ output LDFO;
+ output OSC;
+ output PLL_LOCKED;
+ input R;
+ input REF;
+ output REFO;
+ output VCO;
+ parameter cfg_use_pll = 1'b1;
+ parameter clk_outdivo1 = 0;
+ parameter clk_outdivp1 = 0;
+ parameter clk_outdivp2 = 0;
+ parameter clk_outdivp3o2 = 0;
+ parameter ext_fbk_on = 1'b0;
+ parameter fbk_delay = 0;
+ parameter fbk_delay_on = 1'b0;
+ parameter fbk_intdiv = 2;
+ parameter location = "";
+ parameter pll_cpump = 3'b010;
+ parameter ref_intdiv = 0;
+ parameter ref_osc_on = 1'b0;
+ parameter wfg_sync_cal_lock = 1'b0;
+ parameter wfg_sync_pll_lock = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_WFG_L(R, SI, ZI, RDY, SO, ZO);
+ input R;
+ input RDY;
+ input SI;
+ output SO;
+ input ZI;
+ output ZO;
+ parameter delay = 0;
+ parameter delay_on = 1'b0;
+ parameter location = "";
+ parameter mode = 1'b0;
+ parameter pattern = 16'b0000000000000000;
+ parameter pattern_end = 1;
+ parameter wfg_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_CRX_L(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, BUF_FE_I, RST_N_I, CDR_R_I, CKG_RN_I, PLL_RN_I, TST_I1, TST_I2, TST_I3, TST_I4, LOS_O, DATA_O1, DATA_O2, DATA_O3
+, DATA_O4, DATA_O5, DATA_O6, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24
+, DATA_O25, DATA_O26, DATA_O27, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45
+, DATA_O46, DATA_O47, DATA_O48, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2
+, CH_COM_O3, CH_COM_O4, CH_COM_O5, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7
+, NIT_O8, D_ERR_O1, D_ERR_O2, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4
+, CH_F_O5, CH_F_O6, CH_F_O7, CH_F_O8, ALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOCK_O, RX_I, LINK);
+ input ALIGN_E_I;
+ output ALIGN_O;
+ input ALIGN_S_I;
+ input BUF_FE_I;
+ input BUF_R_I;
+ output BUSY_O;
+ input CDR_R_I;
+ output CH_A_O1;
+ output CH_A_O2;
+ output CH_A_O3;
+ output CH_A_O4;
+ output CH_A_O5;
+ output CH_A_O6;
+ output CH_A_O7;
+ output CH_A_O8;
+ output CH_COM_O1;
+ output CH_COM_O2;
+ output CH_COM_O3;
+ output CH_COM_O4;
+ output CH_COM_O5;
+ output CH_COM_O6;
+ output CH_COM_O7;
+ output CH_COM_O8;
+ output CH_F_O1;
+ output CH_F_O2;
+ output CH_F_O3;
+ output CH_F_O4;
+ output CH_F_O5;
+ output CH_F_O6;
+ output CH_F_O7;
+ output CH_F_O8;
+ output CH_K_O1;
+ output CH_K_O2;
+ output CH_K_O3;
+ output CH_K_O4;
+ output CH_K_O5;
+ output CH_K_O6;
+ output CH_K_O7;
+ output CH_K_O8;
+ input CKG_RN_I;
+ output DATA_O1;
+ output DATA_O10;
+ output DATA_O11;
+ output DATA_O12;
+ output DATA_O13;
+ output DATA_O14;
+ output DATA_O15;
+ output DATA_O16;
+ output DATA_O17;
+ output DATA_O18;
+ output DATA_O19;
+ output DATA_O2;
+ output DATA_O20;
+ output DATA_O21;
+ output DATA_O22;
+ output DATA_O23;
+ output DATA_O24;
+ output DATA_O25;
+ output DATA_O26;
+ output DATA_O27;
+ output DATA_O28;
+ output DATA_O29;
+ output DATA_O3;
+ output DATA_O30;
+ output DATA_O31;
+ output DATA_O32;
+ output DATA_O33;
+ output DATA_O34;
+ output DATA_O35;
+ output DATA_O36;
+ output DATA_O37;
+ output DATA_O38;
+ output DATA_O39;
+ output DATA_O4;
+ output DATA_O40;
+ output DATA_O41;
+ output DATA_O42;
+ output DATA_O43;
+ output DATA_O44;
+ output DATA_O45;
+ output DATA_O46;
+ output DATA_O47;
+ output DATA_O48;
+ output DATA_O49;
+ output DATA_O5;
+ output DATA_O50;
+ output DATA_O51;
+ output DATA_O52;
+ output DATA_O53;
+ output DATA_O54;
+ output DATA_O55;
+ output DATA_O56;
+ output DATA_O57;
+ output DATA_O58;
+ output DATA_O59;
+ output DATA_O6;
+ output DATA_O60;
+ output DATA_O61;
+ output DATA_O62;
+ output DATA_O63;
+ output DATA_O64;
+ output DATA_O7;
+ output DATA_O8;
+ output DATA_O9;
+ input DEC_E_I;
+ input DSCR_E_I;
+ output D_ERR_O1;
+ output D_ERR_O2;
+ output D_ERR_O3;
+ output D_ERR_O4;
+ output D_ERR_O5;
+ output D_ERR_O6;
+ output D_ERR_O7;
+ output D_ERR_O8;
+ inout [9:0] LINK;
+ output LOCK_O;
+ output LOS_O;
+ output NIT_O1;
+ output NIT_O2;
+ output NIT_O3;
+ output NIT_O4;
+ output NIT_O5;
+ output NIT_O6;
+ output NIT_O7;
+ output NIT_O8;
+ input OVS_BS_I1;
+ input OVS_BS_I2;
+ input PLL_RN_I;
+ input REP_E_I;
+ input RST_N_I;
+ input RX_I;
+ input TST_I1;
+ input TST_I2;
+ input TST_I3;
+ input TST_I4;
+ output TST_O1;
+ output TST_O2;
+ output TST_O3;
+ output TST_O4;
+ output TST_O5;
+ output TST_O6;
+ output TST_O7;
+ output TST_O8;
+ parameter location = "";
+ parameter pcs_8b_dscr_sel = 1'b0;
+ parameter pcs_align_bypass = 1'b0;
+ parameter pcs_buffers_bypass = 1'b0;
+ parameter pcs_buffers_use_cdc = 1'b0;
+ parameter pcs_bypass_pma_cdc = 1'b0;
+ parameter pcs_bypass_usr_cdc = 1'b0;
+ parameter pcs_comma_mask = 10'b0000000000;
+ parameter pcs_debug_en = 1'b0;
+ parameter pcs_dec_bypass = 1'b0;
+ parameter pcs_dscr_bypass = 1'b0;
+ parameter pcs_el_buff_diff_bef_comp = 3'b000;
+ parameter pcs_el_buff_max_comp = 3'b000;
+ parameter pcs_el_buff_only_one_skp = 1'b0;
+ parameter pcs_el_buff_skp_char_0 = 9'b000000000;
+ parameter pcs_el_buff_skp_char_1 = 9'b000000000;
+ parameter pcs_el_buff_skp_char_2 = 9'b000000000;
+ parameter pcs_el_buff_skp_char_3 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_0 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_1 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_2 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_3 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_size = 2'b00;
+ parameter pcs_el_buff_skp_seq_size = 2'b00;
+ parameter pcs_el_buff_underflow_handle = 1'b0;
+ parameter pcs_fsm_sel = 2'b00;
+ parameter pcs_fsm_watchdog_en = 1'b0;
+ parameter pcs_loopback = 1'b0;
+ parameter pcs_m_comma_en = 1'b0;
+ parameter pcs_m_comma_val = 10'b0000000000;
+ parameter pcs_nb_comma_bef_realign = 2'b00;
+ parameter pcs_p_comma_en = 1'b0;
+ parameter pcs_p_comma_val = 10'b0000000000;
+ parameter pcs_polarity = 1'b0;
+ parameter pcs_protocol_size = 1'b0;
+ parameter pcs_replace_bypass = 1'b0;
+ parameter pcs_sync_supported = 1'b0;
+ parameter pma_cdr_cp = 4'b0000;
+ parameter pma_clk_pos = 1'b0;
+ parameter pma_ctrl_term = 6'b000000;
+ parameter pma_loopback = 1'b0;
+ parameter pma_pll_cpump_n = 3'b000;
+ parameter pma_pll_divf = 2'b00;
+ parameter pma_pll_divf_en_n = 1'b0;
+ parameter pma_pll_divm = 2'b00;
+ parameter pma_pll_divm_en_n = 1'b0;
+ parameter pma_pll_divn = 1'b0;
+ parameter pma_pll_divn_en_n = 1'b0;
+ parameter test = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_CTX_L(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5
+, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I
+, TST_I1, TST_I2, TST_I3, TST_I4, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17
+, DATA_I18, DATA_I19, DATA_I20, DATA_I21, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38
+, DATA_I39, DATA_I40, DATA_I41, DATA_I42, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59
+, DATA_I60, DATA_I61, DATA_I62, DATA_I63, DATA_I64, TST_O1, TST_O2, TST_O3, TST_O4, BUSY_O, CLK_E_I, TX_O, LINK);
+ output BUSY_O;
+ input CH_K_I1;
+ input CH_K_I2;
+ input CH_K_I3;
+ input CH_K_I4;
+ input CH_K_I5;
+ input CH_K_I6;
+ input CH_K_I7;
+ input CH_K_I8;
+ input CLK_E_I;
+ input DATA_I1;
+ input DATA_I10;
+ input DATA_I11;
+ input DATA_I12;
+ input DATA_I13;
+ input DATA_I14;
+ input DATA_I15;
+ input DATA_I16;
+ input DATA_I17;
+ input DATA_I18;
+ input DATA_I19;
+ input DATA_I2;
+ input DATA_I20;
+ input DATA_I21;
+ input DATA_I22;
+ input DATA_I23;
+ input DATA_I24;
+ input DATA_I25;
+ input DATA_I26;
+ input DATA_I27;
+ input DATA_I28;
+ input DATA_I29;
+ input DATA_I3;
+ input DATA_I30;
+ input DATA_I31;
+ input DATA_I32;
+ input DATA_I33;
+ input DATA_I34;
+ input DATA_I35;
+ input DATA_I36;
+ input DATA_I37;
+ input DATA_I38;
+ input DATA_I39;
+ input DATA_I4;
+ input DATA_I40;
+ input DATA_I41;
+ input DATA_I42;
+ input DATA_I43;
+ input DATA_I44;
+ input DATA_I45;
+ input DATA_I46;
+ input DATA_I47;
+ input DATA_I48;
+ input DATA_I49;
+ input DATA_I5;
+ input DATA_I50;
+ input DATA_I51;
+ input DATA_I52;
+ input DATA_I53;
+ input DATA_I54;
+ input DATA_I55;
+ input DATA_I56;
+ input DATA_I57;
+ input DATA_I58;
+ input DATA_I59;
+ input DATA_I6;
+ input DATA_I60;
+ input DATA_I61;
+ input DATA_I62;
+ input DATA_I63;
+ input DATA_I64;
+ input DATA_I7;
+ input DATA_I8;
+ input DATA_I9;
+ input ENC_E_I1;
+ input ENC_E_I2;
+ input ENC_E_I3;
+ input ENC_E_I4;
+ input ENC_E_I5;
+ input ENC_E_I6;
+ input ENC_E_I7;
+ input ENC_E_I8;
+ input EOF_I1;
+ input EOF_I2;
+ input EOF_I3;
+ input EOF_I4;
+ input EOF_I5;
+ input EOF_I6;
+ input EOF_I7;
+ input EOF_I8;
+ input EOMF_I1;
+ input EOMF_I2;
+ input EOMF_I3;
+ input EOMF_I4;
+ input EOMF_I5;
+ input EOMF_I6;
+ input EOMF_I7;
+ input EOMF_I8;
+ inout [19:0] LINK;
+ input REP_E_I;
+ input RST_N_I;
+ input SCR_E_I1;
+ input SCR_E_I2;
+ input SCR_E_I3;
+ input SCR_E_I4;
+ input SCR_E_I5;
+ input SCR_E_I6;
+ input SCR_E_I7;
+ input SCR_E_I8;
+ input TST_I1;
+ input TST_I2;
+ input TST_I3;
+ input TST_I4;
+ output TST_O1;
+ output TST_O2;
+ output TST_O3;
+ output TST_O4;
+ output TX_O;
+ parameter location = "";
+ parameter pcs_8b_scr_sel = 1'b0;
+ parameter pcs_bypass_pma_cdc = 1'b0;
+ parameter pcs_bypass_usr_cdc = 1'b0;
+ parameter pcs_enc_bypass = 1'b0;
+ parameter pcs_esistream_fsm_en = 1'b0;
+ parameter pcs_loopback = 1'b0;
+ parameter pcs_polarity = 1'b0;
+ parameter pcs_protocol_size = 1'b0;
+ parameter pcs_replace_bypass = 1'b0;
+ parameter pcs_scr_bypass = 1'b0;
+ parameter pcs_scr_init = 17'b00000000000000000;
+ parameter pcs_sync_supported = 1'b0;
+ parameter pma_clk_pos = 1'b0;
+ parameter pma_loopback = 1'b0;
+ parameter test = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1
+, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR, P1RO1
+, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR
+, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI, P3RL
+, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO, P4RI
+, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4
+, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2, P6EI3
+, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2
+, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1
+, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI, P9CTO
+, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO, P10CTI
+, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR, P11CO
+, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL, P12CR
+, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1, P13CL
+, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P14CI1
+, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5
+, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4
+, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2, P16RO3
+, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2
+, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1
+, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL, P19RR
+, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI, P20RL
+, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO, P21RI
+, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER, P22EO
+, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL, P23ER
+, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EL
+, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5
+, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4
+, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3
+, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2
+, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CI2, P29CI3, P29CI4, P29CI5, P29CL, P29CR
+, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1, P30CL
+, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P31CI1
+, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EL, P31ER, P31EO, P31RI, P31RL, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5
+, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4
+, P32RO5, P33CI1, P33CL, P33CR, P33CO, P33CTI, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3
+, P33RO4, P33RO5, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EL, P34ER, P34EO, P34RI, P34RL, P34RR, P34RO1, P34RO2
+, P34RO3, P34RO4, P34RO5);
+ output C1RED;
+ input C1RNE;
+ input C1RS;
+ input C1RW1;
+ input C1RW2;
+ input C1RW3;
+ input C1TS;
+ input C1TW;
+ output C2RED;
+ input C2RNE;
+ input C2RS;
+ input C2RW1;
+ input C2RW2;
+ input C2RW3;
+ input C2TS;
+ input C2TW;
+ input CAD1;
+ input CAD2;
+ input CAD3;
+ input CAD4;
+ input CAD5;
+ input CAD6;
+ output CAL;
+ input CAN1;
+ input CAN2;
+ input CAN3;
+ input CAN4;
+ input CAP1;
+ input CAP2;
+ input CAP3;
+ input CAP4;
+ input CAT1;
+ input CAT2;
+ input CAT3;
+ input CAT4;
+ input CCK;
+ output CKO1;
+ output CKO2;
+ input CTCK;
+ input DC;
+ input DCK;
+ input DIG;
+ input DIS;
+ input DOG;
+ input DOS;
+ input DPAG;
+ input DPAS;
+ input DQSG;
+ input DQSS;
+ input DRA1;
+ input DRA2;
+ input DRA3;
+ input DRA4;
+ input DRA5;
+ input DRA6;
+ input DRI1;
+ input DRI2;
+ input DRI3;
+ input DRI4;
+ input DRI5;
+ input DRI6;
+ input DRL;
+ output DRO1;
+ output DRO2;
+ output DRO3;
+ output DRO4;
+ output DRO5;
+ output DRO6;
+ input DS1;
+ input DS2;
+ input FA1;
+ input FA2;
+ input FA3;
+ input FA4;
+ input FA5;
+ input FA6;
+ output FLD;
+ output FLG;
+ input FZ;
+ input P10CI1;
+ input P10CL;
+ output P10CO;
+ input P10CR;
+ input P10CTI;
+ output P10CTO;
+ input P10EI1;
+ input P10EI2;
+ input P10EI3;
+ input P10EI4;
+ input P10EI5;
+ input P10EL;
+ output P10EO;
+ input P10ER;
+ input P10RI;
+ input P10RL;
+ output P10RO1;
+ output P10RO2;
+ output P10RO3;
+ output P10RO4;
+ output P10RO5;
+ input P10RR;
+ input P11CI1;
+ input P11CL;
+ output P11CO;
+ input P11CR;
+ input P11CTI;
+ output P11CTO;
+ input P11EI1;
+ input P11EI2;
+ input P11EI3;
+ input P11EI4;
+ input P11EI5;
+ input P11EL;
+ output P11EO;
+ input P11ER;
+ input P11RI;
+ input P11RL;
+ output P11RO1;
+ output P11RO2;
+ output P11RO3;
+ output P11RO4;
+ output P11RO5;
+ input P11RR;
+ input P12CI1;
+ input P12CL;
+ output P12CO;
+ input P12CR;
+ input P12CTI;
+ output P12CTO;
+ input P12EI1;
+ input P12EI2;
+ input P12EI3;
+ input P12EI4;
+ input P12EI5;
+ input P12EL;
+ output P12EO;
+ input P12ER;
+ input P12RI;
+ input P12RL;
+ output P12RO1;
+ output P12RO2;
+ output P12RO3;
+ output P12RO4;
+ output P12RO5;
+ input P12RR;
+ input P13CI1;
+ input P13CL;
+ output P13CO;
+ input P13CR;
+ input P13CTI;
+ output P13CTO;
+ input P13EI1;
+ input P13EI2;
+ input P13EI3;
+ input P13EI4;
+ input P13EI5;
+ input P13EL;
+ output P13EO;
+ input P13ER;
+ input P13RI;
+ input P13RL;
+ output P13RO1;
+ output P13RO2;
+ output P13RO3;
+ output P13RO4;
+ output P13RO5;
+ input P13RR;
+ input P14CI1;
+ input P14CL;
+ output P14CO;
+ input P14CR;
+ input P14CTI;
+ output P14CTO;
+ input P14EI1;
+ input P14EI2;
+ input P14EI3;
+ input P14EI4;
+ input P14EI5;
+ input P14EL;
+ output P14EO;
+ input P14ER;
+ input P14RI;
+ input P14RL;
+ output P14RO1;
+ output P14RO2;
+ output P14RO3;
+ output P14RO4;
+ output P14RO5;
+ input P14RR;
+ input P15CI1;
+ input P15CL;
+ output P15CO;
+ input P15CR;
+ input P15CTI;
+ output P15CTO;
+ input P15EI1;
+ input P15EI2;
+ input P15EI3;
+ input P15EI4;
+ input P15EI5;
+ input P15EL;
+ output P15EO;
+ input P15ER;
+ input P15RI;
+ input P15RL;
+ output P15RO1;
+ output P15RO2;
+ output P15RO3;
+ output P15RO4;
+ output P15RO5;
+ input P15RR;
+ input P16CI1;
+ input P16CL;
+ output P16CO;
+ input P16CR;
+ input P16CTI;
+ output P16CTO;
+ input P16EI1;
+ input P16EI2;
+ input P16EI3;
+ input P16EI4;
+ input P16EI5;
+ input P16EL;
+ output P16EO;
+ input P16ER;
+ input P16RI;
+ input P16RL;
+ output P16RO1;
+ output P16RO2;
+ output P16RO3;
+ output P16RO4;
+ output P16RO5;
+ input P16RR;
+ input P17CI1;
+ input P17CL;
+ output P17CO;
+ input P17CR;
+ input P17CTI;
+ output P17CTO;
+ input P17EI1;
+ input P17EI2;
+ input P17EI3;
+ input P17EI4;
+ input P17EI5;
+ input P17EL;
+ output P17EO;
+ input P17ER;
+ input P17RI;
+ input P17RL;
+ output P17RO1;
+ output P17RO2;
+ output P17RO3;
+ output P17RO4;
+ output P17RO5;
+ input P17RR;
+ input P18CI1;
+ input P18CL;
+ output P18CO;
+ input P18CR;
+ input P18CTI;
+ output P18CTO;
+ input P18EI1;
+ input P18EI2;
+ input P18EI3;
+ input P18EI4;
+ input P18EI5;
+ input P18EL;
+ output P18EO;
+ input P18ER;
+ input P18RI;
+ input P18RL;
+ output P18RO1;
+ output P18RO2;
+ output P18RO3;
+ output P18RO4;
+ output P18RO5;
+ input P18RR;
+ input P19CI1;
+ input P19CL;
+ output P19CO;
+ input P19CR;
+ input P19CTI;
+ output P19CTO;
+ input P19EI1;
+ input P19EI2;
+ input P19EI3;
+ input P19EI4;
+ input P19EI5;
+ input P19EL;
+ output P19EO;
+ input P19ER;
+ input P19RI;
+ input P19RL;
+ output P19RO1;
+ output P19RO2;
+ output P19RO3;
+ output P19RO4;
+ output P19RO5;
+ input P19RR;
+ input P1CI1;
+ input P1CL;
+ output P1CO;
+ input P1CR;
+ input P1CTI;
+ output P1CTO;
+ input P1EI1;
+ input P1EI2;
+ input P1EI3;
+ input P1EI4;
+ input P1EI5;
+ input P1EL;
+ output P1EO;
+ input P1ER;
+ input P1RI;
+ input P1RL;
+ output P1RO1;
+ output P1RO2;
+ output P1RO3;
+ output P1RO4;
+ output P1RO5;
+ input P1RR;
+ input P20CI1;
+ input P20CL;
+ output P20CO;
+ input P20CR;
+ input P20CTI;
+ output P20CTO;
+ input P20EI1;
+ input P20EI2;
+ input P20EI3;
+ input P20EI4;
+ input P20EI5;
+ input P20EL;
+ output P20EO;
+ input P20ER;
+ input P20RI;
+ input P20RL;
+ output P20RO1;
+ output P20RO2;
+ output P20RO3;
+ output P20RO4;
+ output P20RO5;
+ input P20RR;
+ input P21CI1;
+ input P21CL;
+ output P21CO;
+ input P21CR;
+ input P21CTI;
+ output P21CTO;
+ input P21EI1;
+ input P21EI2;
+ input P21EI3;
+ input P21EI4;
+ input P21EI5;
+ input P21EL;
+ output P21EO;
+ input P21ER;
+ input P21RI;
+ input P21RL;
+ output P21RO1;
+ output P21RO2;
+ output P21RO3;
+ output P21RO4;
+ output P21RO5;
+ input P21RR;
+ input P22CI1;
+ input P22CL;
+ output P22CO;
+ input P22CR;
+ input P22CTI;
+ output P22CTO;
+ input P22EI1;
+ input P22EI2;
+ input P22EI3;
+ input P22EI4;
+ input P22EI5;
+ input P22EL;
+ output P22EO;
+ input P22ER;
+ input P22RI;
+ input P22RL;
+ output P22RO1;
+ output P22RO2;
+ output P22RO3;
+ output P22RO4;
+ output P22RO5;
+ input P22RR;
+ input P23CI1;
+ input P23CL;
+ output P23CO;
+ input P23CR;
+ input P23CTI;
+ output P23CTO;
+ input P23EI1;
+ input P23EI2;
+ input P23EI3;
+ input P23EI4;
+ input P23EI5;
+ input P23EL;
+ output P23EO;
+ input P23ER;
+ input P23RI;
+ input P23RL;
+ output P23RO1;
+ output P23RO2;
+ output P23RO3;
+ output P23RO4;
+ output P23RO5;
+ input P23RR;
+ input P24CI1;
+ input P24CL;
+ output P24CO;
+ input P24CR;
+ input P24CTI;
+ output P24CTO;
+ input P24EI1;
+ input P24EI2;
+ input P24EI3;
+ input P24EI4;
+ input P24EI5;
+ input P24EL;
+ output P24EO;
+ input P24ER;
+ input P24RI;
+ input P24RL;
+ output P24RO1;
+ output P24RO2;
+ output P24RO3;
+ output P24RO4;
+ output P24RO5;
+ input P24RR;
+ input P25CI1;
+ input P25CL;
+ output P25CO;
+ input P25CR;
+ input P25CTI;
+ output P25CTO;
+ input P25EI1;
+ input P25EI2;
+ input P25EI3;
+ input P25EI4;
+ input P25EI5;
+ input P25EL;
+ output P25EO;
+ input P25ER;
+ input P25RI;
+ input P25RL;
+ output P25RO1;
+ output P25RO2;
+ output P25RO3;
+ output P25RO4;
+ output P25RO5;
+ input P25RR;
+ input P26CI1;
+ input P26CL;
+ output P26CO;
+ input P26CR;
+ input P26CTI;
+ output P26CTO;
+ input P26EI1;
+ input P26EI2;
+ input P26EI3;
+ input P26EI4;
+ input P26EI5;
+ input P26EL;
+ output P26EO;
+ input P26ER;
+ input P26RI;
+ input P26RL;
+ output P26RO1;
+ output P26RO2;
+ output P26RO3;
+ output P26RO4;
+ output P26RO5;
+ input P26RR;
+ input P27CI1;
+ input P27CL;
+ output P27CO;
+ input P27CR;
+ input P27CTI;
+ output P27CTO;
+ input P27EI1;
+ input P27EI2;
+ input P27EI3;
+ input P27EI4;
+ input P27EI5;
+ input P27EL;
+ output P27EO;
+ input P27ER;
+ input P27RI;
+ input P27RL;
+ output P27RO1;
+ output P27RO2;
+ output P27RO3;
+ output P27RO4;
+ output P27RO5;
+ input P27RR;
+ input P28CI1;
+ input P28CL;
+ output P28CO;
+ input P28CR;
+ input P28CTI;
+ output P28CTO;
+ input P28EI1;
+ input P28EI2;
+ input P28EI3;
+ input P28EI4;
+ input P28EI5;
+ input P28EL;
+ output P28EO;
+ input P28ER;
+ input P28RI;
+ input P28RL;
+ output P28RO1;
+ output P28RO2;
+ output P28RO3;
+ output P28RO4;
+ output P28RO5;
+ input P28RR;
+ input P29CI1;
+ input P29CI2;
+ input P29CI3;
+ input P29CI4;
+ input P29CI5;
+ input P29CL;
+ output P29CO;
+ input P29CR;
+ input P29CTI;
+ output P29CTO;
+ input P29EI1;
+ input P29EI2;
+ input P29EI3;
+ input P29EI4;
+ input P29EI5;
+ input P29EL;
+ output P29EO;
+ input P29ER;
+ input P29RI;
+ input P29RL;
+ output P29RO1;
+ output P29RO2;
+ output P29RO3;
+ output P29RO4;
+ output P29RO5;
+ input P29RR;
+ input P2CI1;
+ input P2CL;
+ output P2CO;
+ input P2CR;
+ input P2CTI;
+ output P2CTO;
+ input P2EI1;
+ input P2EI2;
+ input P2EI3;
+ input P2EI4;
+ input P2EI5;
+ input P2EL;
+ output P2EO;
+ input P2ER;
+ input P2RI;
+ input P2RL;
+ output P2RO1;
+ output P2RO2;
+ output P2RO3;
+ output P2RO4;
+ output P2RO5;
+ input P2RR;
+ input P30CI1;
+ input P30CL;
+ output P30CO;
+ input P30CR;
+ input P30CTI;
+ output P30CTO;
+ input P30EI1;
+ input P30EI2;
+ input P30EI3;
+ input P30EI4;
+ input P30EI5;
+ input P30EL;
+ output P30EO;
+ input P30ER;
+ input P30RI;
+ input P30RL;
+ output P30RO1;
+ output P30RO2;
+ output P30RO3;
+ output P30RO4;
+ output P30RO5;
+ input P30RR;
+ input P31CI1;
+ input P31CL;
+ output P31CO;
+ input P31CR;
+ input P31CTI;
+ output P31CTO;
+ input P31EI1;
+ input P31EI2;
+ input P31EI3;
+ input P31EI4;
+ input P31EI5;
+ input P31EL;
+ output P31EO;
+ input P31ER;
+ input P31RI;
+ input P31RL;
+ output P31RO1;
+ output P31RO2;
+ output P31RO3;
+ output P31RO4;
+ output P31RO5;
+ input P31RR;
+ input P32CI1;
+ input P32CL;
+ output P32CO;
+ input P32CR;
+ input P32CTI;
+ output P32CTO;
+ input P32EI1;
+ input P32EI2;
+ input P32EI3;
+ input P32EI4;
+ input P32EI5;
+ input P32EL;
+ output P32EO;
+ input P32ER;
+ input P32RI;
+ input P32RL;
+ output P32RO1;
+ output P32RO2;
+ output P32RO3;
+ output P32RO4;
+ output P32RO5;
+ input P32RR;
+ input P33CI1;
+ input P33CL;
+ output P33CO;
+ input P33CR;
+ input P33CTI;
+ output P33CTO;
+ input P33EI1;
+ input P33EI2;
+ input P33EI3;
+ input P33EI4;
+ input P33EI5;
+ input P33EL;
+ output P33EO;
+ input P33ER;
+ input P33RI;
+ input P33RL;
+ output P33RO1;
+ output P33RO2;
+ output P33RO3;
+ output P33RO4;
+ output P33RO5;
+ input P33RR;
+ input P34CI1;
+ input P34CL;
+ output P34CO;
+ input P34CR;
+ input P34CTI;
+ output P34CTO;
+ input P34EI1;
+ input P34EI2;
+ input P34EI3;
+ input P34EI4;
+ input P34EI5;
+ input P34EL;
+ output P34EO;
+ input P34ER;
+ input P34RI;
+ input P34RL;
+ output P34RO1;
+ output P34RO2;
+ output P34RO3;
+ output P34RO4;
+ output P34RO5;
+ input P34RR;
+ input P3CI1;
+ input P3CL;
+ output P3CO;
+ input P3CR;
+ input P3CTI;
+ output P3CTO;
+ input P3EI1;
+ input P3EI2;
+ input P3EI3;
+ input P3EI4;
+ input P3EI5;
+ input P3EL;
+ output P3EO;
+ input P3ER;
+ input P3RI;
+ input P3RL;
+ output P3RO1;
+ output P3RO2;
+ output P3RO3;
+ output P3RO4;
+ output P3RO5;
+ input P3RR;
+ input P4CI1;
+ input P4CL;
+ output P4CO;
+ input P4CR;
+ input P4CTI;
+ output P4CTO;
+ input P4EI1;
+ input P4EI2;
+ input P4EI3;
+ input P4EI4;
+ input P4EI5;
+ input P4EL;
+ output P4EO;
+ input P4ER;
+ input P4RI;
+ input P4RL;
+ output P4RO1;
+ output P4RO2;
+ output P4RO3;
+ output P4RO4;
+ output P4RO5;
+ input P4RR;
+ input P5CI1;
+ input P5CI2;
+ input P5CI3;
+ input P5CI4;
+ input P5CI5;
+ input P5CL;
+ output P5CO;
+ input P5CR;
+ input P5CTI;
+ output P5CTO;
+ input P5EI1;
+ input P5EI2;
+ input P5EI3;
+ input P5EI4;
+ input P5EI5;
+ input P5EL;
+ output P5EO;
+ input P5ER;
+ input P5RI;
+ input P5RL;
+ output P5RO1;
+ output P5RO2;
+ output P5RO3;
+ output P5RO4;
+ output P5RO5;
+ input P5RR;
+ input P6CI1;
+ input P6CL;
+ output P6CO;
+ input P6CR;
+ input P6CTI;
+ output P6CTO;
+ input P6EI1;
+ input P6EI2;
+ input P6EI3;
+ input P6EI4;
+ input P6EI5;
+ input P6EL;
+ output P6EO;
+ input P6ER;
+ input P6RI;
+ input P6RL;
+ output P6RO1;
+ output P6RO2;
+ output P6RO3;
+ output P6RO4;
+ output P6RO5;
+ input P6RR;
+ input P7CI1;
+ input P7CL;
+ output P7CO;
+ input P7CR;
+ input P7CTI;
+ output P7CTO;
+ input P7EI1;
+ input P7EI2;
+ input P7EI3;
+ input P7EI4;
+ input P7EI5;
+ input P7EL;
+ output P7EO;
+ input P7ER;
+ input P7RI;
+ input P7RL;
+ output P7RO1;
+ output P7RO2;
+ output P7RO3;
+ output P7RO4;
+ output P7RO5;
+ input P7RR;
+ input P8CI1;
+ input P8CL;
+ output P8CO;
+ input P8CR;
+ input P8CTI;
+ output P8CTO;
+ input P8EI1;
+ input P8EI2;
+ input P8EI3;
+ input P8EI4;
+ input P8EI5;
+ input P8EL;
+ output P8EO;
+ input P8ER;
+ input P8RI;
+ input P8RL;
+ output P8RO1;
+ output P8RO2;
+ output P8RO3;
+ output P8RO4;
+ output P8RO5;
+ input P8RR;
+ input P9CI1;
+ input P9CL;
+ output P9CO;
+ input P9CR;
+ input P9CTI;
+ output P9CTO;
+ input P9EI1;
+ input P9EI2;
+ input P9EI3;
+ input P9EI4;
+ input P9EI5;
+ input P9EL;
+ output P9EO;
+ input P9ER;
+ input P9RI;
+ input P9RL;
+ output P9RO1;
+ output P9RO2;
+ output P9RO3;
+ output P9RO4;
+ output P9RO5;
+ input P9RR;
+ input RRCK1;
+ input RRCK2;
+ input RTCK1;
+ input RTCK2;
+ input WRCK1;
+ input WRCK2;
+ input WTCK1;
+ input WTCK2;
+ parameter div_rx1 = 4'b0000;
+ parameter div_rx2 = 4'b0000;
+ parameter div_tx1 = 4'b0000;
+ parameter div_tx2 = 4'b0000;
+ parameter mode_io_cal = 1'b0;
+ parameter mode_side1 = 0;
+ parameter mode_side2 = 0;
+ parameter pads_dict = "";
+ parameter pads_path = "";
+ parameter sel_clk_out1 = 1'b0;
+ parameter sel_clk_out2 = 1'b0;
+ parameter sel_clkr_rx1 = 1'b0;
+ parameter sel_clkr_rx2 = 1'b0;
+ parameter sel_clkw_rx1 = 2'b00;
+ parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_PMA_L(CLK_USER_I, CLK_REF_I, PRE_SG_I, PRE_EN_I, PRE_IS_I1, PRE_IS_I2, PRE_IS_I3, PRE_IS_I4, MAIN_SG_I, MAIN_EN_I1, MAIN_EN_I2, MAIN_EN_I3, MAIN_EN_I4, MAIN_EN_I5, MAIN_EN_I6, MARG_S_I1, MARG_S_I2, MARG_S_I3, MARG_S_I4, MARG_IS_I1, MARG_IS_I2
+, MARG_IS_I3, MARG_IS_I4, MARG_SV_I1, MARG_SV_I2, MARG_SV_I3, MARG_SV_I4, MARG_SV_I5, MARG_ISV_I1, MARG_ISV_I2, MARG_ISV_I3, MARG_ISV_I4, MARG_ISV_I5, POST_EN_I1, POST_EN_I2, POST_EN_I3, POST_EN_I4, POST_EN_I5, POST_SG_I, POST_IS_I1, POST_IS_I2, POST_IS_I3
+, POST_IS_I4, POST_ISV_I1, POST_ISV_I2, POST_ISV_I3, POST_ISV_I4, TX_SEL_I1, TX_SEL_I2, TX_SEL_I3, TX_SEL_I4, TX_SEL_I5, TX_SEL_I6, CT_CAP_I1, CT_CAP_I2, CT_CAP_I3, CT_CAP_I4, CT_RESP_I1, CT_RESP_I2, CT_RESP_I3, CT_RESP_I4, CT_RESN_I1, CT_RESN_I2
+, CT_RESN_I3, CT_RESN_I4, M_EYE_I, RX_SEL_I1, RX_SEL_I2, RX_SEL_I3, RX_SEL_I4, RX_SEL_I5, RX_SEL_I6, PLL_RN_I, RST_N_I, CAL_1P_I1, CAL_1P_I2, CAL_1P_I3, CAL_1P_I4, CAL_1P_I5, CAL_1P_I6, CAL_1P_I7, CAL_1P_I8, CAL_2N_I1, CAL_2N_I2
+, CAL_2N_I3, CAL_2N_I4, CAL_2N_I5, CAL_2N_I6, CAL_2N_I7, CAL_2N_I8, CAL_3N_I1, CAL_3N_I2, CAL_3N_I3, CAL_3N_I4, CAL_3N_I5, CAL_3N_I6, CAL_3N_I7, CAL_3N_I8, CAL_4P_I1, CAL_4P_I2, CAL_4P_I3, CAL_4P_I4, CAL_4P_I5, CAL_4P_I6, CAL_4P_I7
+, CAL_4P_I8, CAL_SEL_I1, CAL_SEL_I2, CAL_SEL_I3, CAL_SEL_I4, CAL_E_I, LOCK_E_I, OVS_E_I, TST_I1, TST_I2, TST_I3, TST_I4, TST_I5, TST_I6, TST_I7, TST_I8, CLK_O, LOCK_O, CAL_O, TST_O1, TST_O2
+, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, CLK_EXT_I, LINK_TX1, LINK_TX2, LINK_TX3, LINK_TX4, LINK_TX5, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3, LINK_RX4, LINK_RX5, LINK_TX0);
+ input CAL_1P_I1;
+ input CAL_1P_I2;
+ input CAL_1P_I3;
+ input CAL_1P_I4;
+ input CAL_1P_I5;
+ input CAL_1P_I6;
+ input CAL_1P_I7;
+ input CAL_1P_I8;
+ input CAL_2N_I1;
+ input CAL_2N_I2;
+ input CAL_2N_I3;
+ input CAL_2N_I4;
+ input CAL_2N_I5;
+ input CAL_2N_I6;
+ input CAL_2N_I7;
+ input CAL_2N_I8;
+ input CAL_3N_I1;
+ input CAL_3N_I2;
+ input CAL_3N_I3;
+ input CAL_3N_I4;
+ input CAL_3N_I5;
+ input CAL_3N_I6;
+ input CAL_3N_I7;
+ input CAL_3N_I8;
+ input CAL_4P_I1;
+ input CAL_4P_I2;
+ input CAL_4P_I3;
+ input CAL_4P_I4;
+ input CAL_4P_I5;
+ input CAL_4P_I6;
+ input CAL_4P_I7;
+ input CAL_4P_I8;
+ input CAL_E_I;
+ output CAL_O;
+ input CAL_SEL_I1;
+ input CAL_SEL_I2;
+ input CAL_SEL_I3;
+ input CAL_SEL_I4;
+ input CLK_EXT_I;
+ output CLK_O;
+ input CLK_REF_I;
+ input CLK_USER_I;
+ input CT_CAP_I1;
+ input CT_CAP_I2;
+ input CT_CAP_I3;
+ input CT_CAP_I4;
+ input CT_RESN_I1;
+ input CT_RESN_I2;
+ input CT_RESN_I3;
+ input CT_RESN_I4;
+ input CT_RESP_I1;
+ input CT_RESP_I2;
+ input CT_RESP_I3;
+ input CT_RESP_I4;
+ inout [9:0] LINK_RX0;
+ inout [9:0] LINK_RX1;
+ inout [9:0] LINK_RX2;
+ inout [9:0] LINK_RX3;
+ inout [9:0] LINK_RX4;
+ inout [9:0] LINK_RX5;
+ inout [19:0] LINK_TX0;
+ inout [19:0] LINK_TX1;
+ inout [19:0] LINK_TX2;
+ inout [19:0] LINK_TX3;
+ inout [19:0] LINK_TX4;
+ inout [19:0] LINK_TX5;
+ input LOCK_E_I;
+ output LOCK_O;
+ input MAIN_EN_I1;
+ input MAIN_EN_I2;
+ input MAIN_EN_I3;
+ input MAIN_EN_I4;
+ input MAIN_EN_I5;
+ input MAIN_EN_I6;
+ input MAIN_SG_I;
+ input MARG_ISV_I1;
+ input MARG_ISV_I2;
+ input MARG_ISV_I3;
+ input MARG_ISV_I4;
+ input MARG_ISV_I5;
+ input MARG_IS_I1;
+ input MARG_IS_I2;
+ input MARG_IS_I3;
+ input MARG_IS_I4;
+ input MARG_SV_I1;
+ input MARG_SV_I2;
+ input MARG_SV_I3;
+ input MARG_SV_I4;
+ input MARG_SV_I5;
+ input MARG_S_I1;
+ input MARG_S_I2;
+ input MARG_S_I3;
+ input MARG_S_I4;
+ input M_EYE_I;
+ input OVS_E_I;
+ input PLL_RN_I;
+ input POST_EN_I1;
+ input POST_EN_I2;
+ input POST_EN_I3;
+ input POST_EN_I4;
+ input POST_EN_I5;
+ input POST_ISV_I1;
+ input POST_ISV_I2;
+ input POST_ISV_I3;
+ input POST_ISV_I4;
+ input POST_IS_I1;
+ input POST_IS_I2;
+ input POST_IS_I3;
+ input POST_IS_I4;
+ input POST_SG_I;
+ input PRE_EN_I;
+ input PRE_IS_I1;
+ input PRE_IS_I2;
+ input PRE_IS_I3;
+ input PRE_IS_I4;
+ input PRE_SG_I;
+ input RST_N_I;
+ input RX_SEL_I1;
+ input RX_SEL_I2;
+ input RX_SEL_I3;
+ input RX_SEL_I4;
+ input RX_SEL_I5;
+ input RX_SEL_I6;
+ input TST_I1;
+ input TST_I2;
+ input TST_I3;
+ input TST_I4;
+ input TST_I5;
+ input TST_I6;
+ input TST_I7;
+ input TST_I8;
+ output TST_O1;
+ output TST_O2;
+ output TST_O3;
+ output TST_O4;
+ output TST_O5;
+ output TST_O6;
+ output TST_O7;
+ output TST_O8;
+ input TX_SEL_I1;
+ input TX_SEL_I2;
+ input TX_SEL_I3;
+ input TX_SEL_I4;
+ input TX_SEL_I5;
+ input TX_SEL_I6;
+ parameter location = "";
+ parameter main_clk_to_fabric_div_en = 1'b0;
+ parameter main_clk_to_fabric_div_mode = 1'b0;
+ parameter main_clk_to_fabric_sel = 1'b0;
+ parameter main_test = 8'b00000000;
+ parameter main_use_only_usr_clock = 1'b0;
+ parameter main_use_pcs_clk_2 = 1'b0;
+ parameter pcs_ovs_mode = 1'b0;
+ parameter pcs_pll_lock_count = 3'b000;
+ parameter pcs_word_len = 2'b00;
+ parameter pll_pma_cpump_n = 3'b000;
+ parameter pll_pma_divf = 2'b00;
+ parameter pll_pma_divf_en_n = 1'b0;
+ parameter pll_pma_divm = 2'b00;
+ parameter pll_pma_divm_en_n = 1'b0;
+ parameter pll_pma_divn = 1'b0;
+ parameter pll_pma_divn_en_n = 1'b0;
+ parameter pll_pma_int_data_len = 1'b0;
+ parameter pll_pma_lvds_mux = 1'b0;
+ parameter pll_pma_mux_ckref = 1'b0;
+ parameter rx_pma_half_step = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_RFB_L(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+ output COR;
+ output ERR;
+ input I1;
+ input I10;
+ input I11;
+ input I12;
+ input I13;
+ input I14;
+ input I15;
+ input I16;
+ input I2;
+ input I3;
+ input I4;
+ input I5;
+ input I6;
+ input I7;
+ input I8;
+ input I9;
+ output O1;
+ output O10;
+ output O11;
+ output O12;
+ output O13;
+ output O14;
+ output O15;
+ output O16;
+ output O2;
+ output O3;
+ output O4;
+ output O5;
+ output O6;
+ output O7;
+ output O8;
+ output O9;
+ input RA1;
+ input RA2;
+ input RA3;
+ input RA4;
+ input RA5;
+ input RA6;
+ input RCK;
+ input RE;
+ input WA1;
+ input WA2;
+ input WA3;
+ input WA4;
+ input WA5;
+ input WA6;
+ input WCK;
+ input WE;
+ parameter mem_ctxt = "";
+ parameter mode = 0;
+ parameter rck_edge = 1'b0;
+ parameter wck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_CONTROL_L(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19
+, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+ output C1RED;
+ input C1RNE;
+ input C1RS;
+ input C1RW1;
+ input C1RW2;
+ input C1RW3;
+ input C1TS;
+ input C1TW;
+ output C2RED;
+ input C2RNE;
+ input C2RS;
+ input C2RW1;
+ input C2RW2;
+ input C2RW3;
+ input C2TS;
+ input C2TW;
+ input CAD1;
+ input CAD2;
+ input CAD3;
+ input CAD4;
+ input CAD5;
+ input CAD6;
+ output CAL;
+ input CAN1;
+ input CAN2;
+ input CAN3;
+ input CAN4;
+ input CAP1;
+ input CAP2;
+ input CAP3;
+ input CAP4;
+ input CAT1;
+ input CAT2;
+ input CAT3;
+ input CAT4;
+ input CCK;
+ output CKO1;
+ output CKO2;
+ input CTCK;
+ input DC;
+ input DCK;
+ input DIG;
+ input DIS;
+ input DOG;
+ input DOS;
+ input DPAG;
+ input DPAS;
+ input DQSG;
+ input DQSS;
+ input DRA1;
+ input DRA2;
+ input DRA3;
+ input DRA4;
+ input DRA5;
+ input DRA6;
+ input DRI1;
+ input DRI2;
+ input DRI3;
+ input DRI4;
+ input DRI5;
+ input DRI6;
+ input DRL;
+ output DRO1;
+ output DRO2;
+ output DRO3;
+ output DRO4;
+ output DRO5;
+ output DRO6;
+ input DS1;
+ input DS2;
+ input FA1;
+ input FA2;
+ input FA3;
+ input FA4;
+ input FA5;
+ input FA6;
+ output FLD;
+ output FLG;
+ input FZ;
+ inout [41:0] LINK1;
+ inout [41:0] LINK10;
+ inout [41:0] LINK11;
+ inout [41:0] LINK12;
+ inout [41:0] LINK13;
+ inout [41:0] LINK14;
+ inout [41:0] LINK15;
+ inout [41:0] LINK16;
+ inout [41:0] LINK17;
+ inout [41:0] LINK18;
+ inout [41:0] LINK19;
+ inout [41:0] LINK2;
+ inout [41:0] LINK20;
+ inout [41:0] LINK21;
+ inout [41:0] LINK22;
+ inout [41:0] LINK23;
+ inout [41:0] LINK24;
+ inout [41:0] LINK25;
+ inout [41:0] LINK26;
+ inout [41:0] LINK27;
+ inout [41:0] LINK28;
+ inout [41:0] LINK29;
+ inout [41:0] LINK3;
+ inout [41:0] LINK30;
+ inout [41:0] LINK31;
+ inout [41:0] LINK32;
+ inout [41:0] LINK33;
+ inout [41:0] LINK34;
+ inout [41:0] LINK4;
+ inout [41:0] LINK5;
+ inout [41:0] LINK6;
+ inout [41:0] LINK7;
+ inout [41:0] LINK8;
+ inout [41:0] LINK9;
+ input RRCK1;
+ input RRCK2;
+ input RTCK1;
+ input RTCK2;
+ input WRCK1;
+ input WRCK2;
+ input WTCK1;
+ input WTCK2;
+ parameter div_rx1 = 4'b0000;
+ parameter div_rx2 = 4'b0000;
+ parameter div_tx1 = 4'b0000;
+ parameter div_tx2 = 4'b0000;
+ parameter inv_di_fclk1 = 1'b0;
+ parameter inv_di_fclk2 = 1'b0;
+ parameter latency1 = 1'b0;
+ parameter latency2 = 1'b0;
+ parameter location = "";
+ parameter mode_cpath = "";
+ parameter mode_epath = "";
+ parameter mode_io_cal = 1'b0;
+ parameter mode_rpath = "";
+ parameter mode_side1 = 0;
+ parameter mode_side2 = 0;
+ parameter mode_tpath = "";
+ parameter sel_clk_out1 = 1'b0;
+ parameter sel_clk_out2 = 1'b0;
+ parameter sel_clkr_rx1 = 1'b0;
+ parameter sel_clkr_rx2 = 1'b0;
+ parameter sel_clkw_rx1 = 2'b00;
+ parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_m.v b/techlibs/nanoxplore/cells_bb_m.v
new file mode 100644
index 000000000..d0497c490
--- /dev/null
+++ b/techlibs/nanoxplore/cells_bb_m.v
@@ -0,0 +1,1527 @@
+(* blackbox *)
+module NX_CKS(CKI, CMD, CKO);
+ input CKI;
+ output CKO;
+ input CMD;
+ parameter ck_edge = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_DSP(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAO1, CAO2, CAO3, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9
+, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12
+, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15
+, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO, CO37, CO49, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11
+, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32
+, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53
+, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18
+, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39
+, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4
+, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, OVF, R, RZ, WE, Z1, Z2, Z3
+, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24
+, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45
+, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53, Z54, Z55, Z56);
+ input A1;
+ input A10;
+ input A11;
+ input A12;
+ input A13;
+ input A14;
+ input A15;
+ input A16;
+ input A17;
+ input A18;
+ input A19;
+ input A2;
+ input A20;
+ input A21;
+ input A22;
+ input A23;
+ input A24;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input A7;
+ input A8;
+ input A9;
+ input B1;
+ input B10;
+ input B11;
+ input B12;
+ input B13;
+ input B14;
+ input B15;
+ input B16;
+ input B17;
+ input B18;
+ input B2;
+ input B3;
+ input B4;
+ input B5;
+ input B6;
+ input B7;
+ input B8;
+ input B9;
+ input C1;
+ input C10;
+ input C11;
+ input C12;
+ input C13;
+ input C14;
+ input C15;
+ input C16;
+ input C17;
+ input C18;
+ input C19;
+ input C2;
+ input C20;
+ input C21;
+ input C22;
+ input C23;
+ input C24;
+ input C25;
+ input C26;
+ input C27;
+ input C28;
+ input C29;
+ input C3;
+ input C30;
+ input C31;
+ input C32;
+ input C33;
+ input C34;
+ input C35;
+ input C36;
+ input C4;
+ input C5;
+ input C6;
+ input C7;
+ input C8;
+ input C9;
+ input CAI1;
+ input CAI10;
+ input CAI11;
+ input CAI12;
+ input CAI13;
+ input CAI14;
+ input CAI15;
+ input CAI16;
+ input CAI17;
+ input CAI18;
+ input CAI2;
+ input CAI3;
+ input CAI4;
+ input CAI5;
+ input CAI6;
+ input CAI7;
+ input CAI8;
+ input CAI9;
+ output CAO1;
+ output CAO10;
+ output CAO11;
+ output CAO12;
+ output CAO13;
+ output CAO14;
+ output CAO15;
+ output CAO16;
+ output CAO17;
+ output CAO18;
+ output CAO2;
+ output CAO3;
+ output CAO4;
+ output CAO5;
+ output CAO6;
+ output CAO7;
+ output CAO8;
+ output CAO9;
+ input CBI1;
+ input CBI10;
+ input CBI11;
+ input CBI12;
+ input CBI13;
+ input CBI14;
+ input CBI15;
+ input CBI16;
+ input CBI17;
+ input CBI18;
+ input CBI2;
+ input CBI3;
+ input CBI4;
+ input CBI5;
+ input CBI6;
+ input CBI7;
+ input CBI8;
+ input CBI9;
+ output CBO1;
+ output CBO10;
+ output CBO11;
+ output CBO12;
+ output CBO13;
+ output CBO14;
+ output CBO15;
+ output CBO16;
+ output CBO17;
+ output CBO18;
+ output CBO2;
+ output CBO3;
+ output CBO4;
+ output CBO5;
+ output CBO6;
+ output CBO7;
+ output CBO8;
+ output CBO9;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO;
+ output CO37;
+ output CO49;
+ input CZI1;
+ input CZI10;
+ input CZI11;
+ input CZI12;
+ input CZI13;
+ input CZI14;
+ input CZI15;
+ input CZI16;
+ input CZI17;
+ input CZI18;
+ input CZI19;
+ input CZI2;
+ input CZI20;
+ input CZI21;
+ input CZI22;
+ input CZI23;
+ input CZI24;
+ input CZI25;
+ input CZI26;
+ input CZI27;
+ input CZI28;
+ input CZI29;
+ input CZI3;
+ input CZI30;
+ input CZI31;
+ input CZI32;
+ input CZI33;
+ input CZI34;
+ input CZI35;
+ input CZI36;
+ input CZI37;
+ input CZI38;
+ input CZI39;
+ input CZI4;
+ input CZI40;
+ input CZI41;
+ input CZI42;
+ input CZI43;
+ input CZI44;
+ input CZI45;
+ input CZI46;
+ input CZI47;
+ input CZI48;
+ input CZI49;
+ input CZI5;
+ input CZI50;
+ input CZI51;
+ input CZI52;
+ input CZI53;
+ input CZI54;
+ input CZI55;
+ input CZI56;
+ input CZI6;
+ input CZI7;
+ input CZI8;
+ input CZI9;
+ output CZO1;
+ output CZO10;
+ output CZO11;
+ output CZO12;
+ output CZO13;
+ output CZO14;
+ output CZO15;
+ output CZO16;
+ output CZO17;
+ output CZO18;
+ output CZO19;
+ output CZO2;
+ output CZO20;
+ output CZO21;
+ output CZO22;
+ output CZO23;
+ output CZO24;
+ output CZO25;
+ output CZO26;
+ output CZO27;
+ output CZO28;
+ output CZO29;
+ output CZO3;
+ output CZO30;
+ output CZO31;
+ output CZO32;
+ output CZO33;
+ output CZO34;
+ output CZO35;
+ output CZO36;
+ output CZO37;
+ output CZO38;
+ output CZO39;
+ output CZO4;
+ output CZO40;
+ output CZO41;
+ output CZO42;
+ output CZO43;
+ output CZO44;
+ output CZO45;
+ output CZO46;
+ output CZO47;
+ output CZO48;
+ output CZO49;
+ output CZO5;
+ output CZO50;
+ output CZO51;
+ output CZO52;
+ output CZO53;
+ output CZO54;
+ output CZO55;
+ output CZO56;
+ output CZO6;
+ output CZO7;
+ output CZO8;
+ output CZO9;
+ input D1;
+ input D10;
+ input D11;
+ input D12;
+ input D13;
+ input D14;
+ input D15;
+ input D16;
+ input D17;
+ input D18;
+ input D2;
+ input D3;
+ input D4;
+ input D5;
+ input D6;
+ input D7;
+ input D8;
+ input D9;
+ output OVF;
+ input R;
+ input RZ;
+ input WE;
+ output Z1;
+ output Z10;
+ output Z11;
+ output Z12;
+ output Z13;
+ output Z14;
+ output Z15;
+ output Z16;
+ output Z17;
+ output Z18;
+ output Z19;
+ output Z2;
+ output Z20;
+ output Z21;
+ output Z22;
+ output Z23;
+ output Z24;
+ output Z25;
+ output Z26;
+ output Z27;
+ output Z28;
+ output Z29;
+ output Z3;
+ output Z30;
+ output Z31;
+ output Z32;
+ output Z33;
+ output Z34;
+ output Z35;
+ output Z36;
+ output Z37;
+ output Z38;
+ output Z39;
+ output Z4;
+ output Z40;
+ output Z41;
+ output Z42;
+ output Z43;
+ output Z44;
+ output Z45;
+ output Z46;
+ output Z47;
+ output Z48;
+ output Z49;
+ output Z5;
+ output Z50;
+ output Z51;
+ output Z52;
+ output Z53;
+ output Z54;
+ output Z55;
+ output Z56;
+ output Z6;
+ output Z7;
+ output Z8;
+ output Z9;
+ parameter raw_config0 = 20'b00000000000000000000;
+ parameter raw_config1 = 19'b0000000000000000000;
+ parameter raw_config2 = 13'b0000000000000;
+ parameter raw_config3 = 7'b0000000;
+ parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_PLL(REF, FBK, VCO, D1, D2, D3, OSC, RDY);
+ output D1;
+ output D2;
+ output D3;
+ input FBK;
+ output OSC;
+ output RDY;
+ input REF;
+ output VCO;
+ parameter clk_outdiv1 = 0;
+ parameter clk_outdiv2 = 0;
+ parameter clk_outdiv3 = 0;
+ parameter ext_fbk_on = 1'b0;
+ parameter fbk_delay = 0;
+ parameter fbk_delay_on = 1'b0;
+ parameter fbk_div_on = 1'b0;
+ parameter fbk_intdiv = 2;
+ parameter location = "";
+ parameter ref_div_on = 1'b0;
+ parameter vco_range = 0;
+endmodule
+
+(* blackbox *)
+module NX_WFG(SI, ZI, RDY, SO, ZO);
+ input RDY;
+ input SI;
+ output SO;
+ input ZI;
+ output ZO;
+ parameter delay = 0;
+ parameter delay_on = 1'b0;
+ parameter location = "";
+ parameter mode = 1'b0;
+ parameter pattern = 16'b0000000000000000;
+ parameter pattern_end = 1;
+ parameter wfg_edge = 1'b0;
+endmodule
+
+
+(* blackbox *)
+module NX_IOM(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, CCK, DCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1
+, C2RW2, C2RW3, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FZ, DC, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4
+, DRA5, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1, CAP2, CAP3
+, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1, DRO2, DRO3
+, DRO4, DRO5, DRO6, CAL, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EL, P1ER, P1EO, P1RI, P1RL, P1RR
+, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EL, P2ER, P2EO, P2RI, P2RL
+, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P3CI1, P3CL, P3CR, P3CO, P3CTI, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EL, P3ER, P3EO, P3RI
+, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EL, P4ER, P4EO
+, P4RI, P4RL, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P5CI1, P5CI2, P5CI3, P5CI4, P5CI5, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3
+, P5EI4, P5EI5, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P6CI1, P6CL, P6CR, P6CO, P6CTI, P6CTO, P6EI1, P6EI2
+, P6EI3, P6EI4, P6EI5, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1
+, P7EI2, P7EI3, P7EI4, P7EI5, P7EL, P7ER, P7EO, P7RI, P7RL, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO
+, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P9CI1, P9CL, P9CR, P9CO, P9CTI
+, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P10CI1, P10CL, P10CR, P10CO
+, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EL, P10ER, P10EO, P10RI, P10RL, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P11CI1, P11CL, P11CR
+, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P12CI1, P12CL
+, P12CR, P12CO, P12CTI, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P13CI1
+, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EL, P13ER, P13EO, P13RI, P13RL, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5
+, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4
+, P14RO5, P15CI1, P15CL, P15CR, P15CO, P15CTI, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3
+, P15RO4, P15RO5, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EL, P16ER, P16EO, P16RI, P16RL, P16RR, P16RO1, P16RO2
+, P16RO3, P16RO4, P16RO5, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1
+, P17RO2, P17RO3, P17RO4, P17RO5, P18CI1, P18CL, P18CR, P18CO, P18CTI, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR
+, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EL, P19ER, P19EO, P19RI, P19RL
+, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EL, P20ER, P20EO, P20RI
+, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P21CI1, P21CL, P21CR, P21CO, P21CTI, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EL, P21ER, P21EO
+, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EL, P22ER
+, P22EO, P22RI, P22RL, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EL
+, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P24CI1, P24CL, P24CR, P24CO, P24CTI, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5
+, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P25CI1, P25CI2, P25CI3, P25CI4, P25CI5, P25CL, P25CR, P25CO, P25CTI, P25CTO
+, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EL, P25ER, P25EO, P25RI, P25RL, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P26CI1, P26CL, P26CR, P26CO, P26CTI
+, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P27CI1, P27CL, P27CR, P27CO
+, P27CTI, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P28CI1, P28CL, P28CR
+, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EL, P28ER, P28EO, P28RI, P28RL, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P29CI1, P29CL
+, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P30CI1
+, P30CL, P30CR, P30CO, P30CTI, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5
+);
+ output C1RED;
+ input C1RNE;
+ input C1RS;
+ input C1RW1;
+ input C1RW2;
+ input C1RW3;
+ input C1TS;
+ input C1TW;
+ output C2RED;
+ input C2RNE;
+ input C2RS;
+ input C2RW1;
+ input C2RW2;
+ input C2RW3;
+ input C2TS;
+ input C2TW;
+ input CAD1;
+ input CAD2;
+ input CAD3;
+ input CAD4;
+ input CAD5;
+ input CAD6;
+ output CAL;
+ input CAN1;
+ input CAN2;
+ input CAN3;
+ input CAN4;
+ input CAP1;
+ input CAP2;
+ input CAP3;
+ input CAP4;
+ input CAT1;
+ input CAT2;
+ input CAT3;
+ input CAT4;
+ input CCK;
+ output CKO1;
+ output CKO2;
+ input CTCK;
+ input DC;
+ input DCK;
+ input DIG;
+ input DIS;
+ input DOG;
+ input DOS;
+ input DPAG;
+ input DPAS;
+ input DQSG;
+ input DQSS;
+ input DRA1;
+ input DRA2;
+ input DRA3;
+ input DRA4;
+ input DRA5;
+ input DRI1;
+ input DRI2;
+ input DRI3;
+ input DRI4;
+ input DRI5;
+ input DRI6;
+ input DRL;
+ output DRO1;
+ output DRO2;
+ output DRO3;
+ output DRO4;
+ output DRO5;
+ output DRO6;
+ input DS1;
+ input DS2;
+ input FA1;
+ input FA2;
+ input FA3;
+ input FA4;
+ input FA5;
+ output FLD;
+ output FLG;
+ input FZ;
+ input P10CI1;
+ input P10CL;
+ output P10CO;
+ input P10CR;
+ input P10CTI;
+ output P10CTO;
+ input P10EI1;
+ input P10EI2;
+ input P10EI3;
+ input P10EI4;
+ input P10EI5;
+ input P10EL;
+ output P10EO;
+ input P10ER;
+ input P10RI;
+ input P10RL;
+ output P10RO1;
+ output P10RO2;
+ output P10RO3;
+ output P10RO4;
+ output P10RO5;
+ input P10RR;
+ input P11CI1;
+ input P11CL;
+ output P11CO;
+ input P11CR;
+ input P11CTI;
+ output P11CTO;
+ input P11EI1;
+ input P11EI2;
+ input P11EI3;
+ input P11EI4;
+ input P11EI5;
+ input P11EL;
+ output P11EO;
+ input P11ER;
+ input P11RI;
+ input P11RL;
+ output P11RO1;
+ output P11RO2;
+ output P11RO3;
+ output P11RO4;
+ output P11RO5;
+ input P11RR;
+ input P12CI1;
+ input P12CL;
+ output P12CO;
+ input P12CR;
+ input P12CTI;
+ output P12CTO;
+ input P12EI1;
+ input P12EI2;
+ input P12EI3;
+ input P12EI4;
+ input P12EI5;
+ input P12EL;
+ output P12EO;
+ input P12ER;
+ input P12RI;
+ input P12RL;
+ output P12RO1;
+ output P12RO2;
+ output P12RO3;
+ output P12RO4;
+ output P12RO5;
+ input P12RR;
+ input P13CI1;
+ input P13CL;
+ output P13CO;
+ input P13CR;
+ input P13CTI;
+ output P13CTO;
+ input P13EI1;
+ input P13EI2;
+ input P13EI3;
+ input P13EI4;
+ input P13EI5;
+ input P13EL;
+ output P13EO;
+ input P13ER;
+ input P13RI;
+ input P13RL;
+ output P13RO1;
+ output P13RO2;
+ output P13RO3;
+ output P13RO4;
+ output P13RO5;
+ input P13RR;
+ input P14CI1;
+ input P14CL;
+ output P14CO;
+ input P14CR;
+ input P14CTI;
+ output P14CTO;
+ input P14EI1;
+ input P14EI2;
+ input P14EI3;
+ input P14EI4;
+ input P14EI5;
+ input P14EL;
+ output P14EO;
+ input P14ER;
+ input P14RI;
+ input P14RL;
+ output P14RO1;
+ output P14RO2;
+ output P14RO3;
+ output P14RO4;
+ output P14RO5;
+ input P14RR;
+ input P15CI1;
+ input P15CL;
+ output P15CO;
+ input P15CR;
+ input P15CTI;
+ output P15CTO;
+ input P15EI1;
+ input P15EI2;
+ input P15EI3;
+ input P15EI4;
+ input P15EI5;
+ input P15EL;
+ output P15EO;
+ input P15ER;
+ input P15RI;
+ input P15RL;
+ output P15RO1;
+ output P15RO2;
+ output P15RO3;
+ output P15RO4;
+ output P15RO5;
+ input P15RR;
+ input P16CI1;
+ input P16CL;
+ output P16CO;
+ input P16CR;
+ input P16CTI;
+ output P16CTO;
+ input P16EI1;
+ input P16EI2;
+ input P16EI3;
+ input P16EI4;
+ input P16EI5;
+ input P16EL;
+ output P16EO;
+ input P16ER;
+ input P16RI;
+ input P16RL;
+ output P16RO1;
+ output P16RO2;
+ output P16RO3;
+ output P16RO4;
+ output P16RO5;
+ input P16RR;
+ input P17CI1;
+ input P17CL;
+ output P17CO;
+ input P17CR;
+ input P17CTI;
+ output P17CTO;
+ input P17EI1;
+ input P17EI2;
+ input P17EI3;
+ input P17EI4;
+ input P17EI5;
+ input P17EL;
+ output P17EO;
+ input P17ER;
+ input P17RI;
+ input P17RL;
+ output P17RO1;
+ output P17RO2;
+ output P17RO3;
+ output P17RO4;
+ output P17RO5;
+ input P17RR;
+ input P18CI1;
+ input P18CL;
+ output P18CO;
+ input P18CR;
+ input P18CTI;
+ output P18CTO;
+ input P18EI1;
+ input P18EI2;
+ input P18EI3;
+ input P18EI4;
+ input P18EI5;
+ input P18EL;
+ output P18EO;
+ input P18ER;
+ input P18RI;
+ input P18RL;
+ output P18RO1;
+ output P18RO2;
+ output P18RO3;
+ output P18RO4;
+ output P18RO5;
+ input P18RR;
+ input P19CI1;
+ input P19CL;
+ output P19CO;
+ input P19CR;
+ input P19CTI;
+ output P19CTO;
+ input P19EI1;
+ input P19EI2;
+ input P19EI3;
+ input P19EI4;
+ input P19EI5;
+ input P19EL;
+ output P19EO;
+ input P19ER;
+ input P19RI;
+ input P19RL;
+ output P19RO1;
+ output P19RO2;
+ output P19RO3;
+ output P19RO4;
+ output P19RO5;
+ input P19RR;
+ input P1CI1;
+ input P1CL;
+ output P1CO;
+ input P1CR;
+ input P1CTI;
+ output P1CTO;
+ input P1EI1;
+ input P1EI2;
+ input P1EI3;
+ input P1EI4;
+ input P1EI5;
+ input P1EL;
+ output P1EO;
+ input P1ER;
+ input P1RI;
+ input P1RL;
+ output P1RO1;
+ output P1RO2;
+ output P1RO3;
+ output P1RO4;
+ output P1RO5;
+ input P1RR;
+ input P20CI1;
+ input P20CL;
+ output P20CO;
+ input P20CR;
+ input P20CTI;
+ output P20CTO;
+ input P20EI1;
+ input P20EI2;
+ input P20EI3;
+ input P20EI4;
+ input P20EI5;
+ input P20EL;
+ output P20EO;
+ input P20ER;
+ input P20RI;
+ input P20RL;
+ output P20RO1;
+ output P20RO2;
+ output P20RO3;
+ output P20RO4;
+ output P20RO5;
+ input P20RR;
+ input P21CI1;
+ input P21CL;
+ output P21CO;
+ input P21CR;
+ input P21CTI;
+ output P21CTO;
+ input P21EI1;
+ input P21EI2;
+ input P21EI3;
+ input P21EI4;
+ input P21EI5;
+ input P21EL;
+ output P21EO;
+ input P21ER;
+ input P21RI;
+ input P21RL;
+ output P21RO1;
+ output P21RO2;
+ output P21RO3;
+ output P21RO4;
+ output P21RO5;
+ input P21RR;
+ input P22CI1;
+ input P22CL;
+ output P22CO;
+ input P22CR;
+ input P22CTI;
+ output P22CTO;
+ input P22EI1;
+ input P22EI2;
+ input P22EI3;
+ input P22EI4;
+ input P22EI5;
+ input P22EL;
+ output P22EO;
+ input P22ER;
+ input P22RI;
+ input P22RL;
+ output P22RO1;
+ output P22RO2;
+ output P22RO3;
+ output P22RO4;
+ output P22RO5;
+ input P22RR;
+ input P23CI1;
+ input P23CL;
+ output P23CO;
+ input P23CR;
+ input P23CTI;
+ output P23CTO;
+ input P23EI1;
+ input P23EI2;
+ input P23EI3;
+ input P23EI4;
+ input P23EI5;
+ input P23EL;
+ output P23EO;
+ input P23ER;
+ input P23RI;
+ input P23RL;
+ output P23RO1;
+ output P23RO2;
+ output P23RO3;
+ output P23RO4;
+ output P23RO5;
+ input P23RR;
+ input P24CI1;
+ input P24CL;
+ output P24CO;
+ input P24CR;
+ input P24CTI;
+ output P24CTO;
+ input P24EI1;
+ input P24EI2;
+ input P24EI3;
+ input P24EI4;
+ input P24EI5;
+ input P24EL;
+ output P24EO;
+ input P24ER;
+ input P24RI;
+ input P24RL;
+ output P24RO1;
+ output P24RO2;
+ output P24RO3;
+ output P24RO4;
+ output P24RO5;
+ input P24RR;
+ input P25CI1;
+ input P25CI2;
+ input P25CI3;
+ input P25CI4;
+ input P25CI5;
+ input P25CL;
+ output P25CO;
+ input P25CR;
+ input P25CTI;
+ output P25CTO;
+ input P25EI1;
+ input P25EI2;
+ input P25EI3;
+ input P25EI4;
+ input P25EI5;
+ input P25EL;
+ output P25EO;
+ input P25ER;
+ input P25RI;
+ input P25RL;
+ output P25RO1;
+ output P25RO2;
+ output P25RO3;
+ output P25RO4;
+ output P25RO5;
+ input P25RR;
+ input P26CI1;
+ input P26CL;
+ output P26CO;
+ input P26CR;
+ input P26CTI;
+ output P26CTO;
+ input P26EI1;
+ input P26EI2;
+ input P26EI3;
+ input P26EI4;
+ input P26EI5;
+ input P26EL;
+ output P26EO;
+ input P26ER;
+ input P26RI;
+ input P26RL;
+ output P26RO1;
+ output P26RO2;
+ output P26RO3;
+ output P26RO4;
+ output P26RO5;
+ input P26RR;
+ input P27CI1;
+ input P27CL;
+ output P27CO;
+ input P27CR;
+ input P27CTI;
+ output P27CTO;
+ input P27EI1;
+ input P27EI2;
+ input P27EI3;
+ input P27EI4;
+ input P27EI5;
+ input P27EL;
+ output P27EO;
+ input P27ER;
+ input P27RI;
+ input P27RL;
+ output P27RO1;
+ output P27RO2;
+ output P27RO3;
+ output P27RO4;
+ output P27RO5;
+ input P27RR;
+ input P28CI1;
+ input P28CL;
+ output P28CO;
+ input P28CR;
+ input P28CTI;
+ output P28CTO;
+ input P28EI1;
+ input P28EI2;
+ input P28EI3;
+ input P28EI4;
+ input P28EI5;
+ input P28EL;
+ output P28EO;
+ input P28ER;
+ input P28RI;
+ input P28RL;
+ output P28RO1;
+ output P28RO2;
+ output P28RO3;
+ output P28RO4;
+ output P28RO5;
+ input P28RR;
+ input P29CI1;
+ input P29CL;
+ output P29CO;
+ input P29CR;
+ input P29CTI;
+ output P29CTO;
+ input P29EI1;
+ input P29EI2;
+ input P29EI3;
+ input P29EI4;
+ input P29EI5;
+ input P29EL;
+ output P29EO;
+ input P29ER;
+ input P29RI;
+ input P29RL;
+ output P29RO1;
+ output P29RO2;
+ output P29RO3;
+ output P29RO4;
+ output P29RO5;
+ input P29RR;
+ input P2CI1;
+ input P2CL;
+ output P2CO;
+ input P2CR;
+ input P2CTI;
+ output P2CTO;
+ input P2EI1;
+ input P2EI2;
+ input P2EI3;
+ input P2EI4;
+ input P2EI5;
+ input P2EL;
+ output P2EO;
+ input P2ER;
+ input P2RI;
+ input P2RL;
+ output P2RO1;
+ output P2RO2;
+ output P2RO3;
+ output P2RO4;
+ output P2RO5;
+ input P2RR;
+ input P30CI1;
+ input P30CL;
+ output P30CO;
+ input P30CR;
+ input P30CTI;
+ output P30CTO;
+ input P30EI1;
+ input P30EI2;
+ input P30EI3;
+ input P30EI4;
+ input P30EI5;
+ input P30EL;
+ output P30EO;
+ input P30ER;
+ input P30RI;
+ input P30RL;
+ output P30RO1;
+ output P30RO2;
+ output P30RO3;
+ output P30RO4;
+ output P30RO5;
+ input P30RR;
+ input P3CI1;
+ input P3CL;
+ output P3CO;
+ input P3CR;
+ input P3CTI;
+ output P3CTO;
+ input P3EI1;
+ input P3EI2;
+ input P3EI3;
+ input P3EI4;
+ input P3EI5;
+ input P3EL;
+ output P3EO;
+ input P3ER;
+ input P3RI;
+ input P3RL;
+ output P3RO1;
+ output P3RO2;
+ output P3RO3;
+ output P3RO4;
+ output P3RO5;
+ input P3RR;
+ input P4CI1;
+ input P4CL;
+ output P4CO;
+ input P4CR;
+ input P4CTI;
+ output P4CTO;
+ input P4EI1;
+ input P4EI2;
+ input P4EI3;
+ input P4EI4;
+ input P4EI5;
+ input P4EL;
+ output P4EO;
+ input P4ER;
+ input P4RI;
+ input P4RL;
+ output P4RO1;
+ output P4RO2;
+ output P4RO3;
+ output P4RO4;
+ output P4RO5;
+ input P4RR;
+ input P5CI1;
+ input P5CI2;
+ input P5CI3;
+ input P5CI4;
+ input P5CI5;
+ input P5CL;
+ output P5CO;
+ input P5CR;
+ input P5CTI;
+ output P5CTO;
+ input P5EI1;
+ input P5EI2;
+ input P5EI3;
+ input P5EI4;
+ input P5EI5;
+ input P5EL;
+ output P5EO;
+ input P5ER;
+ input P5RI;
+ input P5RL;
+ output P5RO1;
+ output P5RO2;
+ output P5RO3;
+ output P5RO4;
+ output P5RO5;
+ input P5RR;
+ input P6CI1;
+ input P6CL;
+ output P6CO;
+ input P6CR;
+ input P6CTI;
+ output P6CTO;
+ input P6EI1;
+ input P6EI2;
+ input P6EI3;
+ input P6EI4;
+ input P6EI5;
+ input P6EL;
+ output P6EO;
+ input P6ER;
+ input P6RI;
+ input P6RL;
+ output P6RO1;
+ output P6RO2;
+ output P6RO3;
+ output P6RO4;
+ output P6RO5;
+ input P6RR;
+ input P7CI1;
+ input P7CL;
+ output P7CO;
+ input P7CR;
+ input P7CTI;
+ output P7CTO;
+ input P7EI1;
+ input P7EI2;
+ input P7EI3;
+ input P7EI4;
+ input P7EI5;
+ input P7EL;
+ output P7EO;
+ input P7ER;
+ input P7RI;
+ input P7RL;
+ output P7RO1;
+ output P7RO2;
+ output P7RO3;
+ output P7RO4;
+ output P7RO5;
+ input P7RR;
+ input P8CI1;
+ input P8CL;
+ output P8CO;
+ input P8CR;
+ input P8CTI;
+ output P8CTO;
+ input P8EI1;
+ input P8EI2;
+ input P8EI3;
+ input P8EI4;
+ input P8EI5;
+ input P8EL;
+ output P8EO;
+ input P8ER;
+ input P8RI;
+ input P8RL;
+ output P8RO1;
+ output P8RO2;
+ output P8RO3;
+ output P8RO4;
+ output P8RO5;
+ input P8RR;
+ input P9CI1;
+ input P9CL;
+ output P9CO;
+ input P9CR;
+ input P9CTI;
+ output P9CTO;
+ input P9EI1;
+ input P9EI2;
+ input P9EI3;
+ input P9EI4;
+ input P9EI5;
+ input P9EL;
+ output P9EO;
+ input P9ER;
+ input P9RI;
+ input P9RL;
+ output P9RO1;
+ output P9RO2;
+ output P9RO3;
+ output P9RO4;
+ output P9RO5;
+ input P9RR;
+ input RRCK1;
+ input RRCK2;
+ input RTCK1;
+ input RTCK2;
+ input SPI1;
+ input SPI2;
+ input SPI3;
+ input WRCK1;
+ input WRCK2;
+ input WTCK1;
+ input WTCK2;
+ parameter div_rx1 = 4'b0000;
+ parameter div_rx2 = 4'b0000;
+ parameter div_tx1 = 4'b0000;
+ parameter div_tx2 = 4'b0000;
+ parameter mode_io_cal = 1'b0;
+ parameter mode_side1 = 0;
+ parameter mode_side2 = 0;
+ parameter pads_dict = "";
+ parameter pads_path = "";
+ parameter sel_clk_out1 = 1'b0;
+ parameter sel_clk_out2 = 1'b0;
+ parameter sel_clkr_rx1 = 1'b0;
+ parameter sel_clkr_rx2 = 1'b0;
+ parameter sel_clkw_rx1 = 2'b00;
+ parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_RFB_M(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+ output COR;
+ output ERR;
+ input I1;
+ input I10;
+ input I11;
+ input I12;
+ input I13;
+ input I14;
+ input I15;
+ input I16;
+ input I2;
+ input I3;
+ input I4;
+ input I5;
+ input I6;
+ input I7;
+ input I8;
+ input I9;
+ output O1;
+ output O10;
+ output O11;
+ output O12;
+ output O13;
+ output O14;
+ output O15;
+ output O16;
+ output O2;
+ output O3;
+ output O4;
+ output O5;
+ output O6;
+ output O7;
+ output O8;
+ output O9;
+ input RA1;
+ input RA2;
+ input RA3;
+ input RA4;
+ input RA5;
+ input RA6;
+ input RCK;
+ input RE;
+ input WA1;
+ input WA2;
+ input WA3;
+ input WA4;
+ input WA5;
+ input WA6;
+ input WCK;
+ input WE;
+ parameter mem_ctxt = "";
+ parameter rck_edge = 1'b0;
+ parameter wck_edge = 1'b0;
+endmodule
+
+
+(* blackbox *)
+module NX_IOM_CONTROL_M(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1
+, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16
+, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+ output C1RED;
+ input C1RNE;
+ input C1RS;
+ input C1RW1;
+ input C1RW2;
+ input C1RW3;
+ input C1TS;
+ input C1TW;
+ output C2RED;
+ input C2RNE;
+ input C2RS;
+ input C2RW1;
+ input C2RW2;
+ input C2RW3;
+ input C2TS;
+ input C2TW;
+ input CAD1;
+ input CAD2;
+ input CAD3;
+ input CAD4;
+ input CAD5;
+ input CAD6;
+ output CAL;
+ input CAN1;
+ input CAN2;
+ input CAN3;
+ input CAN4;
+ input CAP1;
+ input CAP2;
+ input CAP3;
+ input CAP4;
+ input CAT1;
+ input CAT2;
+ input CAT3;
+ input CAT4;
+ input CCK;
+ output CKO1;
+ output CKO2;
+ input CTCK;
+ input DC;
+ input DCK;
+ input DIG;
+ input DIS;
+ input DOG;
+ input DOS;
+ input DPAG;
+ input DPAS;
+ input DQSG;
+ input DQSS;
+ input DRA1;
+ input DRA2;
+ input DRA3;
+ input DRA4;
+ input DRA5;
+ input DRA6;
+ input DRI1;
+ input DRI2;
+ input DRI3;
+ input DRI4;
+ input DRI5;
+ input DRI6;
+ input DRL;
+ output DRO1;
+ output DRO2;
+ output DRO3;
+ output DRO4;
+ output DRO5;
+ output DRO6;
+ input DS1;
+ input DS2;
+ input FA1;
+ input FA2;
+ input FA3;
+ input FA4;
+ input FA5;
+ input FA6;
+ output FLD;
+ output FLG;
+ input FZ;
+ inout [41:0] LINK1;
+ inout [41:0] LINK10;
+ inout [41:0] LINK11;
+ inout [41:0] LINK12;
+ inout [41:0] LINK13;
+ inout [41:0] LINK14;
+ inout [41:0] LINK15;
+ inout [41:0] LINK16;
+ inout [41:0] LINK17;
+ inout [41:0] LINK18;
+ inout [41:0] LINK19;
+ inout [41:0] LINK2;
+ inout [41:0] LINK20;
+ inout [41:0] LINK21;
+ inout [41:0] LINK22;
+ inout [41:0] LINK23;
+ inout [41:0] LINK24;
+ inout [41:0] LINK25;
+ inout [41:0] LINK26;
+ inout [41:0] LINK27;
+ inout [41:0] LINK28;
+ inout [41:0] LINK29;
+ inout [41:0] LINK3;
+ inout [41:0] LINK30;
+ inout [41:0] LINK31;
+ inout [41:0] LINK32;
+ inout [41:0] LINK33;
+ inout [41:0] LINK34;
+ inout [41:0] LINK4;
+ inout [41:0] LINK5;
+ inout [41:0] LINK6;
+ inout [41:0] LINK7;
+ inout [41:0] LINK8;
+ inout [41:0] LINK9;
+ input RRCK1;
+ input RRCK2;
+ input RTCK1;
+ input RTCK2;
+ input SPI1;
+ input SPI2;
+ input SPI3;
+ input WRCK1;
+ input WRCK2;
+ input WTCK1;
+ input WTCK2;
+ parameter div_rx1 = 4'b0000;
+ parameter div_rx2 = 4'b0000;
+ parameter div_tx1 = 4'b0000;
+ parameter div_tx2 = 4'b0000;
+ parameter inv_di_fclk1 = 1'b0;
+ parameter inv_di_fclk2 = 1'b0;
+ parameter latency1 = 1'b0;
+ parameter latency2 = 1'b0;
+ parameter location = "";
+ parameter mode_cpath = "";
+ parameter mode_epath = "";
+ parameter mode_io_cal = 1'b0;
+ parameter mode_rpath = "";
+ parameter mode_side1 = 0;
+ parameter mode_side2 = 0;
+ parameter mode_tpath = "";
+ parameter sel_clk_out1 = 1'b0;
+ parameter sel_clk_out2 = 1'b0;
+ parameter sel_clkr_rx1 = 1'b0;
+ parameter sel_clkr_rx2 = 1'b0;
+ parameter sel_clkw_rx1 = 2'b00;
+ parameter sel_clkw_rx2 = 2'b00;
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
+, RO2, RO3, RO4, RO5, CTO, LINK);
+ input CI1;
+ input CI2;
+ input CI3;
+ input CI4;
+ input CI5;
+ input CL;
+ output CO;
+ input CR;
+ input CTI;
+ output CTO;
+ input EI1;
+ input EI2;
+ input EI3;
+ input EI4;
+ input EI5;
+ input EL;
+ output EO;
+ input ER;
+ inout [41:0] LINK;
+ input RI;
+ input RL;
+ output RO1;
+ output RO2;
+ output RO3;
+ output RO4;
+ output RO5;
+ input RR;
+ parameter chained = 1'b0;
+ parameter cpath_edge = 1'b0;
+ parameter cpath_init = 1'b0;
+ parameter cpath_inv = 1'b0;
+ parameter cpath_load = 1'b0;
+ parameter cpath_mode = 4'b0000;
+ parameter cpath_sync = 1'b0;
+ parameter epath_dynamic = 1'b0;
+ parameter epath_edge = 1'b0;
+ parameter epath_init = 1'b0;
+ parameter epath_load = 1'b0;
+ parameter epath_mode = 4'b0000;
+ parameter epath_sync = 1'b0;
+ parameter location = "";
+ parameter rpath_dynamic = 1'b0;
+ parameter rpath_edge = 1'b0;
+ parameter rpath_init = 1'b0;
+ parameter rpath_load = 1'b0;
+ parameter rpath_mode = 4'b0000;
+ parameter rpath_sync = 1'b0;
+ parameter symbol = "";
+ parameter tpath_mode = 2'b00;
+ parameter variant = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_SERDES_M(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
+ input CTCK;
+ input DCK;
+ output [5:0] DID;
+ input DIG;
+ input [5:0] DRA;
+ input [5:0] DRI;
+ input DRL;
+ output [5:0] DRO;
+ input [1:0] DS;
+ output FLD;
+ output FLG;
+ input FZ;
+ inout [41:0] LINKN;
+ inout [41:0] LINKP;
+ input RRCK;
+ input RRST;
+ input RTCK;
+ input TRST;
+ input WRCK;
+ input WTCK;
+ parameter data_size = 5;
+ parameter location = "";
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_bb_u.v b/techlibs/nanoxplore/cells_bb_u.v
new file mode 100644
index 000000000..bfe04dc25
--- /dev/null
+++ b/techlibs/nanoxplore/cells_bb_u.v
@@ -0,0 +1,2758 @@
+(* blackbox *)
+module NX_CDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, AI1, AI2, AI3, AI4, AI5, AI6, AO1, AO2, AO3, AO4, AO5, AO6, BSRSTI, BDRSTI, BSRSTO
+, BDRSTO, BI1, BI2, BI3, BI4, BI5, BI6, BO1, BO2, BO3, BO4, BO5, BO6, CSRSTI, CDRSTI, CSRSTO, CDRSTO, CI1, CI2, CI3, CI4
+, CI5, CI6, CO1, CO2, CO3, CO4, CO5, CO6, DSRSTI, DDRSTI, DSRSTO, DDRSTO, DI1, DI2, DI3, DI4, DI5, DI6, DO1, DO2, DO3
+, DO4, DO5, DO6);
+ input ADRSTI;
+ output ADRSTO;
+ input AI1;
+ input AI2;
+ input AI3;
+ input AI4;
+ input AI5;
+ input AI6;
+ output AO1;
+ output AO2;
+ output AO3;
+ output AO4;
+ output AO5;
+ output AO6;
+ input ASRSTI;
+ output ASRSTO;
+ input BDRSTI;
+ output BDRSTO;
+ input BI1;
+ input BI2;
+ input BI3;
+ input BI4;
+ input BI5;
+ input BI6;
+ output BO1;
+ output BO2;
+ output BO3;
+ output BO4;
+ output BO5;
+ output BO6;
+ input BSRSTI;
+ output BSRSTO;
+ input CDRSTI;
+ output CDRSTO;
+ input CI1;
+ input CI2;
+ input CI3;
+ input CI4;
+ input CI5;
+ input CI6;
+ input CK1;
+ input CK2;
+ output CO1;
+ output CO2;
+ output CO3;
+ output CO4;
+ output CO5;
+ output CO6;
+ input CSRSTI;
+ output CSRSTO;
+ input DDRSTI;
+ output DDRSTO;
+ input DI1;
+ input DI2;
+ input DI3;
+ input DI4;
+ input DI5;
+ input DI6;
+ output DO1;
+ output DO2;
+ output DO3;
+ output DO4;
+ output DO5;
+ output DO6;
+ input DSRSTI;
+ output DSRSTO;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter cck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter dck_sel = 1'b0;
+ parameter link_BA = 1'b0;
+ parameter link_CB = 1'b0;
+ parameter link_DC = 1'b0;
+ parameter mode = 0;
+ parameter use_adest_arst = 1'b0;
+ parameter use_asrc_arst = 1'b0;
+ parameter use_bdest_arst = 1'b0;
+ parameter use_bsrc_arst = 1'b0;
+ parameter use_cdest_arst = 1'b0;
+ parameter use_csrc_arst = 1'b0;
+ parameter use_ddest_arst = 1'b0;
+ parameter use_dsrc_arst = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_DSP_U(A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21
+, A22, A23, A24, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18
+, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21
+, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, CAI1, CAI2, CAI3, CAI4, CAI5, CAI6
+, CAI7, CAI8, CAI9, CAI10, CAI11, CAI12, CAI13, CAI14, CAI15, CAI16, CAI17, CAI18, CAI19, CAI20, CAI21, CAI22, CAI23, CAI24, CAO1, CAO2, CAO3
+, CAO4, CAO5, CAO6, CAO7, CAO8, CAO9, CAO10, CAO11, CAO12, CAO13, CAO14, CAO15, CAO16, CAO17, CAO18, CAO19, CAO20, CAO21, CAO22, CAO23, CAO24
+, CBI1, CBI2, CBI3, CBI4, CBI5, CBI6, CBI7, CBI8, CBI9, CBI10, CBI11, CBI12, CBI13, CBI14, CBI15, CBI16, CBI17, CBI18, CBO1, CBO2, CBO3
+, CBO4, CBO5, CBO6, CBO7, CBO8, CBO9, CBO10, CBO11, CBO12, CBO13, CBO14, CBO15, CBO16, CBO17, CBO18, CCI, CCO, CI, CK, CO43, CO57
+, RESERVED, CZI1, CZI2, CZI3, CZI4, CZI5, CZI6, CZI7, CZI8, CZI9, CZI10, CZI11, CZI12, CZI13, CZI14, CZI15, CZI16, CZI17, CZI18, CZI19, CZI20
+, CZI21, CZI22, CZI23, CZI24, CZI25, CZI26, CZI27, CZI28, CZI29, CZI30, CZI31, CZI32, CZI33, CZI34, CZI35, CZI36, CZI37, CZI38, CZI39, CZI40, CZI41
+, CZI42, CZI43, CZI44, CZI45, CZI46, CZI47, CZI48, CZI49, CZI50, CZI51, CZI52, CZI53, CZI54, CZI55, CZI56, CZO1, CZO2, CZO3, CZO4, CZO5, CZO6
+, CZO7, CZO8, CZO9, CZO10, CZO11, CZO12, CZO13, CZO14, CZO15, CZO16, CZO17, CZO18, CZO19, CZO20, CZO21, CZO22, CZO23, CZO24, CZO25, CZO26, CZO27
+, CZO28, CZO29, CZO30, CZO31, CZO32, CZO33, CZO34, CZO35, CZO36, CZO37, CZO38, CZO39, CZO40, CZO41, CZO42, CZO43, CZO44, CZO45, CZO46, CZO47, CZO48
+, CZO49, CZO50, CZO51, CZO52, CZO53, CZO54, CZO55, CZO56, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13
+, D14, D15, D16, D17, D18, OVF, R, RZ, WE, WEZ, Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9, Z10, Z11
+, Z12, Z13, Z14, Z15, Z16, Z17, Z18, Z19, Z20, Z21, Z22, Z23, Z24, Z25, Z26, Z27, Z28, Z29, Z30, Z31, Z32
+, Z33, Z34, Z35, Z36, Z37, Z38, Z39, Z40, Z41, Z42, Z43, Z44, Z45, Z46, Z47, Z48, Z49, Z50, Z51, Z52, Z53
+, Z54, Z55, Z56);
+ input A1;
+ input A10;
+ input A11;
+ input A12;
+ input A13;
+ input A14;
+ input A15;
+ input A16;
+ input A17;
+ input A18;
+ input A19;
+ input A2;
+ input A20;
+ input A21;
+ input A22;
+ input A23;
+ input A24;
+ input A3;
+ input A4;
+ input A5;
+ input A6;
+ input A7;
+ input A8;
+ input A9;
+ input B1;
+ input B10;
+ input B11;
+ input B12;
+ input B13;
+ input B14;
+ input B15;
+ input B16;
+ input B17;
+ input B18;
+ input B2;
+ input B3;
+ input B4;
+ input B5;
+ input B6;
+ input B7;
+ input B8;
+ input B9;
+ input C1;
+ input C10;
+ input C11;
+ input C12;
+ input C13;
+ input C14;
+ input C15;
+ input C16;
+ input C17;
+ input C18;
+ input C19;
+ input C2;
+ input C20;
+ input C21;
+ input C22;
+ input C23;
+ input C24;
+ input C25;
+ input C26;
+ input C27;
+ input C28;
+ input C29;
+ input C3;
+ input C30;
+ input C31;
+ input C32;
+ input C33;
+ input C34;
+ input C35;
+ input C36;
+ input C4;
+ input C5;
+ input C6;
+ input C7;
+ input C8;
+ input C9;
+ input CAI1;
+ input CAI10;
+ input CAI11;
+ input CAI12;
+ input CAI13;
+ input CAI14;
+ input CAI15;
+ input CAI16;
+ input CAI17;
+ input CAI18;
+ input CAI19;
+ input CAI2;
+ input CAI20;
+ input CAI21;
+ input CAI22;
+ input CAI23;
+ input CAI24;
+ input CAI3;
+ input CAI4;
+ input CAI5;
+ input CAI6;
+ input CAI7;
+ input CAI8;
+ input CAI9;
+ output CAO1;
+ output CAO10;
+ output CAO11;
+ output CAO12;
+ output CAO13;
+ output CAO14;
+ output CAO15;
+ output CAO16;
+ output CAO17;
+ output CAO18;
+ output CAO19;
+ output CAO2;
+ output CAO20;
+ output CAO21;
+ output CAO22;
+ output CAO23;
+ output CAO24;
+ output CAO3;
+ output CAO4;
+ output CAO5;
+ output CAO6;
+ output CAO7;
+ output CAO8;
+ output CAO9;
+ input CBI1;
+ input CBI10;
+ input CBI11;
+ input CBI12;
+ input CBI13;
+ input CBI14;
+ input CBI15;
+ input CBI16;
+ input CBI17;
+ input CBI18;
+ input CBI2;
+ input CBI3;
+ input CBI4;
+ input CBI5;
+ input CBI6;
+ input CBI7;
+ input CBI8;
+ input CBI9;
+ output CBO1;
+ output CBO10;
+ output CBO11;
+ output CBO12;
+ output CBO13;
+ output CBO14;
+ output CBO15;
+ output CBO16;
+ output CBO17;
+ output CBO18;
+ output CBO2;
+ output CBO3;
+ output CBO4;
+ output CBO5;
+ output CBO6;
+ output CBO7;
+ output CBO8;
+ output CBO9;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO43;
+ output CO57;
+ input CZI1;
+ input CZI10;
+ input CZI11;
+ input CZI12;
+ input CZI13;
+ input CZI14;
+ input CZI15;
+ input CZI16;
+ input CZI17;
+ input CZI18;
+ input CZI19;
+ input CZI2;
+ input CZI20;
+ input CZI21;
+ input CZI22;
+ input CZI23;
+ input CZI24;
+ input CZI25;
+ input CZI26;
+ input CZI27;
+ input CZI28;
+ input CZI29;
+ input CZI3;
+ input CZI30;
+ input CZI31;
+ input CZI32;
+ input CZI33;
+ input CZI34;
+ input CZI35;
+ input CZI36;
+ input CZI37;
+ input CZI38;
+ input CZI39;
+ input CZI4;
+ input CZI40;
+ input CZI41;
+ input CZI42;
+ input CZI43;
+ input CZI44;
+ input CZI45;
+ input CZI46;
+ input CZI47;
+ input CZI48;
+ input CZI49;
+ input CZI5;
+ input CZI50;
+ input CZI51;
+ input CZI52;
+ input CZI53;
+ input CZI54;
+ input CZI55;
+ input CZI56;
+ input CZI6;
+ input CZI7;
+ input CZI8;
+ input CZI9;
+ output CZO1;
+ output CZO10;
+ output CZO11;
+ output CZO12;
+ output CZO13;
+ output CZO14;
+ output CZO15;
+ output CZO16;
+ output CZO17;
+ output CZO18;
+ output CZO19;
+ output CZO2;
+ output CZO20;
+ output CZO21;
+ output CZO22;
+ output CZO23;
+ output CZO24;
+ output CZO25;
+ output CZO26;
+ output CZO27;
+ output CZO28;
+ output CZO29;
+ output CZO3;
+ output CZO30;
+ output CZO31;
+ output CZO32;
+ output CZO33;
+ output CZO34;
+ output CZO35;
+ output CZO36;
+ output CZO37;
+ output CZO38;
+ output CZO39;
+ output CZO4;
+ output CZO40;
+ output CZO41;
+ output CZO42;
+ output CZO43;
+ output CZO44;
+ output CZO45;
+ output CZO46;
+ output CZO47;
+ output CZO48;
+ output CZO49;
+ output CZO5;
+ output CZO50;
+ output CZO51;
+ output CZO52;
+ output CZO53;
+ output CZO54;
+ output CZO55;
+ output CZO56;
+ output CZO6;
+ output CZO7;
+ output CZO8;
+ output CZO9;
+ input D1;
+ input D10;
+ input D11;
+ input D12;
+ input D13;
+ input D14;
+ input D15;
+ input D16;
+ input D17;
+ input D18;
+ input D2;
+ input D3;
+ input D4;
+ input D5;
+ input D6;
+ input D7;
+ input D8;
+ input D9;
+ output OVF;
+ input R;
+ output RESERVED;
+ input RZ;
+ input WE;
+ input WEZ;
+ output Z1;
+ output Z10;
+ output Z11;
+ output Z12;
+ output Z13;
+ output Z14;
+ output Z15;
+ output Z16;
+ output Z17;
+ output Z18;
+ output Z19;
+ output Z2;
+ output Z20;
+ output Z21;
+ output Z22;
+ output Z23;
+ output Z24;
+ output Z25;
+ output Z26;
+ output Z27;
+ output Z28;
+ output Z29;
+ output Z3;
+ output Z30;
+ output Z31;
+ output Z32;
+ output Z33;
+ output Z34;
+ output Z35;
+ output Z36;
+ output Z37;
+ output Z38;
+ output Z39;
+ output Z4;
+ output Z40;
+ output Z41;
+ output Z42;
+ output Z43;
+ output Z44;
+ output Z45;
+ output Z46;
+ output Z47;
+ output Z48;
+ output Z49;
+ output Z5;
+ output Z50;
+ output Z51;
+ output Z52;
+ output Z53;
+ output Z54;
+ output Z55;
+ output Z56;
+ output Z6;
+ output Z7;
+ output Z8;
+ output Z9;
+ parameter raw_config0 = 27'b000000000000000000000000000;
+ parameter raw_config1 = 24'b000000000000000000000000;
+ parameter raw_config2 = 14'b00000000000000;
+ parameter raw_config3 = 3'b000;
+ parameter std_mode = "";
+endmodule
+
+(* blackbox *)
+module NX_PLL_U(R, REF, FBK, OSC, VCO, LDFO, REFO, CLK_DIV1, CLK_DIV2, CLK_DIV3, CLK_DIV4, CLK_DIVD1, CLK_DIVD2, CLK_DIVD3, CLK_DIVD4, CLK_DIVD5, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV
+, CAL_LOCKED, EXT_CAL_LOCKED, CAL1, CAL2, CAL3, CAL4, CAL5, EXT_CAL1, EXT_CAL2, EXT_CAL3, EXT_CAL4, EXT_CAL5);
+ input ARST_CAL;
+ output CAL1;
+ output CAL2;
+ output CAL3;
+ output CAL4;
+ output CAL5;
+ output CAL_LOCKED;
+ input CLK_CAL;
+ output CLK_CAL_DIV;
+ output CLK_DIV1;
+ output CLK_DIV2;
+ output CLK_DIV3;
+ output CLK_DIV4;
+ output CLK_DIVD1;
+ output CLK_DIVD2;
+ output CLK_DIVD3;
+ output CLK_DIVD4;
+ output CLK_DIVD5;
+ input EXT_CAL1;
+ input EXT_CAL2;
+ input EXT_CAL3;
+ input EXT_CAL4;
+ input EXT_CAL5;
+ input EXT_CAL_LOCKED;
+ input FBK;
+ output LDFO;
+ output OSC;
+ output PLL_LOCKED;
+ output PLL_LOCKEDA;
+ input R;
+ input REF;
+ output REFO;
+ output VCO;
+ parameter cal_delay = 6'b011011;
+ parameter cal_div = 4'b0111;
+ parameter clk_cal_sel = 2'b01;
+ parameter clk_outdiv1 = 3'b000;
+ parameter clk_outdiv2 = 3'b000;
+ parameter clk_outdiv3 = 3'b000;
+ parameter clk_outdiv4 = 3'b000;
+ parameter clk_outdivd1 = 4'b0000;
+ parameter clk_outdivd2 = 4'b0000;
+ parameter clk_outdivd3 = 4'b0000;
+ parameter clk_outdivd4 = 4'b0000;
+ parameter clk_outdivd5 = 4'b0000;
+ parameter ext_fbk_on = 1'b0;
+ parameter fbk_delay = 6'b000000;
+ parameter fbk_delay_on = 1'b0;
+ parameter fbk_intdiv = 7'b0000000;
+ parameter location = "";
+ parameter pll_cpump = 4'b0000;
+ parameter pll_lock = 4'b0000;
+ parameter pll_lpf_cap = 4'b0000;
+ parameter pll_lpf_res = 4'b0000;
+ parameter pll_odf = 2'b00;
+ parameter ref_intdiv = 5'b00000;
+ parameter ref_osc_on = 1'b0;
+ parameter use_cal = 1'b0;
+ parameter use_pll = 1'b1;
+endmodule
+
+(* blackbox *)
+module NX_CRX_U(DSCR_E_I, DEC_E_I, ALIGN_E_I, ALIGN_S_I, REP_E_I, BUF_R_I, OVS_BS_I1, OVS_BS_I2, RST_N_I, PMA_RSTN_I, MEYE_RST_I, PWDN_N_I, DBG_S_I1, DBG_S_I2, DBG_S_I3, DATA_O1, DATA_O2, DATA_O3, DATA_O4, DATA_O5, DATA_O6
+, DATA_O7, DATA_O8, DATA_O9, DATA_O10, DATA_O11, DATA_O12, DATA_O13, DATA_O14, DATA_O15, DATA_O16, DATA_O17, DATA_O18, DATA_O19, DATA_O20, DATA_O21, DATA_O22, DATA_O23, DATA_O24, DATA_O25, DATA_O26, DATA_O27
+, DATA_O28, DATA_O29, DATA_O30, DATA_O31, DATA_O32, DATA_O33, DATA_O34, DATA_O35, DATA_O36, DATA_O37, DATA_O38, DATA_O39, DATA_O40, DATA_O41, DATA_O42, DATA_O43, DATA_O44, DATA_O45, DATA_O46, DATA_O47, DATA_O48
+, DATA_O49, DATA_O50, DATA_O51, DATA_O52, DATA_O53, DATA_O54, DATA_O55, DATA_O56, DATA_O57, DATA_O58, DATA_O59, DATA_O60, DATA_O61, DATA_O62, DATA_O63, DATA_O64, CH_COM_O1, CH_COM_O2, CH_COM_O3, CH_COM_O4, CH_COM_O5
+, CH_COM_O6, CH_COM_O7, CH_COM_O8, CH_K_O1, CH_K_O2, CH_K_O3, CH_K_O4, CH_K_O5, CH_K_O6, CH_K_O7, CH_K_O8, NIT_O1, NIT_O2, NIT_O3, NIT_O4, NIT_O5, NIT_O6, NIT_O7, NIT_O8, D_ERR_O1, D_ERR_O2
+, D_ERR_O3, D_ERR_O4, D_ERR_O5, D_ERR_O6, D_ERR_O7, D_ERR_O8, CH_A_O1, CH_A_O2, CH_A_O3, CH_A_O4, CH_A_O5, CH_A_O6, CH_A_O7, CH_A_O8, CH_F_O1, CH_F_O2, CH_F_O3, CH_F_O4, CH_F_O5, CH_F_O6, CH_F_O7
+, CH_F_O8, ALIGN_O, VREALIGN_O, BUSY_O, TST_O1, TST_O2, TST_O3, TST_O4, TST_O5, TST_O6, TST_O7, TST_O8, LOS_O, LL_FLOCK_O, LL_SLOCK_O, PLL_LOCK_O, PLL_LOCKT_O, LINK);
+ input ALIGN_E_I;
+ output ALIGN_O;
+ input ALIGN_S_I;
+ input BUF_R_I;
+ output BUSY_O;
+ output CH_A_O1;
+ output CH_A_O2;
+ output CH_A_O3;
+ output CH_A_O4;
+ output CH_A_O5;
+ output CH_A_O6;
+ output CH_A_O7;
+ output CH_A_O8;
+ output CH_COM_O1;
+ output CH_COM_O2;
+ output CH_COM_O3;
+ output CH_COM_O4;
+ output CH_COM_O5;
+ output CH_COM_O6;
+ output CH_COM_O7;
+ output CH_COM_O8;
+ output CH_F_O1;
+ output CH_F_O2;
+ output CH_F_O3;
+ output CH_F_O4;
+ output CH_F_O5;
+ output CH_F_O6;
+ output CH_F_O7;
+ output CH_F_O8;
+ output CH_K_O1;
+ output CH_K_O2;
+ output CH_K_O3;
+ output CH_K_O4;
+ output CH_K_O5;
+ output CH_K_O6;
+ output CH_K_O7;
+ output CH_K_O8;
+ output DATA_O1;
+ output DATA_O10;
+ output DATA_O11;
+ output DATA_O12;
+ output DATA_O13;
+ output DATA_O14;
+ output DATA_O15;
+ output DATA_O16;
+ output DATA_O17;
+ output DATA_O18;
+ output DATA_O19;
+ output DATA_O2;
+ output DATA_O20;
+ output DATA_O21;
+ output DATA_O22;
+ output DATA_O23;
+ output DATA_O24;
+ output DATA_O25;
+ output DATA_O26;
+ output DATA_O27;
+ output DATA_O28;
+ output DATA_O29;
+ output DATA_O3;
+ output DATA_O30;
+ output DATA_O31;
+ output DATA_O32;
+ output DATA_O33;
+ output DATA_O34;
+ output DATA_O35;
+ output DATA_O36;
+ output DATA_O37;
+ output DATA_O38;
+ output DATA_O39;
+ output DATA_O4;
+ output DATA_O40;
+ output DATA_O41;
+ output DATA_O42;
+ output DATA_O43;
+ output DATA_O44;
+ output DATA_O45;
+ output DATA_O46;
+ output DATA_O47;
+ output DATA_O48;
+ output DATA_O49;
+ output DATA_O5;
+ output DATA_O50;
+ output DATA_O51;
+ output DATA_O52;
+ output DATA_O53;
+ output DATA_O54;
+ output DATA_O55;
+ output DATA_O56;
+ output DATA_O57;
+ output DATA_O58;
+ output DATA_O59;
+ output DATA_O6;
+ output DATA_O60;
+ output DATA_O61;
+ output DATA_O62;
+ output DATA_O63;
+ output DATA_O64;
+ output DATA_O7;
+ output DATA_O8;
+ output DATA_O9;
+ input DBG_S_I1;
+ input DBG_S_I2;
+ input DBG_S_I3;
+ input DEC_E_I;
+ input DSCR_E_I;
+ output D_ERR_O1;
+ output D_ERR_O2;
+ output D_ERR_O3;
+ output D_ERR_O4;
+ output D_ERR_O5;
+ output D_ERR_O6;
+ output D_ERR_O7;
+ output D_ERR_O8;
+ inout [9:0] LINK;
+ output LL_FLOCK_O;
+ output LL_SLOCK_O;
+ output LOS_O;
+ input MEYE_RST_I;
+ output NIT_O1;
+ output NIT_O2;
+ output NIT_O3;
+ output NIT_O4;
+ output NIT_O5;
+ output NIT_O6;
+ output NIT_O7;
+ output NIT_O8;
+ input OVS_BS_I1;
+ input OVS_BS_I2;
+ output PLL_LOCKT_O;
+ output PLL_LOCK_O;
+ input PMA_RSTN_I;
+ input PWDN_N_I;
+ input REP_E_I;
+ input RST_N_I;
+ output TST_O1;
+ output TST_O2;
+ output TST_O3;
+ output TST_O4;
+ output TST_O5;
+ output TST_O6;
+ output TST_O7;
+ output TST_O8;
+ output VREALIGN_O;
+ parameter gearbox_en = 1'b0;
+ parameter gearbox_mode = 1'b0;
+ parameter location = "";
+ parameter pcs_8b_dscr_sel = 1'b0;
+ parameter pcs_align_bypass = 1'b0;
+ parameter pcs_buffers_bypass = 1'b0;
+ parameter pcs_buffers_use_cdc = 1'b0;
+ parameter pcs_bypass_pma_cdc = 1'b0;
+ parameter pcs_bypass_usr_cdc = 1'b0;
+ parameter pcs_comma_mask = 10'b0000000000;
+ parameter pcs_debug_en = 1'b0;
+ parameter pcs_dec_bypass = 1'b0;
+ parameter pcs_dscr_bypass = 1'b0;
+ parameter pcs_el_buff_diff_bef_comp = 4'b0000;
+ parameter pcs_el_buff_max_comp = 4'b0000;
+ parameter pcs_el_buff_only_one_skp = 1'b0;
+ parameter pcs_el_buff_skp_char_0 = 9'b000000000;
+ parameter pcs_el_buff_skp_char_1 = 9'b000000000;
+ parameter pcs_el_buff_skp_char_2 = 9'b000000000;
+ parameter pcs_el_buff_skp_char_3 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_0 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_1 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_2 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_3 = 9'b000000000;
+ parameter pcs_el_buff_skp_header_size = 2'b00;
+ parameter pcs_el_buff_skp_seq_size = 2'b00;
+ parameter pcs_fsm_sel = 2'b00;
+ parameter pcs_fsm_watchdog_en = 1'b0;
+ parameter pcs_loopback = 1'b0;
+ parameter pcs_m_comma_en = 1'b0;
+ parameter pcs_m_comma_val = 10'b0000000000;
+ parameter pcs_nb_comma_bef_realign = 2'b00;
+ parameter pcs_p_comma_en = 1'b0;
+ parameter pcs_p_comma_val = 10'b0000000000;
+ parameter pcs_polarity = 1'b0;
+ parameter pcs_protocol_size = 1'b0;
+ parameter pcs_replace_bypass = 1'b0;
+ parameter pcs_sync_supported = 1'b0;
+ parameter pma_cdr_cp = 4'b0000;
+ parameter pma_clk_pos = 1'b0;
+ parameter pma_coarse_ppm = 3'b000;
+ parameter pma_ctrl_term = 6'b000000;
+ parameter pma_dco_divl = 2'b00;
+ parameter pma_dco_divm = 1'b0;
+ parameter pma_dco_divn = 2'b00;
+ parameter pma_dco_reg_res = 2'b00;
+ parameter pma_dco_vref_sel = 1'b0;
+ parameter pma_fine_ppm = 3'b000;
+ parameter pma_loopback = 1'b0;
+ parameter pma_m_eye_ppm = 3'b000;
+ parameter pma_peak_detect_cmd = 2'b00;
+ parameter pma_peak_detect_on = 1'b0;
+ parameter pma_pll_cpump_n = 3'b000;
+ parameter pma_pll_divf = 2'b00;
+ parameter pma_pll_divf_en_n = 1'b0;
+ parameter pma_pll_divm = 2'b00;
+ parameter pma_pll_divm_en_n = 1'b0;
+ parameter pma_pll_divn = 1'b0;
+ parameter pma_pll_divn_en_n = 1'b0;
+endmodule
+
+
+(* blackbox *)
+module NX_CTX_U(ENC_E_I1, ENC_E_I2, ENC_E_I3, ENC_E_I4, ENC_E_I5, ENC_E_I6, ENC_E_I7, ENC_E_I8, CH_K_I1, CH_K_I2, CH_K_I3, CH_K_I4, CH_K_I5, CH_K_I6, CH_K_I7, CH_K_I8, SCR_E_I1, SCR_E_I2, SCR_E_I3, SCR_E_I4, SCR_E_I5
+, SCR_E_I6, SCR_E_I7, SCR_E_I8, EOMF_I1, EOMF_I2, EOMF_I3, EOMF_I4, EOMF_I5, EOMF_I6, EOMF_I7, EOMF_I8, EOF_I1, EOF_I2, EOF_I3, EOF_I4, EOF_I5, EOF_I6, EOF_I7, EOF_I8, REP_E_I, RST_N_I
+, DATA_I1, DATA_I2, DATA_I3, DATA_I4, DATA_I5, DATA_I6, DATA_I7, DATA_I8, DATA_I9, DATA_I10, DATA_I11, DATA_I12, DATA_I13, DATA_I14, DATA_I15, DATA_I16, DATA_I17, DATA_I18, DATA_I19, DATA_I20, DATA_I21
+, DATA_I22, DATA_I23, DATA_I24, DATA_I25, DATA_I26, DATA_I27, DATA_I28, DATA_I29, DATA_I30, DATA_I31, DATA_I32, DATA_I33, DATA_I34, DATA_I35, DATA_I36, DATA_I37, DATA_I38, DATA_I39, DATA_I40, DATA_I41, DATA_I42
+, DATA_I43, DATA_I44, DATA_I45, DATA_I46, DATA_I47, DATA_I48, DATA_I49, DATA_I50, DATA_I51, DATA_I52, DATA_I53, DATA_I54, DATA_I55, DATA_I56, DATA_I57, DATA_I58, DATA_I59, DATA_I60, DATA_I61, DATA_I62, DATA_I63
+, DATA_I64, BUSY_O, INV_K_O, PWDN_N_I, CLK_E_I, CLK_O, LINK);
+ output BUSY_O;
+ input CH_K_I1;
+ input CH_K_I2;
+ input CH_K_I3;
+ input CH_K_I4;
+ input CH_K_I5;
+ input CH_K_I6;
+ input CH_K_I7;
+ input CH_K_I8;
+ input CLK_E_I;
+ output CLK_O;
+ input DATA_I1;
+ input DATA_I10;
+ input DATA_I11;
+ input DATA_I12;
+ input DATA_I13;
+ input DATA_I14;
+ input DATA_I15;
+ input DATA_I16;
+ input DATA_I17;
+ input DATA_I18;
+ input DATA_I19;
+ input DATA_I2;
+ input DATA_I20;
+ input DATA_I21;
+ input DATA_I22;
+ input DATA_I23;
+ input DATA_I24;
+ input DATA_I25;
+ input DATA_I26;
+ input DATA_I27;
+ input DATA_I28;
+ input DATA_I29;
+ input DATA_I3;
+ input DATA_I30;
+ input DATA_I31;
+ input DATA_I32;
+ input DATA_I33;
+ input DATA_I34;
+ input DATA_I35;
+ input DATA_I36;
+ input DATA_I37;
+ input DATA_I38;
+ input DATA_I39;
+ input DATA_I4;
+ input DATA_I40;
+ input DATA_I41;
+ input DATA_I42;
+ input DATA_I43;
+ input DATA_I44;
+ input DATA_I45;
+ input DATA_I46;
+ input DATA_I47;
+ input DATA_I48;
+ input DATA_I49;
+ input DATA_I5;
+ input DATA_I50;
+ input DATA_I51;
+ input DATA_I52;
+ input DATA_I53;
+ input DATA_I54;
+ input DATA_I55;
+ input DATA_I56;
+ input DATA_I57;
+ input DATA_I58;
+ input DATA_I59;
+ input DATA_I6;
+ input DATA_I60;
+ input DATA_I61;
+ input DATA_I62;
+ input DATA_I63;
+ input DATA_I64;
+ input DATA_I7;
+ input DATA_I8;
+ input DATA_I9;
+ input ENC_E_I1;
+ input ENC_E_I2;
+ input ENC_E_I3;
+ input ENC_E_I4;
+ input ENC_E_I5;
+ input ENC_E_I6;
+ input ENC_E_I7;
+ input ENC_E_I8;
+ input EOF_I1;
+ input EOF_I2;
+ input EOF_I3;
+ input EOF_I4;
+ input EOF_I5;
+ input EOF_I6;
+ input EOF_I7;
+ input EOF_I8;
+ input EOMF_I1;
+ input EOMF_I2;
+ input EOMF_I3;
+ input EOMF_I4;
+ input EOMF_I5;
+ input EOMF_I6;
+ input EOMF_I7;
+ input EOMF_I8;
+ output INV_K_O;
+ inout [19:0] LINK;
+ input PWDN_N_I;
+ input REP_E_I;
+ input RST_N_I;
+ input SCR_E_I1;
+ input SCR_E_I2;
+ input SCR_E_I3;
+ input SCR_E_I4;
+ input SCR_E_I5;
+ input SCR_E_I6;
+ input SCR_E_I7;
+ input SCR_E_I8;
+ parameter gearbox_en = 1'b0;
+ parameter gearbox_mode = 1'b0;
+ parameter location = "";
+ parameter pcs_8b_scr_sel = 1'b0;
+ parameter pcs_bypass_pma_cdc = 1'b0;
+ parameter pcs_bypass_usr_cdc = 1'b0;
+ parameter pcs_enc_bypass = 1'b0;
+ parameter pcs_esistream_fsm_en = 1'b0;
+ parameter pcs_loopback = 1'b0;
+ parameter pcs_polarity = 1'b0;
+ parameter pcs_protocol_size = 1'b0;
+ parameter pcs_replace_bypass = 1'b0;
+ parameter pcs_scr_bypass = 1'b0;
+ parameter pcs_scr_init = 17'b00000000000000000;
+ parameter pcs_sync_supported = 1'b0;
+ parameter pma_clk_pos = 1'b0;
+ parameter pma_loopback = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1
+, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6
+, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN
+, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN
+, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1
+, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6
+, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, P1CI1, P1CL, P1CR, P1CO, P1CTI, P1CTO, P1EI1, P1EI2, P1EI3, P1EI4, P1EI5, P1EI6, P1EI7, P1EI8, P1EL, P1ER, P1EO, P1RI, P1RL
+, P1RR, P1RO1, P1RO2, P1RO3, P1RO4, P1RO5, P1RO6, P1RO7, P1RO8, P2CI1, P2CL, P2CR, P2CO, P2CTI, P2CTO, P2EI1, P2EI2, P2EI3, P2EI4, P2EI5, P2EI6
+, P2EI7, P2EI8, P2EL, P2ER, P2EO, P2RI, P2RL, P2RR, P2RO1, P2RO2, P2RO3, P2RO4, P2RO5, P2RO6, P2RO7, P2RO8, P3CI1, P3CL, P3CR, P3CO, P3CTI
+, P3CTO, P3EI1, P3EI2, P3EI3, P3EI4, P3EI5, P3EI6, P3EI7, P3EI8, P3EL, P3ER, P3EO, P3RI, P3RL, P3RR, P3RO1, P3RO2, P3RO3, P3RO4, P3RO5, P3RO6
+, P3RO7, P3RO8, P4CI1, P4CL, P4CR, P4CO, P4CTI, P4CTO, P4EI1, P4EI2, P4EI3, P4EI4, P4EI5, P4EI6, P4EI7, P4EI8, P4EL, P4ER, P4EO, P4RI, P4RL
+, P4RR, P4RO1, P4RO2, P4RO3, P4RO4, P4RO5, P4RO6, P4RO7, P4RO8, P5CI1, P5CL, P5CR, P5CO, P5CTI, P5CTO, P5EI1, P5EI2, P5EI3, P5EI4, P5EI5, P5EI6
+, P5EI7, P5EI8, P5EL, P5ER, P5EO, P5RI, P5RL, P5RR, P5RO1, P5RO2, P5RO3, P5RO4, P5RO5, P5RO6, P5RO7, P5RO8, P6CI1, P6CL, P6CR, P6CO, P6CTI
+, P6CTO, P6EI1, P6EI2, P6EI3, P6EI4, P6EI5, P6EI6, P6EI7, P6EI8, P6EL, P6ER, P6EO, P6RI, P6RL, P6RR, P6RO1, P6RO2, P6RO3, P6RO4, P6RO5, P6RO6
+, P6RO7, P6RO8, P7CI1, P7CL, P7CR, P7CO, P7CTI, P7CTO, P7EI1, P7EI2, P7EI3, P7EI4, P7EI5, P7EI6, P7EI7, P7EI8, P7EL, P7ER, P7EO, P7RI, P7RL
+, P7RR, P7RO1, P7RO2, P7RO3, P7RO4, P7RO5, P7RO6, P7RO7, P7RO8, P8CI1, P8CL, P8CR, P8CO, P8CTI, P8CTO, P8EI1, P8EI2, P8EI3, P8EI4, P8EI5, P8EI6
+, P8EI7, P8EI8, P8EL, P8ER, P8EO, P8RI, P8RL, P8RR, P8RO1, P8RO2, P8RO3, P8RO4, P8RO5, P8RO6, P8RO7, P8RO8, P9CI1, P9CL, P9CR, P9CO, P9CTI
+, P9CTO, P9EI1, P9EI2, P9EI3, P9EI4, P9EI5, P9EI6, P9EI7, P9EI8, P9EL, P9ER, P9EO, P9RI, P9RL, P9RR, P9RO1, P9RO2, P9RO3, P9RO4, P9RO5, P9RO6
+, P9RO7, P9RO8, P10CI1, P10CL, P10CR, P10CO, P10CTI, P10CTO, P10EI1, P10EI2, P10EI3, P10EI4, P10EI5, P10EI6, P10EI7, P10EI8, P10EL, P10ER, P10EO, P10RI, P10RL
+, P10RR, P10RO1, P10RO2, P10RO3, P10RO4, P10RO5, P10RO6, P10RO7, P10RO8, P11CI1, P11CL, P11CR, P11CO, P11CTI, P11CTO, P11EI1, P11EI2, P11EI3, P11EI4, P11EI5, P11EI6
+, P11EI7, P11EI8, P11EL, P11ER, P11EO, P11RI, P11RL, P11RR, P11RO1, P11RO2, P11RO3, P11RO4, P11RO5, P11RO6, P11RO7, P11RO8, P12CI1, P12CL, P12CR, P12CO, P12CTI
+, P12CTO, P12EI1, P12EI2, P12EI3, P12EI4, P12EI5, P12EI6, P12EI7, P12EI8, P12EL, P12ER, P12EO, P12RI, P12RL, P12RR, P12RO1, P12RO2, P12RO3, P12RO4, P12RO5, P12RO6
+, P12RO7, P12RO8, P13CI1, P13CL, P13CR, P13CO, P13CTI, P13CTO, P13EI1, P13EI2, P13EI3, P13EI4, P13EI5, P13EI6, P13EI7, P13EI8, P13EL, P13ER, P13EO, P13RI, P13RL
+, P13RR, P13RO1, P13RO2, P13RO3, P13RO4, P13RO5, P13RO6, P13RO7, P13RO8, P14CI1, P14CL, P14CR, P14CO, P14CTI, P14CTO, P14EI1, P14EI2, P14EI3, P14EI4, P14EI5, P14EI6
+, P14EI7, P14EI8, P14EL, P14ER, P14EO, P14RI, P14RL, P14RR, P14RO1, P14RO2, P14RO3, P14RO4, P14RO5, P14RO6, P14RO7, P14RO8, P15CI1, P15CL, P15CR, P15CO, P15CTI
+, P15CTO, P15EI1, P15EI2, P15EI3, P15EI4, P15EI5, P15EI6, P15EI7, P15EI8, P15EL, P15ER, P15EO, P15RI, P15RL, P15RR, P15RO1, P15RO2, P15RO3, P15RO4, P15RO5, P15RO6
+, P15RO7, P15RO8, P16CI1, P16CL, P16CR, P16CO, P16CTI, P16CTO, P16EI1, P16EI2, P16EI3, P16EI4, P16EI5, P16EI6, P16EI7, P16EI8, P16EL, P16ER, P16EO, P16RI, P16RL
+, P16RR, P16RO1, P16RO2, P16RO3, P16RO4, P16RO5, P16RO6, P16RO7, P16RO8, P17CI1, P17CL, P17CR, P17CO, P17CTI, P17CTO, P17EI1, P17EI2, P17EI3, P17EI4, P17EI5, P17EI6
+, P17EI7, P17EI8, P17EL, P17ER, P17EO, P17RI, P17RL, P17RR, P17RO1, P17RO2, P17RO3, P17RO4, P17RO5, P17RO6, P17RO7, P17RO8, P18CI1, P18CL, P18CR, P18CO, P18CTI
+, P18CTO, P18EI1, P18EI2, P18EI3, P18EI4, P18EI5, P18EI6, P18EI7, P18EI8, P18EL, P18ER, P18EO, P18RI, P18RL, P18RR, P18RO1, P18RO2, P18RO3, P18RO4, P18RO5, P18RO6
+, P18RO7, P18RO8, P19CI1, P19CL, P19CR, P19CO, P19CTI, P19CTO, P19EI1, P19EI2, P19EI3, P19EI4, P19EI5, P19EI6, P19EI7, P19EI8, P19EL, P19ER, P19EO, P19RI, P19RL
+, P19RR, P19RO1, P19RO2, P19RO3, P19RO4, P19RO5, P19RO6, P19RO7, P19RO8, P20CI1, P20CL, P20CR, P20CO, P20CTI, P20CTO, P20EI1, P20EI2, P20EI3, P20EI4, P20EI5, P20EI6
+, P20EI7, P20EI8, P20EL, P20ER, P20EO, P20RI, P20RL, P20RR, P20RO1, P20RO2, P20RO3, P20RO4, P20RO5, P20RO6, P20RO7, P20RO8, P21CI1, P21CL, P21CR, P21CO, P21CTI
+, P21CTO, P21EI1, P21EI2, P21EI3, P21EI4, P21EI5, P21EI6, P21EI7, P21EI8, P21EL, P21ER, P21EO, P21RI, P21RL, P21RR, P21RO1, P21RO2, P21RO3, P21RO4, P21RO5, P21RO6
+, P21RO7, P21RO8, P22CI1, P22CL, P22CR, P22CO, P22CTI, P22CTO, P22EI1, P22EI2, P22EI3, P22EI4, P22EI5, P22EI6, P22EI7, P22EI8, P22EL, P22ER, P22EO, P22RI, P22RL
+, P22RR, P22RO1, P22RO2, P22RO3, P22RO4, P22RO5, P22RO6, P22RO7, P22RO8, P23CI1, P23CL, P23CR, P23CO, P23CTI, P23CTO, P23EI1, P23EI2, P23EI3, P23EI4, P23EI5, P23EI6
+, P23EI7, P23EI8, P23EL, P23ER, P23EO, P23RI, P23RL, P23RR, P23RO1, P23RO2, P23RO3, P23RO4, P23RO5, P23RO6, P23RO7, P23RO8, P24CI1, P24CL, P24CR, P24CO, P24CTI
+, P24CTO, P24EI1, P24EI2, P24EI3, P24EI4, P24EI5, P24EI6, P24EI7, P24EI8, P24EL, P24ER, P24EO, P24RI, P24RL, P24RR, P24RO1, P24RO2, P24RO3, P24RO4, P24RO5, P24RO6
+, P24RO7, P24RO8, P25CI1, P25CL, P25CR, P25CO, P25CTI, P25CTO, P25EI1, P25EI2, P25EI3, P25EI4, P25EI5, P25EI6, P25EI7, P25EI8, P25EL, P25ER, P25EO, P25RI, P25RL
+, P25RR, P25RO1, P25RO2, P25RO3, P25RO4, P25RO5, P25RO6, P25RO7, P25RO8, P26CI1, P26CL, P26CR, P26CO, P26CTI, P26CTO, P26EI1, P26EI2, P26EI3, P26EI4, P26EI5, P26EI6
+, P26EI7, P26EI8, P26EL, P26ER, P26EO, P26RI, P26RL, P26RR, P26RO1, P26RO2, P26RO3, P26RO4, P26RO5, P26RO6, P26RO7, P26RO8, P27CI1, P27CL, P27CR, P27CO, P27CTI
+, P27CTO, P27EI1, P27EI2, P27EI3, P27EI4, P27EI5, P27EI6, P27EI7, P27EI8, P27EL, P27ER, P27EO, P27RI, P27RL, P27RR, P27RO1, P27RO2, P27RO3, P27RO4, P27RO5, P27RO6
+, P27RO7, P27RO8, P28CI1, P28CL, P28CR, P28CO, P28CTI, P28CTO, P28EI1, P28EI2, P28EI3, P28EI4, P28EI5, P28EI6, P28EI7, P28EI8, P28EL, P28ER, P28EO, P28RI, P28RL
+, P28RR, P28RO1, P28RO2, P28RO3, P28RO4, P28RO5, P28RO6, P28RO7, P28RO8, P29CI1, P29CL, P29CR, P29CO, P29CTI, P29CTO, P29EI1, P29EI2, P29EI3, P29EI4, P29EI5, P29EI6
+, P29EI7, P29EI8, P29EL, P29ER, P29EO, P29RI, P29RL, P29RR, P29RO1, P29RO2, P29RO3, P29RO4, P29RO5, P29RO6, P29RO7, P29RO8, P30CI1, P30CL, P30CR, P30CO, P30CTI
+, P30CTO, P30EI1, P30EI2, P30EI3, P30EI4, P30EI5, P30EI6, P30EI7, P30EI8, P30EL, P30ER, P30EO, P30RI, P30RL, P30RR, P30RO1, P30RO2, P30RO3, P30RO4, P30RO5, P30RO6
+, P30RO7, P30RO8, P31CI1, P31CL, P31CR, P31CO, P31CTI, P31CTO, P31EI1, P31EI2, P31EI3, P31EI4, P31EI5, P31EI6, P31EI7, P31EI8, P31EL, P31ER, P31EO, P31RI, P31RL
+, P31RR, P31RO1, P31RO2, P31RO3, P31RO4, P31RO5, P31RO6, P31RO7, P31RO8, P32CI1, P32CL, P32CR, P32CO, P32CTI, P32CTO, P32EI1, P32EI2, P32EI3, P32EI4, P32EI5, P32EI6
+, P32EI7, P32EI8, P32EL, P32ER, P32EO, P32RI, P32RL, P32RR, P32RO1, P32RO2, P32RO3, P32RO4, P32RO5, P32RO6, P32RO7, P32RO8, P33CI1, P33CL, P33CR, P33CO, P33CTI
+, P33CTO, P33EI1, P33EI2, P33EI3, P33EI4, P33EI5, P33EI6, P33EI7, P33EI8, P33EL, P33ER, P33EO, P33RI, P33RL, P33RR, P33RO1, P33RO2, P33RO3, P33RO4, P33RO5, P33RO6
+, P33RO7, P33RO8, P34CI1, P34CL, P34CR, P34CO, P34CTI, P34CTO, P34EI1, P34EI2, P34EI3, P34EI4, P34EI5, P34EI6, P34EI7, P34EI8, P34EL, P34ER, P34EO, P34RI, P34RL
+, P34RR, P34RO1, P34RO2, P34RO3, P34RO4, P34RO5, P34RO6, P34RO7, P34RO8);
+ output AL1D;
+ output AL1T;
+ output AL2D;
+ output AL2T;
+ output AL3D;
+ output AL3T;
+ input ALCK1;
+ input ALCK2;
+ input ALCK3;
+ input CA1D1;
+ input CA1D2;
+ input CA1D3;
+ input CA1D4;
+ input CA1D5;
+ input CA1D6;
+ input CA1N1;
+ input CA1N2;
+ input CA1N3;
+ input CA1N4;
+ input CA1P1;
+ input CA1P2;
+ input CA1P3;
+ input CA1P4;
+ input CA1T1;
+ input CA1T2;
+ input CA1T3;
+ input CA1T4;
+ input CA2D1;
+ input CA2D2;
+ input CA2D3;
+ input CA2D4;
+ input CA2D5;
+ input CA2D6;
+ input CA2N1;
+ input CA2N2;
+ input CA2N3;
+ input CA2N4;
+ input CA2P1;
+ input CA2P2;
+ input CA2P3;
+ input CA2P4;
+ input CA2T1;
+ input CA2T2;
+ input CA2T3;
+ input CA2T4;
+ input CCK;
+ output CKO1;
+ output CKO2;
+ output DCL;
+ input DCRN;
+ input DQ1CI1;
+ input DQ1CI2;
+ input DQ1CI3;
+ input DQ1CI4;
+ input DQ1CI5;
+ input DQ1CI6;
+ input DQ1CI7;
+ input DQ1CI8;
+ input DQ2CI1;
+ input DQ2CI2;
+ input DQ2CI3;
+ input DQ2CI4;
+ input DQ2CI5;
+ input DQ2CI6;
+ input DQ2CI7;
+ input DQ2CI8;
+ input DQ3CI1;
+ input DQ3CI2;
+ input DQ3CI3;
+ input DQ3CI4;
+ input DQ3CI5;
+ input DQ3CI6;
+ input DQ3CI7;
+ input DQ3CI8;
+ input DQS1CI1;
+ input DQS1CI2;
+ input DQS1CI3;
+ input DQS1CI4;
+ input DQS1CI5;
+ input DQS1CI6;
+ input DQS1CI7;
+ input DQS1CI8;
+ input DQS2CI1;
+ input DQS2CI2;
+ input DQS2CI3;
+ input DQS2CI4;
+ input DQS2CI5;
+ input DQS2CI6;
+ input DQS2CI7;
+ input DQS2CI8;
+ input DQS3CI1;
+ input DQS3CI2;
+ input DQS3CI3;
+ input DQS3CI4;
+ input DQS3CI5;
+ input DQS3CI6;
+ input DQS3CI7;
+ input DQS3CI8;
+ input DRA1;
+ input DRA2;
+ input DRA3;
+ input DRA4;
+ input DRCCSN;
+ input DRDPA1CSN;
+ input DRDPA2CSN;
+ input DRDPA3CSN;
+ input DRE;
+ input DRI1;
+ input DRI1CSN;
+ input DRI2;
+ input DRI2CSN;
+ input DRI3;
+ input DRI3CSN;
+ input DRI4;
+ input DRI5;
+ input DRI6;
+ output DRO1;
+ input DRO1CSN;
+ output DRO2;
+ input DRO2CSN;
+ output DRO3;
+ input DRO3CSN;
+ output DRO4;
+ output DRO5;
+ output DRO6;
+ input DRWDS;
+ input DRWEN;
+ input FA1;
+ input FA2;
+ input FA3;
+ input FA4;
+ input FA5;
+ input FA6;
+ input FCK1;
+ input FCK2;
+ input FDCK;
+ output FLD;
+ output FLG;
+ input FZ;
+ input LD1RN;
+ input LD2RN;
+ input LD3RN;
+ input LDSCK1;
+ input LDSCK2;
+ input LDSCK3;
+ input LE;
+ input P10CI1;
+ input P10CL;
+ output P10CO;
+ input P10CR;
+ input P10CTI;
+ output P10CTO;
+ input P10EI1;
+ input P10EI2;
+ input P10EI3;
+ input P10EI4;
+ input P10EI5;
+ input P10EI6;
+ input P10EI7;
+ input P10EI8;
+ input P10EL;
+ output P10EO;
+ input P10ER;
+ input P10RI;
+ input P10RL;
+ output P10RO1;
+ output P10RO2;
+ output P10RO3;
+ output P10RO4;
+ output P10RO5;
+ output P10RO6;
+ output P10RO7;
+ output P10RO8;
+ input P10RR;
+ input P11CI1;
+ input P11CL;
+ output P11CO;
+ input P11CR;
+ input P11CTI;
+ output P11CTO;
+ input P11EI1;
+ input P11EI2;
+ input P11EI3;
+ input P11EI4;
+ input P11EI5;
+ input P11EI6;
+ input P11EI7;
+ input P11EI8;
+ input P11EL;
+ output P11EO;
+ input P11ER;
+ input P11RI;
+ input P11RL;
+ output P11RO1;
+ output P11RO2;
+ output P11RO3;
+ output P11RO4;
+ output P11RO5;
+ output P11RO6;
+ output P11RO7;
+ output P11RO8;
+ input P11RR;
+ input P12CI1;
+ input P12CL;
+ output P12CO;
+ input P12CR;
+ input P12CTI;
+ output P12CTO;
+ input P12EI1;
+ input P12EI2;
+ input P12EI3;
+ input P12EI4;
+ input P12EI5;
+ input P12EI6;
+ input P12EI7;
+ input P12EI8;
+ input P12EL;
+ output P12EO;
+ input P12ER;
+ input P12RI;
+ input P12RL;
+ output P12RO1;
+ output P12RO2;
+ output P12RO3;
+ output P12RO4;
+ output P12RO5;
+ output P12RO6;
+ output P12RO7;
+ output P12RO8;
+ input P12RR;
+ input P13CI1;
+ input P13CL;
+ output P13CO;
+ input P13CR;
+ input P13CTI;
+ output P13CTO;
+ input P13EI1;
+ input P13EI2;
+ input P13EI3;
+ input P13EI4;
+ input P13EI5;
+ input P13EI6;
+ input P13EI7;
+ input P13EI8;
+ input P13EL;
+ output P13EO;
+ input P13ER;
+ input P13RI;
+ input P13RL;
+ output P13RO1;
+ output P13RO2;
+ output P13RO3;
+ output P13RO4;
+ output P13RO5;
+ output P13RO6;
+ output P13RO7;
+ output P13RO8;
+ input P13RR;
+ input P14CI1;
+ input P14CL;
+ output P14CO;
+ input P14CR;
+ input P14CTI;
+ output P14CTO;
+ input P14EI1;
+ input P14EI2;
+ input P14EI3;
+ input P14EI4;
+ input P14EI5;
+ input P14EI6;
+ input P14EI7;
+ input P14EI8;
+ input P14EL;
+ output P14EO;
+ input P14ER;
+ input P14RI;
+ input P14RL;
+ output P14RO1;
+ output P14RO2;
+ output P14RO3;
+ output P14RO4;
+ output P14RO5;
+ output P14RO6;
+ output P14RO7;
+ output P14RO8;
+ input P14RR;
+ input P15CI1;
+ input P15CL;
+ output P15CO;
+ input P15CR;
+ input P15CTI;
+ output P15CTO;
+ input P15EI1;
+ input P15EI2;
+ input P15EI3;
+ input P15EI4;
+ input P15EI5;
+ input P15EI6;
+ input P15EI7;
+ input P15EI8;
+ input P15EL;
+ output P15EO;
+ input P15ER;
+ input P15RI;
+ input P15RL;
+ output P15RO1;
+ output P15RO2;
+ output P15RO3;
+ output P15RO4;
+ output P15RO5;
+ output P15RO6;
+ output P15RO7;
+ output P15RO8;
+ input P15RR;
+ input P16CI1;
+ input P16CL;
+ output P16CO;
+ input P16CR;
+ input P16CTI;
+ output P16CTO;
+ input P16EI1;
+ input P16EI2;
+ input P16EI3;
+ input P16EI4;
+ input P16EI5;
+ input P16EI6;
+ input P16EI7;
+ input P16EI8;
+ input P16EL;
+ output P16EO;
+ input P16ER;
+ input P16RI;
+ input P16RL;
+ output P16RO1;
+ output P16RO2;
+ output P16RO3;
+ output P16RO4;
+ output P16RO5;
+ output P16RO6;
+ output P16RO7;
+ output P16RO8;
+ input P16RR;
+ input P17CI1;
+ input P17CL;
+ output P17CO;
+ input P17CR;
+ input P17CTI;
+ output P17CTO;
+ input P17EI1;
+ input P17EI2;
+ input P17EI3;
+ input P17EI4;
+ input P17EI5;
+ input P17EI6;
+ input P17EI7;
+ input P17EI8;
+ input P17EL;
+ output P17EO;
+ input P17ER;
+ input P17RI;
+ input P17RL;
+ output P17RO1;
+ output P17RO2;
+ output P17RO3;
+ output P17RO4;
+ output P17RO5;
+ output P17RO6;
+ output P17RO7;
+ output P17RO8;
+ input P17RR;
+ input P18CI1;
+ input P18CL;
+ output P18CO;
+ input P18CR;
+ input P18CTI;
+ output P18CTO;
+ input P18EI1;
+ input P18EI2;
+ input P18EI3;
+ input P18EI4;
+ input P18EI5;
+ input P18EI6;
+ input P18EI7;
+ input P18EI8;
+ input P18EL;
+ output P18EO;
+ input P18ER;
+ input P18RI;
+ input P18RL;
+ output P18RO1;
+ output P18RO2;
+ output P18RO3;
+ output P18RO4;
+ output P18RO5;
+ output P18RO6;
+ output P18RO7;
+ output P18RO8;
+ input P18RR;
+ input P19CI1;
+ input P19CL;
+ output P19CO;
+ input P19CR;
+ input P19CTI;
+ output P19CTO;
+ input P19EI1;
+ input P19EI2;
+ input P19EI3;
+ input P19EI4;
+ input P19EI5;
+ input P19EI6;
+ input P19EI7;
+ input P19EI8;
+ input P19EL;
+ output P19EO;
+ input P19ER;
+ input P19RI;
+ input P19RL;
+ output P19RO1;
+ output P19RO2;
+ output P19RO3;
+ output P19RO4;
+ output P19RO5;
+ output P19RO6;
+ output P19RO7;
+ output P19RO8;
+ input P19RR;
+ input P1CI1;
+ input P1CL;
+ output P1CO;
+ input P1CR;
+ input P1CTI;
+ output P1CTO;
+ input P1EI1;
+ input P1EI2;
+ input P1EI3;
+ input P1EI4;
+ input P1EI5;
+ input P1EI6;
+ input P1EI7;
+ input P1EI8;
+ input P1EL;
+ output P1EO;
+ input P1ER;
+ input P1RI;
+ input P1RL;
+ output P1RO1;
+ output P1RO2;
+ output P1RO3;
+ output P1RO4;
+ output P1RO5;
+ output P1RO6;
+ output P1RO7;
+ output P1RO8;
+ input P1RR;
+ input P20CI1;
+ input P20CL;
+ output P20CO;
+ input P20CR;
+ input P20CTI;
+ output P20CTO;
+ input P20EI1;
+ input P20EI2;
+ input P20EI3;
+ input P20EI4;
+ input P20EI5;
+ input P20EI6;
+ input P20EI7;
+ input P20EI8;
+ input P20EL;
+ output P20EO;
+ input P20ER;
+ input P20RI;
+ input P20RL;
+ output P20RO1;
+ output P20RO2;
+ output P20RO3;
+ output P20RO4;
+ output P20RO5;
+ output P20RO6;
+ output P20RO7;
+ output P20RO8;
+ input P20RR;
+ input P21CI1;
+ input P21CL;
+ output P21CO;
+ input P21CR;
+ input P21CTI;
+ output P21CTO;
+ input P21EI1;
+ input P21EI2;
+ input P21EI3;
+ input P21EI4;
+ input P21EI5;
+ input P21EI6;
+ input P21EI7;
+ input P21EI8;
+ input P21EL;
+ output P21EO;
+ input P21ER;
+ input P21RI;
+ input P21RL;
+ output P21RO1;
+ output P21RO2;
+ output P21RO3;
+ output P21RO4;
+ output P21RO5;
+ output P21RO6;
+ output P21RO7;
+ output P21RO8;
+ input P21RR;
+ input P22CI1;
+ input P22CL;
+ output P22CO;
+ input P22CR;
+ input P22CTI;
+ output P22CTO;
+ input P22EI1;
+ input P22EI2;
+ input P22EI3;
+ input P22EI4;
+ input P22EI5;
+ input P22EI6;
+ input P22EI7;
+ input P22EI8;
+ input P22EL;
+ output P22EO;
+ input P22ER;
+ input P22RI;
+ input P22RL;
+ output P22RO1;
+ output P22RO2;
+ output P22RO3;
+ output P22RO4;
+ output P22RO5;
+ output P22RO6;
+ output P22RO7;
+ output P22RO8;
+ input P22RR;
+ input P23CI1;
+ input P23CL;
+ output P23CO;
+ input P23CR;
+ input P23CTI;
+ output P23CTO;
+ input P23EI1;
+ input P23EI2;
+ input P23EI3;
+ input P23EI4;
+ input P23EI5;
+ input P23EI6;
+ input P23EI7;
+ input P23EI8;
+ input P23EL;
+ output P23EO;
+ input P23ER;
+ input P23RI;
+ input P23RL;
+ output P23RO1;
+ output P23RO2;
+ output P23RO3;
+ output P23RO4;
+ output P23RO5;
+ output P23RO6;
+ output P23RO7;
+ output P23RO8;
+ input P23RR;
+ input P24CI1;
+ input P24CL;
+ output P24CO;
+ input P24CR;
+ input P24CTI;
+ output P24CTO;
+ input P24EI1;
+ input P24EI2;
+ input P24EI3;
+ input P24EI4;
+ input P24EI5;
+ input P24EI6;
+ input P24EI7;
+ input P24EI8;
+ input P24EL;
+ output P24EO;
+ input P24ER;
+ input P24RI;
+ input P24RL;
+ output P24RO1;
+ output P24RO2;
+ output P24RO3;
+ output P24RO4;
+ output P24RO5;
+ output P24RO6;
+ output P24RO7;
+ output P24RO8;
+ input P24RR;
+ input P25CI1;
+ input P25CL;
+ output P25CO;
+ input P25CR;
+ input P25CTI;
+ output P25CTO;
+ input P25EI1;
+ input P25EI2;
+ input P25EI3;
+ input P25EI4;
+ input P25EI5;
+ input P25EI6;
+ input P25EI7;
+ input P25EI8;
+ input P25EL;
+ output P25EO;
+ input P25ER;
+ input P25RI;
+ input P25RL;
+ output P25RO1;
+ output P25RO2;
+ output P25RO3;
+ output P25RO4;
+ output P25RO5;
+ output P25RO6;
+ output P25RO7;
+ output P25RO8;
+ input P25RR;
+ input P26CI1;
+ input P26CL;
+ output P26CO;
+ input P26CR;
+ input P26CTI;
+ output P26CTO;
+ input P26EI1;
+ input P26EI2;
+ input P26EI3;
+ input P26EI4;
+ input P26EI5;
+ input P26EI6;
+ input P26EI7;
+ input P26EI8;
+ input P26EL;
+ output P26EO;
+ input P26ER;
+ input P26RI;
+ input P26RL;
+ output P26RO1;
+ output P26RO2;
+ output P26RO3;
+ output P26RO4;
+ output P26RO5;
+ output P26RO6;
+ output P26RO7;
+ output P26RO8;
+ input P26RR;
+ input P27CI1;
+ input P27CL;
+ output P27CO;
+ input P27CR;
+ input P27CTI;
+ output P27CTO;
+ input P27EI1;
+ input P27EI2;
+ input P27EI3;
+ input P27EI4;
+ input P27EI5;
+ input P27EI6;
+ input P27EI7;
+ input P27EI8;
+ input P27EL;
+ output P27EO;
+ input P27ER;
+ input P27RI;
+ input P27RL;
+ output P27RO1;
+ output P27RO2;
+ output P27RO3;
+ output P27RO4;
+ output P27RO5;
+ output P27RO6;
+ output P27RO7;
+ output P27RO8;
+ input P27RR;
+ input P28CI1;
+ input P28CL;
+ output P28CO;
+ input P28CR;
+ input P28CTI;
+ output P28CTO;
+ input P28EI1;
+ input P28EI2;
+ input P28EI3;
+ input P28EI4;
+ input P28EI5;
+ input P28EI6;
+ input P28EI7;
+ input P28EI8;
+ input P28EL;
+ output P28EO;
+ input P28ER;
+ input P28RI;
+ input P28RL;
+ output P28RO1;
+ output P28RO2;
+ output P28RO3;
+ output P28RO4;
+ output P28RO5;
+ output P28RO6;
+ output P28RO7;
+ output P28RO8;
+ input P28RR;
+ input P29CI1;
+ input P29CL;
+ output P29CO;
+ input P29CR;
+ input P29CTI;
+ output P29CTO;
+ input P29EI1;
+ input P29EI2;
+ input P29EI3;
+ input P29EI4;
+ input P29EI5;
+ input P29EI6;
+ input P29EI7;
+ input P29EI8;
+ input P29EL;
+ output P29EO;
+ input P29ER;
+ input P29RI;
+ input P29RL;
+ output P29RO1;
+ output P29RO2;
+ output P29RO3;
+ output P29RO4;
+ output P29RO5;
+ output P29RO6;
+ output P29RO7;
+ output P29RO8;
+ input P29RR;
+ input P2CI1;
+ input P2CL;
+ output P2CO;
+ input P2CR;
+ input P2CTI;
+ output P2CTO;
+ input P2EI1;
+ input P2EI2;
+ input P2EI3;
+ input P2EI4;
+ input P2EI5;
+ input P2EI6;
+ input P2EI7;
+ input P2EI8;
+ input P2EL;
+ output P2EO;
+ input P2ER;
+ input P2RI;
+ input P2RL;
+ output P2RO1;
+ output P2RO2;
+ output P2RO3;
+ output P2RO4;
+ output P2RO5;
+ output P2RO6;
+ output P2RO7;
+ output P2RO8;
+ input P2RR;
+ input P30CI1;
+ input P30CL;
+ output P30CO;
+ input P30CR;
+ input P30CTI;
+ output P30CTO;
+ input P30EI1;
+ input P30EI2;
+ input P30EI3;
+ input P30EI4;
+ input P30EI5;
+ input P30EI6;
+ input P30EI7;
+ input P30EI8;
+ input P30EL;
+ output P30EO;
+ input P30ER;
+ input P30RI;
+ input P30RL;
+ output P30RO1;
+ output P30RO2;
+ output P30RO3;
+ output P30RO4;
+ output P30RO5;
+ output P30RO6;
+ output P30RO7;
+ output P30RO8;
+ input P30RR;
+ input P31CI1;
+ input P31CL;
+ output P31CO;
+ input P31CR;
+ input P31CTI;
+ output P31CTO;
+ input P31EI1;
+ input P31EI2;
+ input P31EI3;
+ input P31EI4;
+ input P31EI5;
+ input P31EI6;
+ input P31EI7;
+ input P31EI8;
+ input P31EL;
+ output P31EO;
+ input P31ER;
+ input P31RI;
+ input P31RL;
+ output P31RO1;
+ output P31RO2;
+ output P31RO3;
+ output P31RO4;
+ output P31RO5;
+ output P31RO6;
+ output P31RO7;
+ output P31RO8;
+ input P31RR;
+ input P32CI1;
+ input P32CL;
+ output P32CO;
+ input P32CR;
+ input P32CTI;
+ output P32CTO;
+ input P32EI1;
+ input P32EI2;
+ input P32EI3;
+ input P32EI4;
+ input P32EI5;
+ input P32EI6;
+ input P32EI7;
+ input P32EI8;
+ input P32EL;
+ output P32EO;
+ input P32ER;
+ input P32RI;
+ input P32RL;
+ output P32RO1;
+ output P32RO2;
+ output P32RO3;
+ output P32RO4;
+ output P32RO5;
+ output P32RO6;
+ output P32RO7;
+ output P32RO8;
+ input P32RR;
+ input P33CI1;
+ input P33CL;
+ output P33CO;
+ input P33CR;
+ input P33CTI;
+ output P33CTO;
+ input P33EI1;
+ input P33EI2;
+ input P33EI3;
+ input P33EI4;
+ input P33EI5;
+ input P33EI6;
+ input P33EI7;
+ input P33EI8;
+ input P33EL;
+ output P33EO;
+ input P33ER;
+ input P33RI;
+ input P33RL;
+ output P33RO1;
+ output P33RO2;
+ output P33RO3;
+ output P33RO4;
+ output P33RO5;
+ output P33RO6;
+ output P33RO7;
+ output P33RO8;
+ input P33RR;
+ input P34CI1;
+ input P34CL;
+ output P34CO;
+ input P34CR;
+ input P34CTI;
+ output P34CTO;
+ input P34EI1;
+ input P34EI2;
+ input P34EI3;
+ input P34EI4;
+ input P34EI5;
+ input P34EI6;
+ input P34EI7;
+ input P34EI8;
+ input P34EL;
+ output P34EO;
+ input P34ER;
+ input P34RI;
+ input P34RL;
+ output P34RO1;
+ output P34RO2;
+ output P34RO3;
+ output P34RO4;
+ output P34RO5;
+ output P34RO6;
+ output P34RO7;
+ output P34RO8;
+ input P34RR;
+ input P3CI1;
+ input P3CL;
+ output P3CO;
+ input P3CR;
+ input P3CTI;
+ output P3CTO;
+ input P3EI1;
+ input P3EI2;
+ input P3EI3;
+ input P3EI4;
+ input P3EI5;
+ input P3EI6;
+ input P3EI7;
+ input P3EI8;
+ input P3EL;
+ output P3EO;
+ input P3ER;
+ input P3RI;
+ input P3RL;
+ output P3RO1;
+ output P3RO2;
+ output P3RO3;
+ output P3RO4;
+ output P3RO5;
+ output P3RO6;
+ output P3RO7;
+ output P3RO8;
+ input P3RR;
+ input P4CI1;
+ input P4CL;
+ output P4CO;
+ input P4CR;
+ input P4CTI;
+ output P4CTO;
+ input P4EI1;
+ input P4EI2;
+ input P4EI3;
+ input P4EI4;
+ input P4EI5;
+ input P4EI6;
+ input P4EI7;
+ input P4EI8;
+ input P4EL;
+ output P4EO;
+ input P4ER;
+ input P4RI;
+ input P4RL;
+ output P4RO1;
+ output P4RO2;
+ output P4RO3;
+ output P4RO4;
+ output P4RO5;
+ output P4RO6;
+ output P4RO7;
+ output P4RO8;
+ input P4RR;
+ input P5CI1;
+ input P5CL;
+ output P5CO;
+ input P5CR;
+ input P5CTI;
+ output P5CTO;
+ input P5EI1;
+ input P5EI2;
+ input P5EI3;
+ input P5EI4;
+ input P5EI5;
+ input P5EI6;
+ input P5EI7;
+ input P5EI8;
+ input P5EL;
+ output P5EO;
+ input P5ER;
+ input P5RI;
+ input P5RL;
+ output P5RO1;
+ output P5RO2;
+ output P5RO3;
+ output P5RO4;
+ output P5RO5;
+ output P5RO6;
+ output P5RO7;
+ output P5RO8;
+ input P5RR;
+ input P6CI1;
+ input P6CL;
+ output P6CO;
+ input P6CR;
+ input P6CTI;
+ output P6CTO;
+ input P6EI1;
+ input P6EI2;
+ input P6EI3;
+ input P6EI4;
+ input P6EI5;
+ input P6EI6;
+ input P6EI7;
+ input P6EI8;
+ input P6EL;
+ output P6EO;
+ input P6ER;
+ input P6RI;
+ input P6RL;
+ output P6RO1;
+ output P6RO2;
+ output P6RO3;
+ output P6RO4;
+ output P6RO5;
+ output P6RO6;
+ output P6RO7;
+ output P6RO8;
+ input P6RR;
+ input P7CI1;
+ input P7CL;
+ output P7CO;
+ input P7CR;
+ input P7CTI;
+ output P7CTO;
+ input P7EI1;
+ input P7EI2;
+ input P7EI3;
+ input P7EI4;
+ input P7EI5;
+ input P7EI6;
+ input P7EI7;
+ input P7EI8;
+ input P7EL;
+ output P7EO;
+ input P7ER;
+ input P7RI;
+ input P7RL;
+ output P7RO1;
+ output P7RO2;
+ output P7RO3;
+ output P7RO4;
+ output P7RO5;
+ output P7RO6;
+ output P7RO7;
+ output P7RO8;
+ input P7RR;
+ input P8CI1;
+ input P8CL;
+ output P8CO;
+ input P8CR;
+ input P8CTI;
+ output P8CTO;
+ input P8EI1;
+ input P8EI2;
+ input P8EI3;
+ input P8EI4;
+ input P8EI5;
+ input P8EI6;
+ input P8EI7;
+ input P8EI8;
+ input P8EL;
+ output P8EO;
+ input P8ER;
+ input P8RI;
+ input P8RL;
+ output P8RO1;
+ output P8RO2;
+ output P8RO3;
+ output P8RO4;
+ output P8RO5;
+ output P8RO6;
+ output P8RO7;
+ output P8RO8;
+ input P8RR;
+ input P9CI1;
+ input P9CL;
+ output P9CO;
+ input P9CR;
+ input P9CTI;
+ output P9CTO;
+ input P9EI1;
+ input P9EI2;
+ input P9EI3;
+ input P9EI4;
+ input P9EI5;
+ input P9EI6;
+ input P9EI7;
+ input P9EI8;
+ input P9EL;
+ output P9EO;
+ input P9ER;
+ input P9RI;
+ input P9RL;
+ output P9RO1;
+ output P9RO2;
+ output P9RO3;
+ output P9RO4;
+ output P9RO5;
+ output P9RO6;
+ output P9RO7;
+ output P9RO8;
+ input P9RR;
+ input SE;
+ input SWRX1CK;
+ input SWRX2CK;
+ parameter cal_delay1 = "";
+ parameter cal_delay2 = "";
+ parameter div1 = 3'b000;
+ parameter div2 = 3'b000;
+ parameter div3 = 3'b000;
+ parameter div_swrx1 = 3'b000;
+ parameter div_swrx2 = 3'b000;
+ parameter inv_ld_sck1 = 1'b0;
+ parameter inv_ld_sck2 = 1'b0;
+ parameter inv_ld_sck3 = 1'b0;
+ parameter link_ld_12 = 1'b0;
+ parameter link_ld_23 = 1'b0;
+ parameter mode_side1 = 0;
+ parameter mode_side2 = 0;
+ parameter mode_side3 = 0;
+ parameter pads_dict = "";
+ parameter pads_path = "";
+ parameter sel_clk_out1 = 1'b0;
+ parameter sel_clk_out2 = 1'b0;
+ parameter sel_dc_clk = 2'b00;
+ parameter sel_ld_fck1 = 2'b00;
+ parameter sel_ld_fck2 = 2'b00;
+ parameter sel_ld_fck3 = 2'b00;
+ parameter sel_sw_fck1 = 2'b00;
+ parameter sel_sw_fck2 = 2'b00;
+ parameter use_dc = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_PMA_U(CLK_TX_I, CLK_RX_I, CLK_REF_I, DC_E_I, DC_LCSN_I1, DC_LCSN_I2, DC_LCSN_I3, DC_LCSN_I4, DC_CCSN_I, DC_WE_N_I, DC_ADD_I1, DC_ADD_I2, DC_ADD_I3, DC_ADD_I4, DC_WDATAS_I, DC_WDATA_I1, DC_WDATA_I2, DC_WDATA_I3, DC_WDATA_I4, DC_WDATA_I5, DC_WDATA_I6
+, DC_WDATA_I7, DC_WDATA_I8, DC_WDATA_I9, DC_WDATA_I10, DC_WDATA_I11, DC_WDATA_I12, PLL_RN_I, PWDN_N_I, RST_N_I, DBG_S_I1, DBG_S_I2, DBG_A_I, SE_I, SCAN_I1, SCAN_I2, SCAN_I3, SCAN_I4, SCAN_I5, SCAN_I6, SCAN_I7, SCAN_I8
+, CLK_O, CLK_RX_O, LOCK_O, LOCKA_O, FB_LOCK_O, CAL_OUT_O, DBG_R_O, LL_O1, LL_O2, LL_O3, LL_O4, LL_O5, LL_O6, LL_O7, LL_O8, LL_O9, LL_O10, LL_O11, LL_O12, LL_O13, LL_O14
+, LL_O15, LL_O16, LL_O17, LL_O18, LL_O19, LL_O20, SCAN_O1, SCAN_O2, SCAN_O3, SCAN_O4, SCAN_O5, SCAN_O6, SCAN_O7, SCAN_O8, LINK_TX1, LINK_TX2, LINK_TX3, LINK_RX0, LINK_RX1, LINK_RX2, LINK_RX3
+, LINK_TX0);
+ output CAL_OUT_O;
+ output CLK_O;
+ input CLK_REF_I;
+ input CLK_RX_I;
+ output CLK_RX_O;
+ input CLK_TX_I;
+ input DBG_A_I;
+ output DBG_R_O;
+ input DBG_S_I1;
+ input DBG_S_I2;
+ input DC_ADD_I1;
+ input DC_ADD_I2;
+ input DC_ADD_I3;
+ input DC_ADD_I4;
+ input DC_CCSN_I;
+ input DC_E_I;
+ input DC_LCSN_I1;
+ input DC_LCSN_I2;
+ input DC_LCSN_I3;
+ input DC_LCSN_I4;
+ input DC_WDATAS_I;
+ input DC_WDATA_I1;
+ input DC_WDATA_I10;
+ input DC_WDATA_I11;
+ input DC_WDATA_I12;
+ input DC_WDATA_I2;
+ input DC_WDATA_I3;
+ input DC_WDATA_I4;
+ input DC_WDATA_I5;
+ input DC_WDATA_I6;
+ input DC_WDATA_I7;
+ input DC_WDATA_I8;
+ input DC_WDATA_I9;
+ input DC_WE_N_I;
+ output FB_LOCK_O;
+ inout [9:0] LINK_RX0;
+ inout [9:0] LINK_RX1;
+ inout [9:0] LINK_RX2;
+ inout [9:0] LINK_RX3;
+ inout [19:0] LINK_TX0;
+ inout [19:0] LINK_TX1;
+ inout [19:0] LINK_TX2;
+ inout [19:0] LINK_TX3;
+ output LL_O1;
+ output LL_O10;
+ output LL_O11;
+ output LL_O12;
+ output LL_O13;
+ output LL_O14;
+ output LL_O15;
+ output LL_O16;
+ output LL_O17;
+ output LL_O18;
+ output LL_O19;
+ output LL_O2;
+ output LL_O20;
+ output LL_O3;
+ output LL_O4;
+ output LL_O5;
+ output LL_O6;
+ output LL_O7;
+ output LL_O8;
+ output LL_O9;
+ output LOCKA_O;
+ output LOCK_O;
+ input PLL_RN_I;
+ input PWDN_N_I;
+ input RST_N_I;
+ input SCAN_I1;
+ input SCAN_I2;
+ input SCAN_I3;
+ input SCAN_I4;
+ input SCAN_I5;
+ input SCAN_I6;
+ input SCAN_I7;
+ input SCAN_I8;
+ output SCAN_O1;
+ output SCAN_O2;
+ output SCAN_O3;
+ output SCAN_O4;
+ output SCAN_O5;
+ output SCAN_O6;
+ output SCAN_O7;
+ output SCAN_O8;
+ input SE_I;
+ parameter dyn_all_rx_pma_m_eye = 1'b0;
+ parameter dyn_all_rx_pma_m_eye_coarse_ena = 1'b0;
+ parameter dyn_all_rx_pma_m_eye_dn = 1'b0;
+ parameter dyn_all_rx_pma_m_eye_fine_ena = 1'b0;
+ parameter dyn_all_rx_pma_m_eye_step = 4'b0000;
+ parameter dyn_all_rx_pma_m_eye_up = 1'b0;
+ parameter dyn_all_rx_pma_threshold_1 = 5'b00000;
+ parameter dyn_all_rx_pma_threshold_2 = 5'b00000;
+ parameter dyn_all_rx_pma_trim_locked = 3'b000;
+ parameter dyn_all_rx_pma_trim_mode = 2'b00;
+ parameter dyn_all_rx_pma_trim_unlocked = 3'b000;
+ parameter dyn_rx0_pma_ctle_cap_p = 4'b0000;
+ parameter dyn_rx0_pma_ctle_res_p = 4'b0000;
+ parameter dyn_rx0_pma_dfe_idac_tap1_n = 6'b000000;
+ parameter dyn_rx0_pma_dfe_idac_tap2_n = 6'b000000;
+ parameter dyn_rx0_pma_dfe_idac_tap3_n = 6'b000000;
+ parameter dyn_rx0_pma_dfe_idac_tap4_n = 6'b000000;
+ parameter dyn_rx0_pma_termination_cmd = 6'b000000;
+ parameter dyn_rx1_pma_ctle_cap_p = 4'b0000;
+ parameter dyn_rx1_pma_ctle_res_p = 4'b0000;
+ parameter dyn_rx1_pma_dfe_idac_tap1_n = 6'b000000;
+ parameter dyn_rx1_pma_dfe_idac_tap2_n = 6'b000000;
+ parameter dyn_rx1_pma_dfe_idac_tap3_n = 6'b000000;
+ parameter dyn_rx1_pma_dfe_idac_tap4_n = 6'b000000;
+ parameter dyn_rx1_pma_termination_cmd = 6'b000000;
+ parameter dyn_rx2_pma_ctle_cap_p = 4'b0000;
+ parameter dyn_rx2_pma_ctle_res_p = 4'b0000;
+ parameter dyn_rx2_pma_dfe_idac_tap1_n = 6'b000000;
+ parameter dyn_rx2_pma_dfe_idac_tap2_n = 6'b000000;
+ parameter dyn_rx2_pma_dfe_idac_tap3_n = 6'b000000;
+ parameter dyn_rx2_pma_dfe_idac_tap4_n = 6'b000000;
+ parameter dyn_rx2_pma_termination_cmd = 6'b000000;
+ parameter dyn_rx3_pma_ctle_cap_p = 4'b0000;
+ parameter dyn_rx3_pma_ctle_res_p = 4'b0000;
+ parameter dyn_rx3_pma_dfe_idac_tap1_n = 6'b000000;
+ parameter dyn_rx3_pma_dfe_idac_tap2_n = 6'b000000;
+ parameter dyn_rx3_pma_dfe_idac_tap3_n = 6'b000000;
+ parameter dyn_rx3_pma_dfe_idac_tap4_n = 6'b000000;
+ parameter dyn_rx3_pma_termination_cmd = 6'b000000;
+ parameter dyn_tx0_pma_main_en = 6'b000000;
+ parameter dyn_tx0_pma_main_sign = 1'b0;
+ parameter dyn_tx0_pma_margin_input = 9'b000000000;
+ parameter dyn_tx0_pma_margin_sel = 9'b000000000;
+ parameter dyn_tx0_pma_post_en = 5'b00000;
+ parameter dyn_tx0_pma_post_sel = 8'b00000000;
+ parameter dyn_tx0_pma_post_sign = 1'b0;
+ parameter dyn_tx0_pma_pre_en = 1'b0;
+ parameter dyn_tx0_pma_pre_sel = 4'b0000;
+ parameter dyn_tx0_pma_pre_sign = 1'b0;
+ parameter dyn_tx1_pma_main_en = 6'b000000;
+ parameter dyn_tx1_pma_main_sign = 1'b0;
+ parameter dyn_tx1_pma_margin_input = 9'b000000000;
+ parameter dyn_tx1_pma_margin_sel = 9'b000000000;
+ parameter dyn_tx1_pma_post_en = 5'b00000;
+ parameter dyn_tx1_pma_post_sel = 8'b00000000;
+ parameter dyn_tx1_pma_post_sign = 1'b0;
+ parameter dyn_tx1_pma_pre_en = 1'b0;
+ parameter dyn_tx1_pma_pre_sel = 4'b0000;
+ parameter dyn_tx1_pma_pre_sign = 1'b0;
+ parameter dyn_tx2_pma_main_en = 6'b000000;
+ parameter dyn_tx2_pma_main_sign = 1'b0;
+ parameter dyn_tx2_pma_margin_input = 9'b000000000;
+ parameter dyn_tx2_pma_margin_sel = 9'b000000000;
+ parameter dyn_tx2_pma_post_en = 5'b00000;
+ parameter dyn_tx2_pma_post_sel = 8'b00000000;
+ parameter dyn_tx2_pma_post_sign = 1'b0;
+ parameter dyn_tx2_pma_pre_en = 1'b0;
+ parameter dyn_tx2_pma_pre_sel = 4'b0000;
+ parameter dyn_tx2_pma_pre_sign = 1'b0;
+ parameter dyn_tx3_pma_main_en = 6'b000000;
+ parameter dyn_tx3_pma_main_sign = 1'b0;
+ parameter dyn_tx3_pma_margin_input = 9'b000000000;
+ parameter dyn_tx3_pma_margin_sel = 9'b000000000;
+ parameter dyn_tx3_pma_post_en = 5'b00000;
+ parameter dyn_tx3_pma_post_sel = 8'b00000000;
+ parameter dyn_tx3_pma_post_sign = 1'b0;
+ parameter dyn_tx3_pma_pre_en = 1'b0;
+ parameter dyn_tx3_pma_pre_sel = 4'b0000;
+ parameter dyn_tx3_pma_pre_sign = 1'b0;
+ parameter location = "";
+ parameter main_clk_to_fabric_div_en = 1'b0;
+ parameter main_clk_to_fabric_div_mode = 1'b0;
+ parameter main_clk_to_fabric_sel = 1'b0;
+ parameter main_rclk_to_fabric_sel = 2'b00;
+ parameter main_use_only_usr_clock = 1'b0;
+ parameter pcs_ovs_en = 1'b0;
+ parameter pcs_ovs_mode = 1'b0;
+ parameter pcs_pll_lock_ppm = 3'b000;
+ parameter pcs_word_len = 2'b00;
+ parameter pll_pma_ckref_ext = 1'b0;
+ parameter pll_pma_cpump = 4'b0000;
+ parameter pll_pma_divl = 2'b00;
+ parameter pll_pma_divm = 1'b0;
+ parameter pll_pma_divn = 2'b00;
+ parameter pll_pma_gbx_en = 1'b0;
+ parameter pll_pma_int_data_len = 1'b0;
+ parameter pll_pma_lvds_en = 1'b0;
+ parameter pll_pma_lvds_mux = 1'b0;
+ parameter pll_pma_mux_ckref = 1'b0;
+ parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
+ parameter test_mode = 2'b00;
+ parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_FIFO_U(RCK, WCK, WE, WEA, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17
+, I18, I19, I20, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2
+, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23
+, O24, O25, O26, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, WRSTI, WAI1, WAI2, WAI3, WAI4, WAI5, WAI6, WAI7
+, WRSTO, WAO1, WAO2, WAO3, WAO4, WAO5, WAO6, WAO7, WEQ1, WEQ2, RRSTI, RAI1, RAI2, RAI3, RAI4, RAI5, RAI6, RAI7, RRSTO, RAO1, RAO2
+, RAO3, RAO4, RAO5, RAO6, RAO7, REQ1, REQ2);
+ input I1;
+ input I10;
+ input I11;
+ input I12;
+ input I13;
+ input I14;
+ input I15;
+ input I16;
+ input I17;
+ input I18;
+ input I19;
+ input I2;
+ input I20;
+ input I21;
+ input I22;
+ input I23;
+ input I24;
+ input I25;
+ input I26;
+ input I27;
+ input I28;
+ input I29;
+ input I3;
+ input I30;
+ input I31;
+ input I32;
+ input I33;
+ input I34;
+ input I35;
+ input I36;
+ input I4;
+ input I5;
+ input I6;
+ input I7;
+ input I8;
+ input I9;
+ output O1;
+ output O10;
+ output O11;
+ output O12;
+ output O13;
+ output O14;
+ output O15;
+ output O16;
+ output O17;
+ output O18;
+ output O19;
+ output O2;
+ output O20;
+ output O21;
+ output O22;
+ output O23;
+ output O24;
+ output O25;
+ output O26;
+ output O27;
+ output O28;
+ output O29;
+ output O3;
+ output O30;
+ output O31;
+ output O32;
+ output O33;
+ output O34;
+ output O35;
+ output O36;
+ output O4;
+ output O5;
+ output O6;
+ output O7;
+ output O8;
+ output O9;
+ input RAI1;
+ input RAI2;
+ input RAI3;
+ input RAI4;
+ input RAI5;
+ input RAI6;
+ input RAI7;
+ output RAO1;
+ output RAO2;
+ output RAO3;
+ output RAO4;
+ output RAO5;
+ output RAO6;
+ output RAO7;
+ input RCK;
+ output REQ1;
+ output REQ2;
+ input RRSTI;
+ output RRSTO;
+ input WAI1;
+ input WAI2;
+ input WAI3;
+ input WAI4;
+ input WAI5;
+ input WAI6;
+ input WAI7;
+ output WAO1;
+ output WAO2;
+ output WAO3;
+ output WAO4;
+ output WAO5;
+ output WAO6;
+ output WAO7;
+ input WCK;
+ input WE;
+ input WEA;
+ output WEQ1;
+ output WEQ2;
+ input WRSTI;
+ output WRSTO;
+ parameter mode = 0;
+ parameter rck_edge = 1'b0;
+ parameter read_addr_inv = 7'b0000000;
+ parameter use_read_arst = 1'b0;
+ parameter use_write_arst = 1'b0;
+ parameter wck_edge = 1'b0;
+endmodule
+
+
+(* blackbox *)
+module NX_IOM_CONTROL_U(ALCK1, ALCK2, ALCK3, LDSCK1, LDSCK2, LDSCK3, SWRX1CK, SWRX2CK, FCK1, FCK2, FDCK, CCK, DQ1CI1, DQ1CI2, DQ1CI3, DQ1CI4, DQ1CI5, DQ1CI6, DQ1CI7, DQ1CI8, DQ2CI1
+, DQ2CI2, DQ2CI3, DQ2CI4, DQ2CI5, DQ2CI6, DQ2CI7, DQ2CI8, DQ3CI1, DQ3CI2, DQ3CI3, DQ3CI4, DQ3CI5, DQ3CI6, DQ3CI7, DQ3CI8, DQS1CI1, DQS1CI2, DQS1CI3, DQS1CI4, DQS1CI5, DQS1CI6
+, DQS1CI7, DQS1CI8, DQS2CI1, DQS2CI2, DQS2CI3, DQS2CI4, DQS2CI5, DQS2CI6, DQS2CI7, DQS2CI8, DQS3CI1, DQS3CI2, DQS3CI3, DQS3CI4, DQS3CI5, DQS3CI6, DQS3CI7, DQS3CI8, LD1RN, LD2RN, LD3RN
+, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DCRN, LE, SE, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3, DRA4, DRO1CSN
+, DRO2CSN, DRO3CSN, DRI1CSN, DRI2CSN, DRI3CSN, DRDPA1CSN, DRDPA2CSN, DRDPA3CSN, DRCCSN, DRWDS, DRWEN, DRE, CA1P1, CA1P2, CA1P3, CA1P4, CA2P1, CA2P2, CA2P3, CA2P4, CA1N1
+, CA1N2, CA1N3, CA1N4, CA2N1, CA2N2, CA2N3, CA2N4, CA1T1, CA1T2, CA1T3, CA1T4, CA2T1, CA2T2, CA2T3, CA2T4, CA1D1, CA1D2, CA1D3, CA1D4, CA1D5, CA1D6
+, CA2D1, CA2D2, CA2D3, CA2D4, CA2D5, CA2D6, CKO1, CKO2, FLD, FLG, AL1D, AL2D, AL3D, AL1T, AL2T, AL3T, DCL, DRO1, DRO2, DRO3, DRO4
+, DRO5, DRO6, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16, LINK17, LINK18, LINK19, LINK20
+, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+ output AL1D;
+ output AL1T;
+ output AL2D;
+ output AL2T;
+ output AL3D;
+ output AL3T;
+ input ALCK1;
+ input ALCK2;
+ input ALCK3;
+ input CA1D1;
+ input CA1D2;
+ input CA1D3;
+ input CA1D4;
+ input CA1D5;
+ input CA1D6;
+ input CA1N1;
+ input CA1N2;
+ input CA1N3;
+ input CA1N4;
+ input CA1P1;
+ input CA1P2;
+ input CA1P3;
+ input CA1P4;
+ input CA1T1;
+ input CA1T2;
+ input CA1T3;
+ input CA1T4;
+ input CA2D1;
+ input CA2D2;
+ input CA2D3;
+ input CA2D4;
+ input CA2D5;
+ input CA2D6;
+ input CA2N1;
+ input CA2N2;
+ input CA2N3;
+ input CA2N4;
+ input CA2P1;
+ input CA2P2;
+ input CA2P3;
+ input CA2P4;
+ input CA2T1;
+ input CA2T2;
+ input CA2T3;
+ input CA2T4;
+ input CCK;
+ output CKO1;
+ output CKO2;
+ output DCL;
+ input DCRN;
+ input DQ1CI1;
+ input DQ1CI2;
+ input DQ1CI3;
+ input DQ1CI4;
+ input DQ1CI5;
+ input DQ1CI6;
+ input DQ1CI7;
+ input DQ1CI8;
+ input DQ2CI1;
+ input DQ2CI2;
+ input DQ2CI3;
+ input DQ2CI4;
+ input DQ2CI5;
+ input DQ2CI6;
+ input DQ2CI7;
+ input DQ2CI8;
+ input DQ3CI1;
+ input DQ3CI2;
+ input DQ3CI3;
+ input DQ3CI4;
+ input DQ3CI5;
+ input DQ3CI6;
+ input DQ3CI7;
+ input DQ3CI8;
+ input DQS1CI1;
+ input DQS1CI2;
+ input DQS1CI3;
+ input DQS1CI4;
+ input DQS1CI5;
+ input DQS1CI6;
+ input DQS1CI7;
+ input DQS1CI8;
+ input DQS2CI1;
+ input DQS2CI2;
+ input DQS2CI3;
+ input DQS2CI4;
+ input DQS2CI5;
+ input DQS2CI6;
+ input DQS2CI7;
+ input DQS2CI8;
+ input DQS3CI1;
+ input DQS3CI2;
+ input DQS3CI3;
+ input DQS3CI4;
+ input DQS3CI5;
+ input DQS3CI6;
+ input DQS3CI7;
+ input DQS3CI8;
+ input DRA1;
+ input DRA2;
+ input DRA3;
+ input DRA4;
+ input DRCCSN;
+ input DRDPA1CSN;
+ input DRDPA2CSN;
+ input DRDPA3CSN;
+ input DRE;
+ input DRI1;
+ input DRI1CSN;
+ input DRI2;
+ input DRI2CSN;
+ input DRI3;
+ input DRI3CSN;
+ input DRI4;
+ input DRI5;
+ input DRI6;
+ output DRO1;
+ input DRO1CSN;
+ output DRO2;
+ input DRO2CSN;
+ output DRO3;
+ input DRO3CSN;
+ output DRO4;
+ output DRO5;
+ output DRO6;
+ input DRWDS;
+ input DRWEN;
+ input FA1;
+ input FA2;
+ input FA3;
+ input FA4;
+ input FA5;
+ input FA6;
+ input FCK1;
+ input FCK2;
+ input FDCK;
+ output FLD;
+ output FLG;
+ input FZ;
+ input LD1RN;
+ input LD2RN;
+ input LD3RN;
+ input LDSCK1;
+ input LDSCK2;
+ input LDSCK3;
+ input LE;
+ inout [41:0] LINK1;
+ inout [41:0] LINK10;
+ inout [41:0] LINK11;
+ inout [41:0] LINK12;
+ inout [41:0] LINK13;
+ inout [41:0] LINK14;
+ inout [41:0] LINK15;
+ inout [41:0] LINK16;
+ inout [41:0] LINK17;
+ inout [41:0] LINK18;
+ inout [41:0] LINK19;
+ inout [41:0] LINK2;
+ inout [41:0] LINK20;
+ inout [41:0] LINK21;
+ inout [41:0] LINK22;
+ inout [41:0] LINK23;
+ inout [41:0] LINK24;
+ inout [41:0] LINK25;
+ inout [41:0] LINK26;
+ inout [41:0] LINK27;
+ inout [41:0] LINK28;
+ inout [41:0] LINK29;
+ inout [41:0] LINK3;
+ inout [41:0] LINK30;
+ inout [41:0] LINK31;
+ inout [41:0] LINK32;
+ inout [41:0] LINK33;
+ inout [41:0] LINK34;
+ inout [41:0] LINK4;
+ inout [41:0] LINK5;
+ inout [41:0] LINK6;
+ inout [41:0] LINK7;
+ inout [41:0] LINK8;
+ inout [41:0] LINK9;
+ input SE;
+ input SWRX1CK;
+ input SWRX2CK;
+ parameter cal_delay1 = "";
+ parameter cal_delay2 = "";
+ parameter div1 = 3'b000;
+ parameter div2 = 3'b000;
+ parameter div3 = 3'b000;
+ parameter div_swrx1 = 3'b000;
+ parameter div_swrx2 = 3'b000;
+ parameter inv_ld_sck1 = 1'b0;
+ parameter inv_ld_sck2 = 1'b0;
+ parameter inv_ld_sck3 = 1'b0;
+ parameter link_ld_12 = 1'b0;
+ parameter link_ld_23 = 1'b0;
+ parameter location = "";
+ parameter mode_side1 = 0;
+ parameter mode_side2 = 0;
+ parameter mode_side3 = 0;
+ parameter sel_clk_out1 = 1'b0;
+ parameter sel_clk_out2 = 1'b0;
+ parameter sel_dc_clk = 2'b00;
+ parameter sel_ld_fck1 = 2'b00;
+ parameter sel_ld_fck2 = 2'b00;
+ parameter sel_ld_fck3 = 2'b00;
+ parameter sel_sw_fck1 = 2'b00;
+ parameter sel_sw_fck2 = 2'b00;
+ parameter use_dc = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER_M(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
+, RO2, RO3, RO4, RO5, CTO, LINK);
+ input CI1;
+ input CI2;
+ input CI3;
+ input CI4;
+ input CI5;
+ input CL;
+ output CO;
+ input CR;
+ input CTI;
+ output CTO;
+ input EI1;
+ input EI2;
+ input EI3;
+ input EI4;
+ input EI5;
+ input EL;
+ output EO;
+ input ER;
+ inout [41:0] LINK;
+ input RI;
+ input RL;
+ output RO1;
+ output RO2;
+ output RO3;
+ output RO4;
+ output RO5;
+ input RR;
+ parameter chained = 1'b0;
+ parameter cpath_edge = 1'b0;
+ parameter cpath_init = 1'b0;
+ parameter cpath_inv = 1'b0;
+ parameter cpath_load = 1'b0;
+ parameter cpath_mode = 4'b0000;
+ parameter cpath_sync = 1'b0;
+ parameter epath_dynamic = 1'b0;
+ parameter epath_edge = 1'b0;
+ parameter epath_init = 1'b0;
+ parameter epath_load = 1'b0;
+ parameter epath_mode = 4'b0000;
+ parameter epath_sync = 1'b0;
+ parameter location = "";
+ parameter rpath_dynamic = 1'b0;
+ parameter rpath_edge = 1'b0;
+ parameter rpath_init = 1'b0;
+ parameter rpath_load = 1'b0;
+ parameter rpath_mode = 4'b0000;
+ parameter rpath_sync = 1'b0;
+ parameter symbol = "";
+ parameter tpath_mode = 2'b00;
+ parameter variant = "";
+endmodule
+
+(* blackbox *)
+module NX_IOM_DRIVER_U(EI1, EI2, EI3, EI4, EI5, EI6, EI7, EI8, EL, ER, CI1, CL, CR, RI, RL, RR, CO, CTI, CTO, EO, RO1
+, RO2, RO3, RO4, RO5, RO6, RO7, RO8, LINK);
+ input CI1;
+ input CL;
+ output CO;
+ input CR;
+ input CTI;
+ output CTO;
+ input EI1;
+ input EI2;
+ input EI3;
+ input EI4;
+ input EI5;
+ input EI6;
+ input EI7;
+ input EI8;
+ input EL;
+ output EO;
+ input ER;
+ inout [41:0] LINK;
+ input RI;
+ input RL;
+ output RO1;
+ output RO2;
+ output RO3;
+ output RO4;
+ output RO5;
+ output RO6;
+ output RO7;
+ output RO8;
+ input RR;
+ parameter chained = 1'b0;
+ parameter cpath_edge = 1'b0;
+ parameter cpath_init = 1'b0;
+ parameter cpath_inv = 1'b0;
+ parameter cpath_load = 1'b0;
+ parameter cpath_mode = 4'b0000;
+ parameter cpath_sync = 1'b0;
+ parameter cpath_type = 1'b0;
+ parameter epath_dynamic = 1'b0;
+ parameter epath_edge = 1'b0;
+ parameter epath_init = 1'b0;
+ parameter epath_load = 1'b0;
+ parameter epath_mode = 4'b0000;
+ parameter epath_sync = 1'b0;
+ parameter epath_type = 1'b0;
+ parameter location = "";
+ parameter rpath_dynamic = 1'b0;
+ parameter rpath_edge = 1'b0;
+ parameter rpath_init = 1'b0;
+ parameter rpath_load = 1'b0;
+ parameter rpath_mode = 4'b0000;
+ parameter rpath_sync = 1'b0;
+ parameter rpath_type = 1'b0;
+ parameter symbol = "";
+ parameter tpath_mode = 1'b0;
+endmodule
+
+(* blackbox *)
+module NX_IOM_SERDES_U(FCK, SCK, LDRN, DRWDS, DRWEN, DRE, FZ, ALD, ALT, FLD, FLG, LINK, DRA, DRI, DRO, DID, DRIN, DRDN, FA, DRON);
+ output ALD;
+ output ALT;
+ output [5:0] DID;
+ input [3:0] DRA;
+ input [2:0] DRDN;
+ input DRE;
+ input [5:0] DRI;
+ input [2:0] DRIN;
+ output [5:0] DRO;
+ input [2:0] DRON;
+ input DRWDS;
+ input DRWEN;
+ input [5:0] FA;
+ input FCK;
+ output FLD;
+ output FLG;
+ input FZ;
+ input LDRN;
+ inout [41:0] LINK;
+ input SCK;
+ parameter data_size = 5;
+ parameter location = "";
+endmodule
diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v
new file mode 100644
index 000000000..39df93ee0
--- /dev/null
+++ b/techlibs/nanoxplore/cells_map.v
@@ -0,0 +1,95 @@
+`default_nettype none
+
+module \$lut (A, Y);
+ parameter WIDTH = 0;
+ parameter LUT = 0;
+
+ (* force_downto *)
+ input [WIDTH-1:0] A;
+ output Y;
+
+ generate
+ if (WIDTH == 1) begin
+ localparam [15:0] INIT = {{2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}},
+ {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}, {2{LUT[1:0]}}};
+ NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I1(A[0]), .I2(1'b0), .I3(1'b0), .I4(1'b0));
+ end else
+ if (WIDTH == 2) begin
+ localparam [15:0] INIT = {{4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}, {4{LUT[3:0]}}};
+ NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I1(A[0]), .I2(A[1]), .I3(1'b0), .I4(1'b0), );
+ end else
+ if (WIDTH == 3) begin
+ localparam [15:0] INIT = {{8{LUT[7:0]}}, {8{LUT[7:0]}}};
+ NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(1'b0));
+ end else
+ if (WIDTH == 4) begin
+ NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+ .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(A[3]));
+ end else begin
+ wire _TECHMAP_FAIL_ = 1;
+ end
+ endgenerate
+endmodule
+
+(* techmap_celltype = "$_DFF_[NP]P[01]_" *)
+module \$_DFF_xxxx_ (input D, C, R, output Q);
+ parameter _TECHMAP_CELLTYPE_ = "";
+ localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N";
+ localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1";
+ wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+ NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
+endmodule
+
+(* techmap_celltype = "$_SDFF_[NP]P[01]_" *)
+module \$_SDFF_xxxx_ (input D, C, R, output Q);
+ parameter _TECHMAP_CELLTYPE_ = "";
+ localparam dff_edge = _TECHMAP_CELLTYPE_[3*8 +: 8] == "N";
+ localparam dff_type = _TECHMAP_CELLTYPE_[1*8 +: 8] == "1";
+ wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+ NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b0), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(R), .O(Q));
+endmodule
+
+(* techmap_celltype = "$_DFFE_[NP]P[01]P_" *)
+module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
+ parameter _TECHMAP_CELLTYPE_ = "";
+ localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N";
+ localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1";
+ wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+ NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
+endmodule
+
+(* techmap_celltype = "$_SDFFE_[NP]P[01]P_" *)
+module \$_SDFFE_xxxx_ (input D, C, R, E, output Q);
+ parameter _TECHMAP_CELLTYPE_ = "";
+ localparam dff_edge = _TECHMAP_CELLTYPE_[4*8 +: 8] == "N";
+ localparam dff_type = _TECHMAP_CELLTYPE_[2*8 +: 8] == "1";
+ wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+ NX_DFF #(.dff_ctxt(dff_type), .dff_edge(dff_edge), .dff_init(1'b1), .dff_load(1'b1), .dff_sync(1'b1), .dff_type(dff_type)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(R), .O(Q));
+endmodule
+
+module \$_DFF_P_ (input D, C, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+ NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
+endmodule
+
+module \$_DFF_N_ (input D, C, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+ NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b0), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(1'b1), .R(1'b0), .O(Q));
+endmodule
+
+module \$_DFFE_PP_ (input D, C, E, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+ NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b0), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
+endmodule
+
+module \$_DFFE_NP_ (input D, C, E, output Q);
+ parameter _TECHMAP_WIREINIT_Q_ = 1'b0;
+ wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+ NX_DFF #(.dff_ctxt(_TECHMAP_WIREINIT_Q_), .dff_edge(1'b1), .dff_init(1'b0), .dff_load(1'b1), .dff_sync(1'b0), .dff_type(1'b0)) _TECHMAP_REPLACE_ (.I(D), .CK(C), .L(E), .R(1'b0), .O(Q));
+endmodule
diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v
new file mode 100644
index 000000000..7453821d0
--- /dev/null
+++ b/techlibs/nanoxplore/cells_sim.v
@@ -0,0 +1,421 @@
+(* abc9_lut=1 *)
+module NX_LUT(input I1, I2, I3, I4, output O);
+
+parameter lut_table = 16'h0000;
+
+wire [7:0] s1 = I4 ? lut_table[15:8] : lut_table[7:0];
+wire [3:0] s2 = I3 ? s1[7:4] : s1[3:0];
+wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0];
+assign O = I1 ? s3[1] : s3[0];
+
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_DFF(input I, CK, L, R, output reg O);
+
+parameter dff_ctxt = 1'bx;
+parameter dff_edge = 1'b0;
+parameter dff_init = 1'b0;
+parameter dff_load = 1'b0;
+parameter dff_sync = 1'b0;
+parameter dff_type = 1'b0;
+
+initial begin
+ O = dff_ctxt;
+end
+
+wire clock = CK ^ dff_edge;
+wire load = dff_load ? L : 1'b1;
+wire async_reset = !dff_sync && dff_init && R;
+wire sync_reset = dff_sync && dff_init && R;
+
+always @(posedge clock, posedge async_reset)
+ if (async_reset) O <= dff_type;
+ else if (sync_reset) O <= dff_type;
+ else if (load) O <= I;
+
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_DFR(input I, CK, L, R, output O);
+
+parameter data_inv = 1'b0;
+parameter dff_edge = 1'b0;
+parameter dff_init = 1'b0;
+parameter dff_load = 1'b0;
+parameter dff_sync = 1'b0;
+parameter dff_type = 1'b0;
+parameter iobname = "";
+parameter location = "";
+parameter mode = 0;
+parameter path = 0;
+parameter ring = 0;
+
+wire clock = CK ^ dff_edge;
+wire load = dff_load ? L : 1'b1;
+wire async_reset = !dff_sync && dff_init && R;
+wire sync_reset = dff_sync && dff_init && R;
+reg O_reg;
+
+always @(posedge clock, posedge async_reset)
+ if (async_reset) O_reg <= dff_type;
+ else if (sync_reset) O_reg <= dff_type;
+ else if (load) O_reg <= I;
+
+assign O = data_inv ? O_reg : ~O_reg;
+
+endmodule
+
+
+(* abc9_box, lib_whitebox *)
+module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
+parameter add_carry = 0;
+
+wire CI_1;
+wire CO1, CO2, CO3;
+
+assign CI_1 = (add_carry==2) ? CI : ((add_carry==1) ? 1'b1 : 1'b0);
+
+assign { CO1, S1 } = A1 + B1 + CI_1;
+assign { CO2, S2 } = A2 + B2 + CO1;
+assign { CO3, S3 } = A3 + B3 + CO2;
+assign { CO, S4 } = A4 + B4 + CO3;
+
+endmodule
+
+module NX_IOB(I, C, T, O, IO);
+ input C;
+ input I;
+ (* iopad_external_pin *)
+ inout IO;
+ output O;
+ input T;
+ parameter differential = "";
+ parameter drive = "";
+ parameter dynDrive = "";
+ parameter dynInput = "";
+ parameter dynTerm = "";
+ parameter extra = 3;
+ parameter inputDelayLine = "";
+ parameter inputDelayOn = "";
+ parameter inputSignalSlope = "";
+ parameter location = "";
+ parameter locked = 1'b0;
+ parameter outputCapacity = "";
+ parameter outputDelayLine = "";
+ parameter outputDelayOn = "";
+ parameter slewRate = "";
+ parameter standard = "";
+ parameter termination = "";
+ parameter terminationReference = "";
+ parameter turbo = "";
+ parameter weakTermination = "";
+
+ assign O = IO;
+ assign IO = C ? I : 1'bz;
+endmodule
+
+module NX_IOB_I(C, T, IO, O);
+ input C;
+ (* iopad_external_pin *)
+ input IO;
+ output O;
+ input T;
+ parameter differential = "";
+ parameter drive = "";
+ parameter dynDrive = "";
+ parameter dynInput = "";
+ parameter dynTerm = "";
+ parameter extra = 1;
+ parameter inputDelayLine = "";
+ parameter inputDelayOn = "";
+ parameter inputSignalSlope = "";
+ parameter location = "";
+ parameter locked = 1'b0;
+ parameter outputCapacity = "";
+ parameter outputDelayLine = "";
+ parameter outputDelayOn = "";
+ parameter slewRate = "";
+ parameter standard = "";
+ parameter termination = "";
+ parameter terminationReference = "";
+ parameter turbo = "";
+ parameter weakTermination = "";
+
+ assign O = IO;
+endmodule
+
+module NX_IOB_O(I, C, T, IO);
+ input C;
+ input I;
+ (* iopad_external_pin *)
+ output IO;
+ input T;
+ parameter differential = "";
+ parameter drive = "";
+ parameter dynDrive = "";
+ parameter dynInput = "";
+ parameter dynTerm = "";
+ parameter extra = 2;
+ parameter inputDelayLine = "";
+ parameter inputDelayOn = "";
+ parameter inputSignalSlope = "";
+ parameter location = "";
+ parameter locked = 1'b0;
+ parameter outputCapacity = "";
+ parameter outputDelayLine = "";
+ parameter outputDelayOn = "";
+ parameter slewRate = "";
+ parameter standard = "";
+ parameter termination = "";
+ parameter terminationReference = "";
+ parameter turbo = "";
+ parameter weakTermination = "";
+
+ assign IO = C ? I : 1'bz;
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_CY_1BIT(CI, A, B, S, CO);
+ (* abc9_carry *)
+ input CI;
+ input A;
+ input B;
+ output S;
+ (* abc9_carry *)
+ output CO;
+ parameter first = 1'b0;
+
+ assign {CO, S} = A + B + CI;
+endmodule
+
+module NX_BD(I, O);
+ input I;
+ output O;
+ parameter mode = "global_lowskew";
+
+ assign O = I;
+endmodule
+
+module NX_BFF(I, O);
+ input I;
+ output O;
+
+ assign O = I;
+endmodule
+
+module NX_BFR(I, O);
+ input I;
+ output O;
+ parameter data_inv = 1'b0;
+ parameter iobname = "";
+ parameter location = "";
+ parameter mode = 0;
+ parameter path = 0;
+ parameter ring = 0;
+
+ assign O = data_inv ? ~I : I;
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13
+, AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10
+, BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3
+, AO4, AO5, AO6, AO7, AO8, AO9, AO10, AO11, AO12, AO13, AO14, AO15, AO16, AO17, AO18, AO19, AO20, AO21, AO22, AO23, AO24
+, BO1, BO2, BO3, BO4, BO5, BO6, BO7, BO8, BO9, BO10, BO11, BO12, BO13, BO14, BO15, BO16, BO17, BO18, BO19, BO20, BO21
+, BO22, BO23, BO24, AA1, AA2, AA3, AA4, AA5, AA6, AA7, AA8, AA9, AA10, AA11, AA12, AA13, AA14, AA15, AA16, ACS, AWE
+, AR, BA1, BA2, BA3, BA4, BA5, BA6, BA7, BA8, BA9, BA10, BA11, BA12, BA13, BA14, BA15, BA16, BCS, BWE, BR);
+ input AA1;
+ input AA10;
+ input AA11;
+ input AA12;
+ input AA13;
+ input AA14;
+ input AA15;
+ input AA16;
+ input AA2;
+ input AA3;
+ input AA4;
+ input AA5;
+ input AA6;
+ input AA7;
+ input AA8;
+ input AA9;
+ input ACK;
+ input ACKC;
+ input ACKD;
+ input ACKR;
+ output ACOR;
+ input ACS;
+ output AERR;
+ input AI1;
+ input AI10;
+ input AI11;
+ input AI12;
+ input AI13;
+ input AI14;
+ input AI15;
+ input AI16;
+ input AI17;
+ input AI18;
+ input AI19;
+ input AI2;
+ input AI20;
+ input AI21;
+ input AI22;
+ input AI23;
+ input AI24;
+ input AI3;
+ input AI4;
+ input AI5;
+ input AI6;
+ input AI7;
+ input AI8;
+ input AI9;
+ output reg AO1;
+ output reg AO10;
+ output reg AO11;
+ output reg AO12;
+ output reg AO13;
+ output reg AO14;
+ output reg AO15;
+ output reg AO16;
+ output reg AO17;
+ output reg AO18;
+ output reg AO19;
+ output reg AO2;
+ output reg AO20;
+ output reg AO21;
+ output reg AO22;
+ output reg AO23;
+ output reg AO24;
+ output reg AO3;
+ output reg AO4;
+ output reg AO5;
+ output reg AO6;
+ output reg AO7;
+ output reg AO8;
+ output reg AO9;
+ input AR;
+ input AWE;
+ input BA1;
+ input BA10;
+ input BA11;
+ input BA12;
+ input BA13;
+ input BA14;
+ input BA15;
+ input BA16;
+ input BA2;
+ input BA3;
+ input BA4;
+ input BA5;
+ input BA6;
+ input BA7;
+ input BA8;
+ input BA9;
+ input BCK;
+ input BCKC;
+ input BCKD;
+ input BCKR;
+ output BCOR;
+ input BCS;
+ output BERR;
+ input BI1;
+ input BI10;
+ input BI11;
+ input BI12;
+ input BI13;
+ input BI14;
+ input BI15;
+ input BI16;
+ input BI17;
+ input BI18;
+ input BI19;
+ input BI2;
+ input BI20;
+ input BI21;
+ input BI22;
+ input BI23;
+ input BI24;
+ input BI3;
+ input BI4;
+ input BI5;
+ input BI6;
+ input BI7;
+ input BI8;
+ input BI9;
+ output reg BO1;
+ output reg BO10;
+ output reg BO11;
+ output reg BO12;
+ output reg BO13;
+ output reg BO14;
+ output reg BO15;
+ output reg BO16;
+ output reg BO17;
+ output reg BO18;
+ output reg BO19;
+ output reg BO2;
+ output reg BO20;
+ output reg BO21;
+ output reg BO22;
+ output reg BO23;
+ output reg BO24;
+ output reg BO3;
+ output reg BO4;
+ output reg BO5;
+ output reg BO6;
+ output reg BO7;
+ output reg BO8;
+ output reg BO9;
+ input BR;
+ input BWE;
+ parameter mcka_edge = 1'b0;
+ parameter mckb_edge = 1'b0;
+ parameter mem_ctxt = "";
+ parameter pcka_edge = 1'b0;
+ parameter pckb_edge = 1'b0;
+ parameter pipe_ia = 1'b0;
+ parameter pipe_ib = 1'b0;
+ parameter pipe_oa = 1'b0;
+ parameter pipe_ob = 1'b0;
+ parameter raw_config0 = 4'b0000;
+ parameter raw_config1 = 16'b0000000000000000;
+ //parameter raw_l_enable = 1'b0;
+ //parameter raw_l_extend = 4'b0000;
+ //parameter raw_u_enable = 1'b0;
+ //parameter raw_u_extend = 8'b00000000;
+ parameter std_mode = "";
+
+ reg [24-1:0] mem [2048-1:0]; // 48 Kbit of memory
+
+ /*integer i;
+ initial begin
+ for (i = 0; i < 2048; i = i + 1)
+ mem[i] = 24'b0;
+ end*/
+
+ wire [15:0] AA = { AA16, AA15, AA14, AA13, AA12, AA11, AA10, AA9, AA8, AA7, AA6, AA5, AA4, AA3, AA2, AA1 };
+ wire [23:0] AI = { AI24, AI23, AI22, AI21, AI20, AI19, AI18, AI17, AI16, AI15, AI14, AI13, AI12, AI11, AI10, AI9, AI8, AI7, AI6, AI5, AI4, AI3, AI2, AI1 };
+ wire [23:0] AO = { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 };
+ wire [15:0] BA = { BA16, BA15, BA14, BA13, BA12, BA11, BA10, BA9, BA8, BA7, BA6, BA5, BA4, BA3, BA2, BA1 };
+ wire [23:0] BI = { BI24, BI23, BI22, BI21, BI20, BI19, BI18, BI17, BI16, BI15, BI14, BI13, BI12, BI11, BI10, BI9, BI8, BI7, BI6, BI5, BI4, BI3, BI2, BI1 };
+ wire [23:0] BO = { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 };
+
+ always @(posedge ACK)
+ if (AWE)
+ mem[AA[10:0]] <= AI;
+ else
+ { AO24, AO23, AO22, AO21, AO20, AO19, AO18, AO17, AO16, AO15, AO14, AO13, AO12, AO11, AO10, AO9, AO8, AO7, AO6, AO5, AO4, AO3, AO2, AO1 } <= mem[AA[10:0]];
+ assign ACOR = 1'b0;
+ assign AERR = 1'b0;
+
+ always @(posedge BCK)
+ if (BWE)
+ mem[BA[10:0]] <= BI;
+ else
+ { BO24, BO23, BO22, BO21, BO20, BO19, BO18, BO17, BO16, BO15, BO14, BO13, BO12, BO11, BO10, BO9, BO8, BO7, BO6, BO5, BO4, BO3, BO2, BO1 } <= mem[BA[10:0]];
+ assign BCOR = 1'b0;
+ assign BERR = 1'b0;
+endmodule
diff --git a/techlibs/nanoxplore/cells_sim_l.v b/techlibs/nanoxplore/cells_sim_l.v
new file mode 100644
index 000000000..e69de29bb
diff --git a/techlibs/nanoxplore/cells_sim_m.v b/techlibs/nanoxplore/cells_sim_m.v
new file mode 100644
index 000000000..e69de29bb
diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
new file mode 100644
index 000000000..e11aaabee
--- /dev/null
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -0,0 +1,306 @@
+(* abc9_box, lib_whitebox *)
+module NX_GCK_U(SI1, SI2, CMD, SO);
+ input CMD;
+ input SI1;
+ input SI2;
+ output SO;
+ parameter inv_in = 1'b0;
+ parameter inv_out = 1'b0;
+ parameter std_mode = "BYPASS";
+
+ wire SI1_int = inv_in ? ~SI1 : SI1;
+ wire SI2_int = inv_in ? ~SI2 : SI2;
+
+ wire SO_int;
+ generate
+ if (std_mode == "BYPASS") begin
+ assign SO_int = SI1_int;
+ end
+ else if (std_mode == "MUX") begin
+ assign SO_int = CMD ? SI1_int : SI2_int;
+ end
+ else if (std_mode == "CKS") begin
+ assign SO_int = CMD ? SI1_int : 1'b0;
+ end
+ else if (std_mode == "CSC") begin
+ assign SO_int = CMD;
+ end
+ else
+ $error("Unrecognised std_mode");
+ endgenerate
+ assign SO = inv_out ? ~SO_int : SO_int;
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20
+, I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5
+, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26
+, O27, O28, O29, O30, O31, O32, O33, O34, O35, O36, RA1, RA2, RA3, RA4, RA5, RA6, RA7, RA8, RA9, RA10, WA1
+, WA2, WA3, WA4, WA5, WA6, WE, WEA);
+ input I1;
+ input I10;
+ input I11;
+ input I12;
+ input I13;
+ input I14;
+ input I15;
+ input I16;
+ input I17;
+ input I18;
+ input I19;
+ input I2;
+ input I20;
+ input I21;
+ input I22;
+ input I23;
+ input I24;
+ input I25;
+ input I26;
+ input I27;
+ input I28;
+ input I29;
+ input I3;
+ input I30;
+ input I31;
+ input I32;
+ input I33;
+ input I34;
+ input I35;
+ input I36;
+ input I4;
+ input I5;
+ input I6;
+ input I7;
+ input I8;
+ input I9;
+ output O1;
+ output O10;
+ output O11;
+ output O12;
+ output O13;
+ output O14;
+ output O15;
+ output O16;
+ output O17;
+ output O18;
+ output O19;
+ output O2;
+ output O20;
+ output O21;
+ output O22;
+ output O23;
+ output O24;
+ output O25;
+ output O26;
+ output O27;
+ output O28;
+ output O29;
+ output O3;
+ output O30;
+ output O31;
+ output O32;
+ output O33;
+ output O34;
+ output O35;
+ output O36;
+ output O4;
+ output O5;
+ output O6;
+ output O7;
+ output O8;
+ output O9;
+ input RA1;
+ input RA10;
+ input RA2;
+ input RA3;
+ input RA4;
+ input RA5;
+ input RA6;
+ input RA7;
+ input RA8;
+ input RA9;
+ input WA1;
+ input WA2;
+ input WA3;
+ input WA4;
+ input WA5;
+ input WA6;
+ input WCK;
+ input WE;
+ input WEA;
+ parameter mem_ctxt = "";
+ parameter mode = 0;
+ parameter wck_edge = 1'b0;
+
+ wire clock = WCK ^ wck_edge;
+
+ localparam MEM_SIZE = mode == 2 ? 64 : 32;
+ localparam MEM_WIDTH = mode == 3 ? 36 : 18;
+ localparam ADDR_WIDTH = mode == 2 ? 6 : 5;
+ localparam DATA_SIZE = MEM_SIZE * MEM_WIDTH;
+ localparam MAX_SIZE = DATA_SIZE + MEM_SIZE + 1;
+
+ reg [MEM_WIDTH-1:0] mem [MEM_SIZE-1:0];
+
+ function [DATA_SIZE-1:0] convert_initval;
+ input [8*MAX_SIZE-1:0] hex_initval;
+ reg done;
+ reg [DATA_SIZE-1:0] temp;
+ reg [7:0] char;
+ integer i,j;
+ begin
+ done = 1'b0;
+ temp = 0;
+ j = 0;
+ for (i = 0; i < MAX_SIZE; i = i + 1) begin
+ char = hex_initval[8*i +: 8];
+ if (char >= "0" && char <= "1") begin
+ temp[j] = char - "0";
+ j = j + 1;
+ end
+ end
+ convert_initval = temp;
+ end
+ endfunction
+
+ integer i;
+ reg [DATA_SIZE-1:0] mem_data;
+ initial begin
+ mem_data = convert_initval(mem_ctxt);
+ for (i = 0; i < MEM_SIZE; i = i + 1)
+ mem[i] = mem_data[MEM_WIDTH*(MEM_SIZE-i-1) +: MEM_WIDTH];
+ end
+
+ wire [ADDR_WIDTH-1:0] WA = (mode==2) ? { WA6, WA5, WA4, WA3, WA2, WA1 } : { WA5, WA4, WA3, WA2, WA1 };
+ wire [36-1:0] O = { O36, O35, O34, O33, O32, O31, O30, O29, O28,
+ O27, O26, O25, O24, O23, O22, O21, O20, O19,
+ O18, O17, O16, O15, O14, O13, O12, O11, O10,
+ O9, O8, O7, O6, O5, O4, O3, O2, O1 };
+ wire [36-1:0] I = { I36, I35, I34, I33, I32, I31, I30, I29, I28,
+ I27, I26, I25, I24, I23, I22, I21, I20, I19,
+ I18, I17, I16, I15, I14, I13, I12, I11, I10,
+ I9, I8, I7, I6, I5, I4, I3, I2, I1 };
+ generate
+ if (mode==0) begin
+ assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];
+ end
+ else if (mode==1) begin
+ assign O = mem[{ WA5, WA4, WA3, WA2, WA1 }];
+ end
+ else if (mode==2) begin
+ assign O = mem[{ RA6, RA5, RA4, RA3, RA2, RA1 }];
+ end
+ else if (mode==3) begin
+ assign O = mem[{ RA5, RA4, RA3, RA2, RA1 }];
+ end
+ else if (mode==4) begin
+ assign O = { mem[{ RA10, RA9, RA8, RA7, RA6 }], mem[{ RA5, RA4, RA3, RA2, RA1 }] };
+ end
+ else
+ $error("Unknown NX_RFB_U mode");
+ endgenerate
+
+ always @(posedge clock)
+ if (WE)
+ mem[WA] <= I[MEM_WIDTH-1:0];
+endmodule
+
+(* abc9_box, lib_whitebox *)
+module NX_WFG_U(R, SI, ZI, SO, ZO);
+ input R;
+ input SI;
+ output SO;
+ input ZI;
+ output ZO;
+ parameter delay = 0;
+ parameter delay_on = 1'b0;
+ parameter div_phase = 1'b0;
+ parameter div_ratio = 0;
+ parameter location = "";
+ parameter mode = 0;
+ parameter pattern = 16'b0000000000000000;
+ parameter pattern_end = 0;
+ parameter reset_on_cal_lock_n = 1'b0;
+ parameter reset_on_pll_lock_n = 1'b0;
+ parameter reset_on_pll_locka_n = 1'b0;
+ parameter wfg_edge = 1'b0;
+
+ generate
+ if (mode==0) begin
+ assign SO = SI;
+ end
+ else if (mode==1) begin
+ wire clock = ZI ^ wfg_edge;
+ wire reset = R || SI;
+ reg [3:0] counter = 0;
+ reg [15:0] rom = pattern;
+
+ always @(posedge clock)
+ begin
+ if (reset)
+ counter <= 4'b0;
+ else
+ counter <= counter + 1;
+ end
+ assign SO = counter == pattern_end;
+ assign ZO = rom[counter];
+ end
+ else if (mode==2) begin
+ end
+ else
+ $error("Unknown NX_WFG_U mode");
+ endgenerate
+endmodule
+
+module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2);
+ input CK;
+ input CKF;
+ input R;
+ input I;
+ input I2;
+ input L;
+ output O;
+ output O2;
+
+ parameter location = "";
+ parameter path = 0;
+ parameter dff_type = 1'b0;
+ parameter dff_sync = 1'b0;
+ parameter dff_load = 1'b0;
+
+ wire load = dff_load ? 1'b1 : L; // reversed when compared to DFF
+ wire async_reset = !dff_sync && R;
+ wire sync_reset = dff_sync && R;
+
+ generate
+ if (path==1) begin
+ // IDDFR
+ always @(posedge CK, posedge async_reset)
+ if (async_reset) O <= dff_type;
+ else if (sync_reset) O <= dff_type;
+ else if (load) O <= I;
+
+ always @(posedge CKF, posedge async_reset)
+ if (async_reset) O2 <= dff_type;
+ else if (sync_reset) O2 <= dff_type;
+ else if (load) O2 <= I;
+ end
+ else if (path==0 || path==2) begin
+ reg q1, q2;
+ // ODDFR
+ always @(posedge CK, posedge async_reset)
+ if (async_reset) q1 <= dff_type;
+ else if (sync_reset) q1 <= dff_type;
+ else if (load) q1 <= I;
+
+ always @(posedge CKF, posedge async_reset)
+ if (async_reset) q2 <= dff_type;
+ else if (sync_reset) q2 <= dff_type;
+ else if (load) q2 <= I2;
+
+ assign O = CK ? q1 : q2;
+ end
+ else
+ $error("Unknown NX_DDFR_U path");
+ endgenerate
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap.v b/techlibs/nanoxplore/cells_wrap.v
new file mode 100644
index 000000000..aa328c4c6
--- /dev/null
+++ b/techlibs/nanoxplore/cells_wrap.v
@@ -0,0 +1,201 @@
+module NX_RAM_WRAP(ACK, ACKD, ACKR, BCK, BCKD, BCKR, ACOR, AERR, BCOR, BERR, ACS, AWE, AR, BCS, BWE, BR, BI, AO, BO, AI, AA
+, BA);
+ input [15:0] AA;
+ input ACK;
+ input ACKD;
+ input ACKR;
+ output ACOR;
+ input ACS;
+ output AERR;
+ input [23:0] AI;
+ output [23:0] AO;
+ input AR;
+ input AWE;
+ input [15:0] BA;
+ input BCK;
+ input BCKD;
+ input BCKR;
+ output BCOR;
+ input BCS;
+ output BERR;
+ input [23:0] BI;
+ output [23:0] BO;
+ input BR;
+ input BWE;
+ parameter mcka_edge = 1'b0;
+ parameter mckb_edge = 1'b0;
+ parameter mem_ctxt = "";
+ parameter pcka_edge = 1'b0;
+ parameter pckb_edge = 1'b0;
+ parameter pipe_ia = 1'b0;
+ parameter pipe_ib = 1'b0;
+ parameter pipe_oa = 1'b0;
+ parameter pipe_ob = 1'b0;
+ parameter raw_config0 = 4'b0000;
+ parameter raw_config1 = 16'b0000000000000000;
+ parameter std_mode = "";
+
+ NX_RAM #(
+ .mcka_edge(mcka_edge),
+ .mckb_edge(mckb_edge),
+ .mem_ctxt(mem_ctxt),
+ .pcka_edge(pcka_edge),
+ .pckb_edge(pckb_edge),
+ .pipe_ia(pipe_ia),
+ .pipe_ib(pipe_ib),
+ .pipe_oa(pipe_oa),
+ .pipe_ob(pipe_ob),
+ .raw_config0(raw_config0),
+ .raw_config1(raw_config1),
+ .std_mode(std_mode)
+ ) ram (
+ .AA1(AA[0]),
+ .AA10(AA[9]),
+ .AA11(AA[10]),
+ .AA12(AA[11]),
+ .AA13(AA[12]),
+ .AA14(AA[13]),
+ .AA15(AA[14]),
+ .AA16(AA[15]),
+ .AA2(AA[1]),
+ .AA3(AA[2]),
+ .AA4(AA[3]),
+ .AA5(AA[4]),
+ .AA6(AA[5]),
+ .AA7(AA[6]),
+ .AA8(AA[7]),
+ .AA9(AA[8]),
+ .ACK(ACK),
+ .ACKC(ACK),
+ .ACKD(ACKD),
+ .ACKR(ACKR),
+ .ACOR(ACOR),
+ .ACS(ACS),
+ .AERR(AERR),
+ .AI1(AI[0]),
+ .AI10(AI[9]),
+ .AI11(AI[10]),
+ .AI12(AI[11]),
+ .AI13(AI[12]),
+ .AI14(AI[13]),
+ .AI15(AI[14]),
+ .AI16(AI[15]),
+ .AI17(AI[16]),
+ .AI18(AI[17]),
+ .AI19(AI[18]),
+ .AI2(AI[1]),
+ .AI20(AI[19]),
+ .AI21(AI[20]),
+ .AI22(AI[21]),
+ .AI23(AI[22]),
+ .AI24(AI[23]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AI7(AI[6]),
+ .AI8(AI[7]),
+ .AI9(AI[8]),
+ .AO1(AO[0]),
+ .AO10(AO[9]),
+ .AO11(AO[10]),
+ .AO12(AO[11]),
+ .AO13(AO[12]),
+ .AO14(AO[13]),
+ .AO15(AO[14]),
+ .AO16(AO[15]),
+ .AO17(AO[16]),
+ .AO18(AO[17]),
+ .AO19(AO[18]),
+ .AO2(AO[1]),
+ .AO20(AO[19]),
+ .AO21(AO[20]),
+ .AO22(AO[21]),
+ .AO23(AO[22]),
+ .AO24(AO[23]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .AO7(AO[6]),
+ .AO8(AO[7]),
+ .AO9(AO[8]),
+ .AR(AR),
+ .AWE(AWE),
+ .BA1(BA[0]),
+ .BA10(BA[9]),
+ .BA11(BA[10]),
+ .BA12(BA[11]),
+ .BA13(BA[12]),
+ .BA14(BA[13]),
+ .BA15(BA[14]),
+ .BA16(BA[15]),
+ .BA2(BA[1]),
+ .BA3(BA[2]),
+ .BA4(BA[3]),
+ .BA5(BA[4]),
+ .BA6(BA[5]),
+ .BA7(BA[6]),
+ .BA8(BA[7]),
+ .BA9(BA[8]),
+ .BCK(BCK),
+ .BCKC(BCK),
+ .BCKD(BCKD),
+ .BCKR(BCKR),
+ .BCOR(BCOR),
+ .BCS(BCS),
+ .BERR(BERR),
+ .BI1(BI[0]),
+ .BI10(BI[9]),
+ .BI11(BI[10]),
+ .BI12(BI[11]),
+ .BI13(BI[12]),
+ .BI14(BI[13]),
+ .BI15(BI[14]),
+ .BI16(BI[15]),
+ .BI17(BI[16]),
+ .BI18(BI[17]),
+ .BI19(BI[18]),
+ .BI2(BI[1]),
+ .BI20(BI[19]),
+ .BI21(BI[20]),
+ .BI22(BI[21]),
+ .BI23(BI[22]),
+ .BI24(BI[23]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BI7(BI[6]),
+ .BI8(BI[7]),
+ .BI9(BI[8]),
+ .BO1(BO[0]),
+ .BO10(BO[9]),
+ .BO11(BO[10]),
+ .BO12(BO[11]),
+ .BO13(BO[12]),
+ .BO14(BO[13]),
+ .BO15(BO[14]),
+ .BO16(BO[15]),
+ .BO17(BO[16]),
+ .BO18(BO[17]),
+ .BO19(BO[18]),
+ .BO2(BO[1]),
+ .BO20(BO[19]),
+ .BO21(BO[20]),
+ .BO22(BO[21]),
+ .BO23(BO[22]),
+ .BO24(BO[23]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .BO7(BO[6]),
+ .BO8(BO[7]),
+ .BO9(BO[8]),
+ .BR(BR),
+ .BWE(BWE)
+ );
+
+endmodule
+
diff --git a/techlibs/nanoxplore/cells_wrap_l.v b/techlibs/nanoxplore/cells_wrap_l.v
new file mode 100644
index 000000000..5bfdd4d13
--- /dev/null
+++ b/techlibs/nanoxplore/cells_wrap_l.v
@@ -0,0 +1,1713 @@
+module NX_CDC_L_2DFF(CK1, CK2, ADRSTI, BDRSTI, BI, AO, BO, AI);
+ input ADRSTI;
+ input [5:0] AI;
+ output [5:0] AO;
+ input BDRSTI;
+ input [5:0] BI;
+ output [5:0] BO;
+ input CK1;
+ input CK2;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter gt0_bypass_reg1 = 1'b0;
+ parameter gt0_bypass_reg2 = 1'b0;
+ parameter gt1_bypass_reg1 = 1'b0;
+ parameter gt1_bypass_reg2 = 1'b0;
+ parameter use_adest_arst = 2'b00;
+ parameter use_bdest_arst = 2'b00;
+
+ NX_CDC_L #(
+ .mode(0), // -- 0: 2DFF
+ .ck0_edge(ck0_edge),
+ .ck1_edge(ck1_edge),
+ .ack_sel(ack_sel),
+ .bck_sel(bck_sel),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(2'b00),
+ .use_adest_arst(use_adest_arst),
+ .use_bsrc_arst(2'b00),
+ .use_bdest_arst(use_bdest_arst),
+ .use_csrc_arst(2'b00),
+ .use_cdest_arst(2'b00),
+ .use_dsrc_arst(2'b00),
+ .use_ddest_arst(2'b00),
+ .gt0_bypass_reg1(gt0_bypass_reg1),
+ .gt0_bypass_reg2(gt0_bypass_reg2),
+ .gt1_bypass_reg1(gt1_bypass_reg2),
+ .gt1_bypass_reg2(gt1_bypass_reg2),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(CK1),
+ .CK2(CK2),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0)
+ );
+endmodule
+
+module NX_CDC_L_3DFF(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);
+ input ADRSTI;
+ input [5:0] AI;
+ output [5:0] AO;
+ input ASRSTI;
+ input BDRSTI;
+ input [5:0] BI;
+ output [5:0] BO;
+ input BSRSTI;
+ input CK1;
+ input CK2;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter gt0_bypass_reg1 = 1'b0;
+ parameter gt0_bypass_reg2 = 1'b0;
+ parameter gt1_bypass_reg1 = 1'b0;
+ parameter gt1_bypass_reg2 = 1'b0;
+ parameter use_adest_arst = 2'b00;
+ parameter use_asrc_arst = 2'b00;
+ parameter use_bdest_arst = 2'b00;
+ parameter use_bsrc_arst = 2'b00;
+
+ NX_CDC_L #(
+ .mode(1), // -- 1: 3DFF
+ .ck0_edge(ck0_edge),
+ .ck1_edge(ck1_edge),
+ .ack_sel(ack_sel),
+ .bck_sel(bck_sel),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(use_asrc_arst),
+ .use_adest_arst(use_adest_arst),
+ .use_bsrc_arst(use_bsrc_arst),
+ .use_bdest_arst(use_bdest_arst),
+ .use_csrc_arst(2'b00),
+ .use_cdest_arst(2'b00),
+ .use_dsrc_arst(2'b00),
+ .use_ddest_arst(2'b00),
+ .gt0_bypass_reg1(gt0_bypass_reg1),
+ .gt0_bypass_reg2(gt0_bypass_reg2),
+ .gt1_bypass_reg1(gt1_bypass_reg2),
+ .gt1_bypass_reg2(gt1_bypass_reg2),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(CK1),
+ .CK2(CK2),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0)
+ );
+endmodule
+
+module NX_CDC_L_FULL(CK1, CK2, ASRSTI, ADRSTI, BDRSTI, BSRSTI, BI, AO, BO, AI);
+ input ADRSTI;
+ input [5:0] AI;
+ output [5:0] AO;
+ input ASRSTI;
+ input BDRSTI;
+ input [5:0] BI;
+ output [5:0] BO;
+ input BSRSTI;
+ input CK1;
+ input CK2;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter gt0_bypass_reg1 = 1'b0;
+ parameter gt0_bypass_reg2 = 1'b0;
+ parameter gt1_bypass_reg1 = 1'b0;
+ parameter gt1_bypass_reg2 = 1'b0;
+ parameter use_adest_arst = 2'b00;
+ parameter use_asrc_arst = 2'b00;
+ parameter use_bdest_arst = 2'b00;
+ parameter use_bsrc_arst = 2'b00;
+
+ NX_CDC_L #(
+ .mode(2), // -- 2: B2G_3DFF_G2B
+ .ck0_edge(ck0_edge),
+ .ck1_edge(ck1_edge),
+ .ack_sel(ack_sel),
+ .bck_sel(bck_sel),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(use_asrc_arst),
+ .use_adest_arst(use_adest_arst),
+ .use_bsrc_arst(use_bsrc_arst),
+ .use_bdest_arst(use_bdest_arst),
+ .use_csrc_arst(2'b00),
+ .use_cdest_arst(2'b00),
+ .use_dsrc_arst(2'b00),
+ .use_ddest_arst(2'b00),
+ .gt0_bypass_reg1(gt0_bypass_reg1),
+ .gt0_bypass_reg2(gt0_bypass_reg2),
+ .gt1_bypass_reg1(gt1_bypass_reg2),
+ .gt1_bypass_reg2(gt1_bypass_reg2),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(CK1),
+ .CK2(CK2),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0)
+ );
+endmodule
+
+module NX_CDC_L_BIN2GRAY(CK1, CK2, BI, AO, BO, AI);
+ input [5:0] AI;
+ output [5:0] AO;
+ input [5:0] BI;
+ output [5:0] BO;
+ input CK1;
+ input CK2;
+
+ NX_CDC_L #(
+ .mode(3), // -- 3: bin2gray
+ .ck0_edge(1'b0),
+ .ck1_edge(1'b0),
+ .ack_sel(1'b0),
+ .bck_sel(1'b0),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(2'b00),
+ .use_adest_arst(2'b00),
+ .use_bsrc_arst(2'b00),
+ .use_bdest_arst(2'b00),
+ .use_csrc_arst(2'b00),
+ .use_cdest_arst(2'b00),
+ .use_dsrc_arst(2'b00),
+ .use_ddest_arst(2'b00),
+ .gt0_bypass_reg1(1'b0),
+ .gt0_bypass_reg2(1'b0),
+ .gt1_bypass_reg1(1'b0),
+ .gt1_bypass_reg2(1'b0),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(CK1),
+ .CK2(CK2),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0)
+ );
+endmodule
+
+module NX_DSP_L_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+ input [23:0] A;
+ input [17:0] B;
+ input [35:0] C;
+ input [23:0] CAI;
+ output [23:0] CAO;
+ input [17:0] CBI;
+ output [17:0] CBO;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO;
+ output CO36;
+ output CO56;
+ input [55:0] CZI;
+ output [55:0] CZO;
+ input [17:0] D;
+ output OVF;
+ input R;
+ input RZ;
+ input WE;
+ output [55:0] Z;
+ parameter ALU_DYNAMIC_OP = 1'b0;
+ parameter ALU_MUX = 1'b0;
+ parameter ALU_OP = 6'b000000;
+ parameter CO_SEL = 1'b0;
+ parameter ENABLE_PR_ALU_RST = 1'b0;
+ parameter ENABLE_PR_A_RST = 1'b0;
+ parameter ENABLE_PR_B_RST = 1'b0;
+ parameter ENABLE_PR_CI_RST = 1'b0;
+ parameter ENABLE_PR_CO_RST = 1'b0;
+ parameter ENABLE_PR_C_RST = 1'b0;
+ parameter ENABLE_PR_D_RST = 1'b0;
+ parameter ENABLE_PR_MULT_RST = 1'b0;
+ parameter ENABLE_PR_OV_RST = 1'b0;
+ parameter ENABLE_PR_P_RST = 1'b0;
+ parameter ENABLE_PR_X_RST = 1'b0;
+ parameter ENABLE_PR_Y_RST = 1'b0;
+ parameter ENABLE_PR_Z_RST = 1'b0;
+ parameter ENABLE_SATURATION = 1'b0;
+ parameter MUX_A = 1'b0;
+ parameter MUX_B = 1'b0;
+ parameter MUX_CI = 1'b0;
+ parameter MUX_P = 1'b0;
+ parameter MUX_X = 2'b00;
+ parameter MUX_Y = 1'b0;
+ parameter MUX_Z = 1'b0;
+ parameter PRE_ADDER_OP = 1'b0;
+ parameter PR_ALU_MUX = 1'b0;
+ parameter PR_A_CASCADE_MUX = 2'b00;
+ parameter PR_A_MUX = 2'b00;
+ parameter PR_B_CASCADE_MUX = 2'b00;
+ parameter PR_B_MUX = 2'b00;
+ parameter PR_CI_MUX = 1'b0;
+ parameter PR_CO_MUX = 1'b0;
+ parameter PR_C_MUX = 1'b0;
+ parameter PR_D_MUX = 1'b0;
+ parameter PR_MULT_MUX = 1'b0;
+ parameter PR_OV_MUX = 1'b0;
+ parameter PR_P_MUX = 1'b0;
+ parameter PR_X_MUX = 1'b0;
+ parameter PR_Y_MUX = 1'b0;
+ parameter PR_Z_MUX = 1'b0;
+ parameter SATURATION_RANK = 6'b000000;
+ parameter SIGNED_MODE = 1'b0;
+ parameter Z_FEEDBACK_SHL12 = 1'b0;
+
+localparam RAW_CONFIG0_GEN = { CO_SEL, ALU_DYNAMIC_OP, SATURATION_RANK, ENABLE_SATURATION, Z_FEEDBACK_SHL12, MUX_Z,
+ MUX_CI, MUX_Y, MUX_X, MUX_P, MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };
+
+localparam RAW_CONFIG1_GEN = { PR_OV_MUX, PR_CO_MUX, PR_Z_MUX, PR_ALU_MUX, PR_MULT_MUX, PR_Y_MUX, PR_X_MUX,
+ PR_P_MUX, PR_CI_MUX, PR_D_MUX, PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };
+
+localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_Z_RST, ENABLE_PR_ALU_RST,
+ ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,
+ ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };
+
+localparam RAW_CONFIG3_GEN = { ALU_MUX, ALU_OP };
+
+ NX_DSP_L #(
+ .std_mode(""),
+ .raw_config0(RAW_CONFIG0_GEN),
+ .raw_config1(RAW_CONFIG1_GEN),
+ .raw_config2(RAW_CONFIG2_GEN),
+ .raw_config3(RAW_CONFIG3_GEN),
+ ) _TECHMAP_REPLACE_ (
+ .A1(A[0]),
+ .A2(A[1]),
+ .A3(A[2]),
+ .A4(A[3]),
+ .A5(A[4]),
+ .A6(A[5]),
+ .A7(A[6]),
+ .A8(A[7]),
+ .A9(A[8]),
+ .A10(A[9]),
+ .A11(A[10]),
+ .A12(A[11]),
+ .A13(A[12]),
+ .A14(A[13]),
+ .A15(A[14]),
+ .A16(A[15]),
+ .A17(A[16]),
+ .A18(A[17]),
+ .A19(A[18]),
+ .A20(A[19]),
+ .A21(A[20]),
+ .A22(A[21]),
+ .A23(A[22]),
+ .A24(A[23]),
+
+ .B1(B[0]),
+ .B2(B[1]),
+ .B3(B[2]),
+ .B4(B[3]),
+ .B5(B[4]),
+ .B6(B[5]),
+ .B7(B[6]),
+ .B8(B[7]),
+ .B9(B[8]),
+ .B10(B[9]),
+ .B11(B[10]),
+ .B12(B[11]),
+ .B13(B[12]),
+ .B14(B[13]),
+ .B15(B[14]),
+ .B16(B[15]),
+ .B17(B[16]),
+ .B18(B[17]),
+
+ .C1(C[0]),
+ .C2(C[1]),
+ .C3(C[2]),
+ .C4(C[3]),
+ .C5(C[4]),
+ .C6(C[5]),
+ .C7(C[6]),
+ .C8(C[7]),
+ .C9(C[8]),
+ .C10(C[9]),
+ .C11(C[10]),
+ .C12(C[11]),
+ .C13(C[12]),
+ .C14(C[13]),
+ .C15(C[14]),
+ .C16(C[15]),
+ .C17(C[16]),
+ .C18(C[17]),
+ .C19(C[18]),
+ .C20(C[19]),
+ .C21(C[20]),
+ .C22(C[21]),
+ .C23(C[22]),
+ .C24(C[23]),
+ .C25(C[24]),
+ .C26(C[25]),
+ .C27(C[26]),
+ .C28(C[27]),
+ .C29(C[28]),
+ .C30(C[29]),
+ .C31(C[30]),
+ .C32(C[31]),
+ .C33(C[32]),
+ .C34(C[33]),
+ .C35(C[34]),
+ .C36(C[35]),
+
+ .CAI1(CAI[0]),
+ .CAI2(CAI[1]),
+ .CAI3(CAI[2]),
+ .CAI4(CAI[3]),
+ .CAI5(CAI[4]),
+ .CAI6(CAI[5]),
+ .CAI7(CAI[6]),
+ .CAI8(CAI[7]),
+ .CAI9(CAI[8]),
+ .CAI10(CAI[9]),
+ .CAI11(CAI[10]),
+ .CAI12(CAI[11]),
+ .CAI13(CAI[12]),
+ .CAI14(CAI[13]),
+ .CAI15(CAI[14]),
+ .CAI16(CAI[15]),
+ .CAI17(CAI[16]),
+ .CAI18(CAI[17]),
+ .CAI19(CAI[18]),
+ .CAI20(CAI[19]),
+ .CAI21(CAI[20]),
+ .CAI22(CAI[21]),
+ .CAI23(CAI[22]),
+ .CAI24(CAI[23]),
+
+ .CAO1(CAO[0]),
+ .CAO2(CAO[1]),
+ .CAO3(CAO[2]),
+ .CAO4(CAO[3]),
+ .CAO5(CAO[4]),
+ .CAO6(CAO[5]),
+ .CAO7(CAO[6]),
+ .CAO8(CAO[7]),
+ .CAO9(CAO[8]),
+ .CAO10(CAO[9]),
+ .CAO11(CAO[10]),
+ .CAO12(CAO[11]),
+ .CAO13(CAO[12]),
+ .CAO14(CAO[13]),
+ .CAO15(CAO[14]),
+ .CAO16(CAO[15]),
+ .CAO17(CAO[16]),
+ .CAO18(CAO[17]),
+ .CAO19(CAO[18]),
+ .CAO20(CAO[19]),
+ .CAO21(CAO[20]),
+ .CAO22(CAO[21]),
+ .CAO23(CAO[22]),
+ .CAO24(CAO[23]),
+
+ .CBI1(CBI[0]),
+ .CBI2(CBI[1]),
+ .CBI3(CBI[2]),
+ .CBI4(CBI[3]),
+ .CBI5(CBI[4]),
+ .CBI6(CBI[5]),
+ .CBI7(CBI[6]),
+ .CBI8(CBI[7]),
+ .CBI9(CBI[8]),
+ .CBI10(CBI[9]),
+ .CBI11(CBI[10]),
+ .CBI12(CBI[11]),
+ .CBI13(CBI[12]),
+ .CBI14(CBI[13]),
+ .CBI15(CBI[14]),
+ .CBI16(CBI[15]),
+ .CBI17(CBI[16]),
+ .CBI18(CBI[17]),
+
+ .CBO1(CBO[0]),
+ .CBO2(CBO[1]),
+ .CBO3(CBO[2]),
+ .CBO4(CBO[3]),
+ .CBO5(CBO[4]),
+ .CBO6(CBO[5]),
+ .CBO7(CBO[6]),
+ .CBO8(CBO[7]),
+ .CBO9(CBO[8]),
+ .CBO10(CBO[9]),
+ .CBO11(CBO[10]),
+ .CBO12(CBO[11]),
+ .CBO13(CBO[12]),
+ .CBO14(CBO[13]),
+ .CBO15(CBO[14]),
+ .CBO16(CBO[15]),
+ .CBO17(CBO[16]),
+ .CBO18(CBO[17]),
+
+ .CCI(CCI),
+ .CCO(CCO),
+ .CI(CI),
+ .CK(CK),
+ .CO(CO),
+ .CO37(CO36),
+ .CO57(CO56),
+
+ .CZI1(CZI[0]),
+ .CZI2(CZI[1]),
+ .CZI3(CZI[2]),
+ .CZI4(CZI[3]),
+ .CZI5(CZI[4]),
+ .CZI6(CZI[5]),
+ .CZI7(CZI[6]),
+ .CZI8(CZI[7]),
+ .CZI9(CZI[8]),
+ .CZI10(CZI[9]),
+ .CZI11(CZI[10]),
+ .CZI12(CZI[11]),
+ .CZI13(CZI[12]),
+ .CZI14(CZI[13]),
+ .CZI15(CZI[14]),
+ .CZI16(CZI[15]),
+ .CZI17(CZI[16]),
+ .CZI18(CZI[17]),
+ .CZI19(CZI[18]),
+ .CZI20(CZI[19]),
+ .CZI21(CZI[20]),
+ .CZI22(CZI[21]),
+ .CZI23(CZI[22]),
+ .CZI24(CZI[23]),
+ .CZI25(CZI[24]),
+ .CZI26(CZI[25]),
+ .CZI27(CZI[26]),
+ .CZI28(CZI[27]),
+ .CZI29(CZI[28]),
+ .CZI30(CZI[29]),
+ .CZI31(CZI[30]),
+ .CZI32(CZI[31]),
+ .CZI33(CZI[32]),
+ .CZI34(CZI[33]),
+ .CZI35(CZI[34]),
+ .CZI36(CZI[35]),
+ .CZI37(CZI[36]),
+ .CZI38(CZI[37]),
+ .CZI39(CZI[38]),
+ .CZI40(CZI[39]),
+ .CZI41(CZI[40]),
+ .CZI42(CZI[41]),
+ .CZI43(CZI[42]),
+ .CZI44(CZI[43]),
+ .CZI45(CZI[44]),
+ .CZI46(CZI[45]),
+ .CZI47(CZI[46]),
+ .CZI48(CZI[47]),
+ .CZI49(CZI[48]),
+ .CZI50(CZI[49]),
+ .CZI51(CZI[50]),
+ .CZI52(CZI[51]),
+ .CZI53(CZI[52]),
+ .CZI54(CZI[53]),
+ .CZI55(CZI[54]),
+ .CZI56(CZI[55]),
+
+ .CZO1(CZO[0]),
+ .CZO2(CZO[1]),
+ .CZO3(CZO[2]),
+ .CZO4(CZO[3]),
+ .CZO5(CZO[4]),
+ .CZO6(CZO[5]),
+ .CZO7(CZO[6]),
+ .CZO8(CZO[7]),
+ .CZO9(CZO[8]),
+ .CZO10(CZO[9]),
+ .CZO11(CZO[10]),
+ .CZO12(CZO[11]),
+ .CZO13(CZO[12]),
+ .CZO14(CZO[13]),
+ .CZO15(CZO[14]),
+ .CZO16(CZO[15]),
+ .CZO17(CZO[16]),
+ .CZO18(CZO[17]),
+ .CZO19(CZO[18]),
+ .CZO20(CZO[19]),
+ .CZO21(CZO[20]),
+ .CZO22(CZO[21]),
+ .CZO23(CZO[22]),
+ .CZO24(CZO[23]),
+ .CZO25(CZO[24]),
+ .CZO26(CZO[25]),
+ .CZO27(CZO[26]),
+ .CZO28(CZO[27]),
+ .CZO29(CZO[28]),
+ .CZO30(CZO[29]),
+ .CZO31(CZO[30]),
+ .CZO32(CZO[31]),
+ .CZO33(CZO[32]),
+ .CZO34(CZO[33]),
+ .CZO35(CZO[34]),
+ .CZO36(CZO[35]),
+ .CZO37(CZO[36]),
+ .CZO38(CZO[37]),
+ .CZO39(CZO[38]),
+ .CZO40(CZO[39]),
+ .CZO41(CZO[40]),
+ .CZO42(CZO[41]),
+ .CZO43(CZO[42]),
+ .CZO44(CZO[43]),
+ .CZO45(CZO[44]),
+ .CZO46(CZO[45]),
+ .CZO47(CZO[46]),
+ .CZO48(CZO[47]),
+ .CZO49(CZO[48]),
+ .CZO50(CZO[49]),
+ .CZO51(CZO[50]),
+ .CZO52(CZO[51]),
+ .CZO53(CZO[52]),
+ .CZO54(CZO[53]),
+ .CZO55(CZO[54]),
+ .CZO56(CZO[55]),
+
+ .D1(D[0]),
+ .D2(D[1]),
+ .D3(D[2]),
+ .D4(D[3]),
+ .D5(D[4]),
+ .D6(D[5]),
+ .D7(D[6]),
+ .D8(D[7]),
+ .D9(D[8]),
+ .D10(D[9]),
+ .D11(D[10]),
+ .D12(D[11]),
+ .D13(D[12]),
+ .D14(D[13]),
+ .D15(D[14]),
+ .D16(D[15]),
+ .D17(D[16]),
+ .D18(D[17]),
+
+ .OVF(OVF),
+ .R(R),
+ .RZ(RZ),
+ .WE(WE),
+
+ .Z1(Z[0]),
+ .Z2(Z[1]),
+ .Z3(Z[2]),
+ .Z4(Z[3]),
+ .Z5(Z[4]),
+ .Z6(Z[5]),
+ .Z7(Z[6]),
+ .Z8(Z[7]),
+ .Z9(Z[8]),
+ .Z10(Z[9]),
+ .Z11(Z[10]),
+ .Z12(Z[11]),
+ .Z13(Z[12]),
+ .Z14(Z[13]),
+ .Z15(Z[14]),
+ .Z16(Z[15]),
+ .Z17(Z[16]),
+ .Z18(Z[17]),
+ .Z19(Z[18]),
+ .Z20(Z[19]),
+ .Z21(Z[20]),
+ .Z22(Z[21]),
+ .Z23(Z[22]),
+ .Z24(Z[23]),
+ .Z25(Z[24]),
+ .Z26(Z[25]),
+ .Z27(Z[26]),
+ .Z28(Z[27]),
+ .Z29(Z[28]),
+ .Z30(Z[29]),
+ .Z31(Z[30]),
+ .Z32(Z[31]),
+ .Z33(Z[32]),
+ .Z34(Z[33]),
+ .Z35(Z[34]),
+ .Z36(Z[35]),
+ .Z37(Z[36]),
+ .Z38(Z[37]),
+ .Z39(Z[38]),
+ .Z40(Z[39]),
+ .Z41(Z[40]),
+ .Z42(Z[41]),
+ .Z43(Z[42]),
+ .Z44(Z[43]),
+ .Z45(Z[44]),
+ .Z46(Z[45]),
+ .Z47(Z[46]),
+ .Z48(Z[47]),
+ .Z49(Z[48]),
+ .Z50(Z[49]),
+ .Z51(Z[50]),
+ .Z52(Z[51]),
+ .Z53(Z[52]),
+ .Z54(Z[53]),
+ .Z55(Z[54]),
+ .Z56(Z[55])
+ );
+endmodule
+
+module NX_DSP_L_WRAP(CCI, CCO, CI, CK, CO, CO37, CO57, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+ input [23:0] A;
+ input [17:0] B;
+ input [35:0] C;
+ input [23:0] CAI;
+ output [23:0] CAO;
+ input [17:0] CBI;
+ output [17:0] CBO;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO;
+ output CO37;
+ output CO57;
+ input [55:0] CZI;
+ output [55:0] CZO;
+ input [17:0] D;
+ output OVF;
+ input R;
+ input RZ;
+ input WE;
+ output [55:0] Z;
+ parameter raw_config0 = 20'b00000000000000000000;
+ parameter raw_config1 = 19'b0000000000000000000;
+ parameter raw_config2 = 13'b0000000000000;
+ parameter raw_config3 = 7'b0000000;
+ parameter std_mode = "";
+
+ NX_DSP_L #(
+ .std_mode(std_mode),
+ .raw_config0(raw_config0),
+ .raw_config1(raw_config1),
+ .raw_config2(raw_config2),
+ .raw_config3(raw_config3),
+ ) _TECHMAP_REPLACE_ (
+ .A1(A[0]),
+ .A2(A[1]),
+ .A3(A[2]),
+ .A4(A[3]),
+ .A5(A[4]),
+ .A6(A[5]),
+ .A7(A[6]),
+ .A8(A[7]),
+ .A9(A[8]),
+ .A10(A[9]),
+ .A11(A[10]),
+ .A12(A[11]),
+ .A13(A[12]),
+ .A14(A[13]),
+ .A15(A[14]),
+ .A16(A[15]),
+ .A17(A[16]),
+ .A18(A[17]),
+ .A19(A[18]),
+ .A20(A[19]),
+ .A21(A[20]),
+ .A22(A[21]),
+ .A23(A[22]),
+ .A24(A[23]),
+
+ .B1(B[0]),
+ .B2(B[1]),
+ .B3(B[2]),
+ .B4(B[3]),
+ .B5(B[4]),
+ .B6(B[5]),
+ .B7(B[6]),
+ .B8(B[7]),
+ .B9(B[8]),
+ .B10(B[9]),
+ .B11(B[10]),
+ .B12(B[11]),
+ .B13(B[12]),
+ .B14(B[13]),
+ .B15(B[14]),
+ .B16(B[15]),
+ .B17(B[16]),
+ .B18(B[17]),
+
+ .C1(C[0]),
+ .C2(C[1]),
+ .C3(C[2]),
+ .C4(C[3]),
+ .C5(C[4]),
+ .C6(C[5]),
+ .C7(C[6]),
+ .C8(C[7]),
+ .C9(C[8]),
+ .C10(C[9]),
+ .C11(C[10]),
+ .C12(C[11]),
+ .C13(C[12]),
+ .C14(C[13]),
+ .C15(C[14]),
+ .C16(C[15]),
+ .C17(C[16]),
+ .C18(C[17]),
+ .C19(C[18]),
+ .C20(C[19]),
+ .C21(C[20]),
+ .C22(C[21]),
+ .C23(C[22]),
+ .C24(C[23]),
+ .C25(C[24]),
+ .C26(C[25]),
+ .C27(C[26]),
+ .C28(C[27]),
+ .C29(C[28]),
+ .C30(C[29]),
+ .C31(C[30]),
+ .C32(C[31]),
+ .C33(C[32]),
+ .C34(C[33]),
+ .C35(C[34]),
+ .C36(C[35]),
+
+ .CAI1(CAI[0]),
+ .CAI2(CAI[1]),
+ .CAI3(CAI[2]),
+ .CAI4(CAI[3]),
+ .CAI5(CAI[4]),
+ .CAI6(CAI[5]),
+ .CAI7(CAI[6]),
+ .CAI8(CAI[7]),
+ .CAI9(CAI[8]),
+ .CAI10(CAI[9]),
+ .CAI11(CAI[10]),
+ .CAI12(CAI[11]),
+ .CAI13(CAI[12]),
+ .CAI14(CAI[13]),
+ .CAI15(CAI[14]),
+ .CAI16(CAI[15]),
+ .CAI17(CAI[16]),
+ .CAI18(CAI[17]),
+ .CAI19(CAI[18]),
+ .CAI20(CAI[19]),
+ .CAI21(CAI[20]),
+ .CAI22(CAI[21]),
+ .CAI23(CAI[22]),
+ .CAI24(CAI[23]),
+
+ .CAO1(CAO[0]),
+ .CAO2(CAO[1]),
+ .CAO3(CAO[2]),
+ .CAO4(CAO[3]),
+ .CAO5(CAO[4]),
+ .CAO6(CAO[5]),
+ .CAO7(CAO[6]),
+ .CAO8(CAO[7]),
+ .CAO9(CAO[8]),
+ .CAO10(CAO[9]),
+ .CAO11(CAO[10]),
+ .CAO12(CAO[11]),
+ .CAO13(CAO[12]),
+ .CAO14(CAO[13]),
+ .CAO15(CAO[14]),
+ .CAO16(CAO[15]),
+ .CAO17(CAO[16]),
+ .CAO18(CAO[17]),
+ .CAO19(CAO[18]),
+ .CAO20(CAO[19]),
+ .CAO21(CAO[20]),
+ .CAO22(CAO[21]),
+ .CAO23(CAO[22]),
+ .CAO24(CAO[23]),
+
+ .CBI1(CBI[0]),
+ .CBI2(CBI[1]),
+ .CBI3(CBI[2]),
+ .CBI4(CBI[3]),
+ .CBI5(CBI[4]),
+ .CBI6(CBI[5]),
+ .CBI7(CBI[6]),
+ .CBI8(CBI[7]),
+ .CBI9(CBI[8]),
+ .CBI10(CBI[9]),
+ .CBI11(CBI[10]),
+ .CBI12(CBI[11]),
+ .CBI13(CBI[12]),
+ .CBI14(CBI[13]),
+ .CBI15(CBI[14]),
+ .CBI16(CBI[15]),
+ .CBI17(CBI[16]),
+ .CBI18(CBI[17]),
+
+ .CBO1(CBO[0]),
+ .CBO2(CBO[1]),
+ .CBO3(CBO[2]),
+ .CBO4(CBO[3]),
+ .CBO5(CBO[4]),
+ .CBO6(CBO[5]),
+ .CBO7(CBO[6]),
+ .CBO8(CBO[7]),
+ .CBO9(CBO[8]),
+ .CBO10(CBO[9]),
+ .CBO11(CBO[10]),
+ .CBO12(CBO[11]),
+ .CBO13(CBO[12]),
+ .CBO14(CBO[13]),
+ .CBO15(CBO[14]),
+ .CBO16(CBO[15]),
+ .CBO17(CBO[16]),
+ .CBO18(CBO[17]),
+
+ .CCI(CCI),
+ .CCO(CCO),
+ .CI(CI),
+ .CK(CK),
+ .CO(CO),
+ .CO37(CO37),
+ .CO57(CO57),
+
+ .CZI1(CZI[0]),
+ .CZI2(CZI[1]),
+ .CZI3(CZI[2]),
+ .CZI4(CZI[3]),
+ .CZI5(CZI[4]),
+ .CZI6(CZI[5]),
+ .CZI7(CZI[6]),
+ .CZI8(CZI[7]),
+ .CZI9(CZI[8]),
+ .CZI10(CZI[9]),
+ .CZI11(CZI[10]),
+ .CZI12(CZI[11]),
+ .CZI13(CZI[12]),
+ .CZI14(CZI[13]),
+ .CZI15(CZI[14]),
+ .CZI16(CZI[15]),
+ .CZI17(CZI[16]),
+ .CZI18(CZI[17]),
+ .CZI19(CZI[18]),
+ .CZI20(CZI[19]),
+ .CZI21(CZI[20]),
+ .CZI22(CZI[21]),
+ .CZI23(CZI[22]),
+ .CZI24(CZI[23]),
+ .CZI25(CZI[24]),
+ .CZI26(CZI[25]),
+ .CZI27(CZI[26]),
+ .CZI28(CZI[27]),
+ .CZI29(CZI[28]),
+ .CZI30(CZI[29]),
+ .CZI31(CZI[30]),
+ .CZI32(CZI[31]),
+ .CZI33(CZI[32]),
+ .CZI34(CZI[33]),
+ .CZI35(CZI[34]),
+ .CZI36(CZI[35]),
+ .CZI37(CZI[36]),
+ .CZI38(CZI[37]),
+ .CZI39(CZI[38]),
+ .CZI40(CZI[39]),
+ .CZI41(CZI[40]),
+ .CZI42(CZI[41]),
+ .CZI43(CZI[42]),
+ .CZI44(CZI[43]),
+ .CZI45(CZI[44]),
+ .CZI46(CZI[45]),
+ .CZI47(CZI[46]),
+ .CZI48(CZI[47]),
+ .CZI49(CZI[48]),
+ .CZI50(CZI[49]),
+ .CZI51(CZI[50]),
+ .CZI52(CZI[51]),
+ .CZI53(CZI[52]),
+ .CZI54(CZI[53]),
+ .CZI55(CZI[54]),
+ .CZI56(CZI[55]),
+
+ .CZO1(CZO[0]),
+ .CZO2(CZO[1]),
+ .CZO3(CZO[2]),
+ .CZO4(CZO[3]),
+ .CZO5(CZO[4]),
+ .CZO6(CZO[5]),
+ .CZO7(CZO[6]),
+ .CZO8(CZO[7]),
+ .CZO9(CZO[8]),
+ .CZO10(CZO[9]),
+ .CZO11(CZO[10]),
+ .CZO12(CZO[11]),
+ .CZO13(CZO[12]),
+ .CZO14(CZO[13]),
+ .CZO15(CZO[14]),
+ .CZO16(CZO[15]),
+ .CZO17(CZO[16]),
+ .CZO18(CZO[17]),
+ .CZO19(CZO[18]),
+ .CZO20(CZO[19]),
+ .CZO21(CZO[20]),
+ .CZO22(CZO[21]),
+ .CZO23(CZO[22]),
+ .CZO24(CZO[23]),
+ .CZO25(CZO[24]),
+ .CZO26(CZO[25]),
+ .CZO27(CZO[26]),
+ .CZO28(CZO[27]),
+ .CZO29(CZO[28]),
+ .CZO30(CZO[29]),
+ .CZO31(CZO[30]),
+ .CZO32(CZO[31]),
+ .CZO33(CZO[32]),
+ .CZO34(CZO[33]),
+ .CZO35(CZO[34]),
+ .CZO36(CZO[35]),
+ .CZO37(CZO[36]),
+ .CZO38(CZO[37]),
+ .CZO39(CZO[38]),
+ .CZO40(CZO[39]),
+ .CZO41(CZO[40]),
+ .CZO42(CZO[41]),
+ .CZO43(CZO[42]),
+ .CZO44(CZO[43]),
+ .CZO45(CZO[44]),
+ .CZO46(CZO[45]),
+ .CZO47(CZO[46]),
+ .CZO48(CZO[47]),
+ .CZO49(CZO[48]),
+ .CZO50(CZO[49]),
+ .CZO51(CZO[50]),
+ .CZO52(CZO[51]),
+ .CZO53(CZO[52]),
+ .CZO54(CZO[53]),
+ .CZO55(CZO[54]),
+ .CZO56(CZO[55]),
+
+ .D1(D[0]),
+ .D2(D[1]),
+ .D3(D[2]),
+ .D4(D[3]),
+ .D5(D[4]),
+ .D6(D[5]),
+ .D7(D[6]),
+ .D8(D[7]),
+ .D9(D[8]),
+ .D10(D[9]),
+ .D11(D[10]),
+ .D12(D[11]),
+ .D13(D[12]),
+ .D14(D[13]),
+ .D15(D[14]),
+ .D16(D[15]),
+ .D17(D[16]),
+ .D18(D[17]),
+
+ .OVF(OVF),
+ .R(R),
+ .RZ(RZ),
+ .WE(WE),
+
+ .Z1(Z[0]),
+ .Z2(Z[1]),
+ .Z3(Z[2]),
+ .Z4(Z[3]),
+ .Z5(Z[4]),
+ .Z6(Z[5]),
+ .Z7(Z[6]),
+ .Z8(Z[7]),
+ .Z9(Z[8]),
+ .Z10(Z[9]),
+ .Z11(Z[10]),
+ .Z12(Z[11]),
+ .Z13(Z[12]),
+ .Z14(Z[13]),
+ .Z15(Z[14]),
+ .Z16(Z[15]),
+ .Z17(Z[16]),
+ .Z18(Z[17]),
+ .Z19(Z[18]),
+ .Z20(Z[19]),
+ .Z21(Z[20]),
+ .Z22(Z[21]),
+ .Z23(Z[22]),
+ .Z24(Z[23]),
+ .Z25(Z[24]),
+ .Z26(Z[25]),
+ .Z27(Z[26]),
+ .Z28(Z[27]),
+ .Z29(Z[28]),
+ .Z30(Z[29]),
+ .Z31(Z[30]),
+ .Z32(Z[31]),
+ .Z33(Z[32]),
+ .Z34(Z[33]),
+ .Z35(Z[34]),
+ .Z36(Z[35]),
+ .Z37(Z[36]),
+ .Z38(Z[37]),
+ .Z39(Z[38]),
+ .Z40(Z[39]),
+ .Z41(Z[40]),
+ .Z42(Z[41]),
+ .Z43(Z[42]),
+ .Z44(Z[43]),
+ .Z45(Z[44]),
+ .Z46(Z[45]),
+ .Z47(Z[46]),
+ .Z48(Z[47]),
+ .Z49(Z[48]),
+ .Z50(Z[49]),
+ .Z51(Z[50]),
+ .Z52(Z[51]),
+ .Z53(Z[52]),
+ .Z54(Z[53]),
+ .Z55(Z[54]),
+ .Z56(Z[55])
+ );
+endmodule
+
+module NX_RFB_L_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
+ output COR;
+ output ERR;
+ input [15:0] I;
+ output [15:0] O;
+ input [5:0] RA;
+ input RCK;
+ input RE;
+ input [5:0] WA;
+ input WCK;
+ input WE;
+ parameter mem_ctxt = "";
+ parameter mode = 0;
+ parameter rck_edge = 1'b0;
+ parameter wck_edge = 1'b0;
+
+ NX_RFB_L #(
+ .mode(mode),
+ .rck_edge(rck_edge),
+ .wck_edge(wck_edge),
+ .mem_ctxt(mem_ctxt)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(RCK),
+ .WCK(WCK),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .COR(COR),
+ .ERR(ERR),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .RA1(RA[0]),
+ .RA2(RA[1]),
+ .RA3(RA[2]),
+ .RA4(RA[3]),
+ .RA5(RA[4]),
+ .RA6(RA[5]),
+ .RE(RE),
+ .WA1(WA[0]),
+ .WA2(WA[1]),
+ .WA3(WA[2]),
+ .WA4(WA[3]),
+ .WA5(WA[4]),
+ .WA6(WA[5]),
+ .WE(WE)
+ );
+endmodule
+
+module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+ output COR;
+ output ERR;
+ input I1;
+ input I10;
+ input I11;
+ input I12;
+ input I13;
+ input I14;
+ input I15;
+ input I16;
+ input I2;
+ input I3;
+ input I4;
+ input I5;
+ input I6;
+ input I7;
+ input I8;
+ input I9;
+ output O1;
+ output O10;
+ output O11;
+ output O12;
+ output O13;
+ output O14;
+ output O15;
+ output O16;
+ output O2;
+ output O3;
+ output O4;
+ output O5;
+ output O6;
+ output O7;
+ output O8;
+ output O9;
+ input RA1;
+ input RA2;
+ input RA3;
+ input RA4;
+ input RA5;
+ input RA6;
+ input RCK;
+ input RE;
+ input WA1;
+ input WA2;
+ input WA3;
+ input WA4;
+ input WA5;
+ input WA6;
+ input WCK;
+ input WE;
+ parameter addr_mask = 5'b00000;
+ parameter mem_ctxt = "";
+ parameter rck_edge = 1'b0;
+ parameter wck_edge = 1'b0;
+ parameter we_mask = 1'b0;
+ parameter wea_mask = 1'b0;
+
+ NX_RFB_L #(
+ .mode(0),
+ .mem_ctxt(mem_ctxt),
+ .rck_edge(rck_edge),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(RCK),
+ .WCK(WCK),
+ .I1(I1),
+ .I2(I2),
+ .I3(I3),
+ .I4(I4),
+ .I5(I5),
+ .I6(I6),
+ .I7(I7),
+ .I8(I8),
+ .I9(I9),
+ .I10(I10),
+ .I11(I11),
+ .I12(I12),
+ .I13(I13),
+ .I14(I14),
+ .I15(I15),
+ .I16(I16),
+ .COR(COR),
+ .ERR(ERR),
+ .O1(O1),
+ .O2(O2),
+ .O3(O3),
+ .O4(O4),
+ .O5(O5),
+ .O6(O6),
+ .O7(O7),
+ .O8(O8),
+ .O9(O9),
+ .O10(O10),
+ .O11(O11),
+ .O12(O12),
+ .O13(O13),
+ .O14(O14),
+ .O15(O15),
+ .O16(O16),
+ .RA1(RA1),
+ .RA2(RA2),
+ .RA3(RA3),
+ .RA4(RA4),
+ .RA5(RA5),
+ .RA6(RA6),
+ .RE(RE),
+ .WA1(WA1),
+ .WA2(WA2),
+ .WA3(WA3),
+ .WA4(WA4),
+ .WA5(WA5),
+ .WA6(WA6),
+ .WE(WE)
+ );
+endmodule
+
+//TODO
+module SMUL24x32_2DSP_ACC_2DSP_L(clk, rst, we, A, B, Z);
+ input [23:0] A;
+ input [31:0] B;
+ output [91:0] Z;
+ input clk;
+ input rst;
+ input we;
+endmodule
+
+//TODO
+module NX_HSSL_L_FULL(hssl_clk_user_i, hssl_clk_ref_i, hssl_clock_o, usr_com_tx_pma_pre_sign_i, usr_com_tx_pma_pre_en_i, usr_com_tx_pma_main_sign_i, usr_com_rx_pma_m_eye_i, usr_com_tx_pma_post_sign_i, usr_pll_pma_rst_n_i, usr_main_rst_n_i, usr_calibrate_pma_en_i, usr_pcs_ctrl_pll_lock_en_i, usr_pcs_ctrl_ovs_en_i, usr_pll_lock_o, usr_calibrate_pma_out_o, pma_clk_ext_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i, usr_tx0_pma_clk_en_i, usr_tx0_busy_o, pma_tx0_o
+, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_ctrl_el_buff_fifo_en_i, usr_rx0_rst_n_i, usr_rx0_pma_cdr_rst_i, usr_rx0_pma_ckgen_rst_n_i, usr_rx0_pma_pll_rst_n_i, usr_rx0_pma_loss_of_signal_o, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_busy_o, usr_rx0_pll_lock_o, pma_rx0_i, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_pma_clk_en_i, usr_tx1_busy_o, pma_tx1_o
+, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_ctrl_el_buff_fifo_en_i, usr_rx1_rst_n_i, usr_rx1_pma_cdr_rst_i, usr_rx1_pma_ckgen_rst_n_i, usr_rx1_pma_pll_rst_n_i, usr_rx1_pma_loss_of_signal_o, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_busy_o, usr_rx1_pll_lock_o, pma_rx1_i, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_pma_clk_en_i, usr_tx2_busy_o, pma_tx2_o
+, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_ctrl_el_buff_fifo_en_i, usr_rx2_rst_n_i, usr_rx2_pma_cdr_rst_i, usr_rx2_pma_ckgen_rst_n_i, usr_rx2_pma_pll_rst_n_i, usr_rx2_pma_loss_of_signal_o, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_busy_o, usr_rx2_pll_lock_o, pma_rx2_i, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_pma_clk_en_i, usr_tx3_busy_o, pma_tx3_o
+, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_ctrl_el_buff_fifo_en_i, usr_rx3_rst_n_i, usr_rx3_pma_cdr_rst_i, usr_rx3_pma_ckgen_rst_n_i, usr_rx3_pma_pll_rst_n_i, usr_rx3_pma_loss_of_signal_o, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_busy_o, usr_rx3_pll_lock_o, pma_rx3_i, usr_tx4_ctrl_replace_en_i, usr_tx4_rst_n_i, usr_tx4_pma_clk_en_i, usr_tx4_busy_o, pma_tx4_o
+, usr_rx4_ctrl_dscr_en_i, usr_rx4_ctrl_dec_en_i, usr_rx4_ctrl_align_en_i, usr_rx4_ctrl_align_sync_i, usr_rx4_ctrl_replace_en_i, usr_rx4_ctrl_el_buff_rst_i, usr_rx4_ctrl_el_buff_fifo_en_i, usr_rx4_rst_n_i, usr_rx4_pma_cdr_rst_i, usr_rx4_pma_ckgen_rst_n_i, usr_rx4_pma_pll_rst_n_i, usr_rx4_pma_loss_of_signal_o, usr_rx4_ctrl_char_is_aligned_o, usr_rx4_busy_o, usr_rx4_pll_lock_o, pma_rx4_i, usr_tx5_ctrl_replace_en_i, usr_tx5_rst_n_i, usr_tx5_pma_clk_en_i, usr_tx5_busy_o, pma_tx5_o
+, usr_rx5_ctrl_dscr_en_i, usr_rx5_ctrl_dec_en_i, usr_rx5_ctrl_align_en_i, usr_rx5_ctrl_align_sync_i, usr_rx5_ctrl_replace_en_i, usr_rx5_ctrl_el_buff_rst_i, usr_rx5_ctrl_el_buff_fifo_en_i, usr_rx5_rst_n_i, usr_rx5_pma_cdr_rst_i, usr_rx5_pma_ckgen_rst_n_i, usr_rx5_pma_pll_rst_n_i, usr_rx5_pma_loss_of_signal_o, usr_rx5_ctrl_char_is_aligned_o, usr_rx5_busy_o, usr_rx5_pll_lock_o, pma_rx5_i, usr_com_tx_pma_main_en_i, usr_com_tx_pma_margin_sel_i, usr_com_tx_pma_margin_input_sel_i, usr_com_tx_pma_margin_sel_var_i, usr_com_tx_pma_margin_input_sel_var_i
+, usr_com_tx_pma_post_en_i, usr_com_tx_pma_post_input_sel_i, usr_com_tx_pma_post_input_sel_var_i, usr_com_rx_pma_ctle_cap_i, usr_com_rx_pma_ctle_resp_i, usr_com_rx_pma_ctle_resn_i, usr_com_ctrl_tx_sel_i, usr_com_ctrl_rx_sel_i, usr_calibrate_pma_res_p1_i, usr_calibrate_pma_res_n2_i, usr_calibrate_pma_res_n3_i, usr_calibrate_pma_res_p4_i, usr_calibrate_pma_sel_i, usr_main_test_i, usr_main_test_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_test_i
+, usr_tx0_data_i, usr_tx0_test_o, usr_rx0_data_o, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_test_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_test_i, usr_tx1_data_i, usr_tx1_test_o, usr_rx1_data_o
+, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_test_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_test_i, usr_tx2_data_i, usr_tx2_test_o, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_test_i, usr_rx2_ctrl_char_is_comma_o
+, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i, usr_tx3_ctrl_end_of_frame_i, usr_tx3_test_i, usr_tx3_data_i, usr_tx3_test_o, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_test_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o
+, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_tx4_ctrl_enc_en_i, usr_tx4_ctrl_char_is_k_i, usr_tx4_ctrl_scr_en_i, usr_tx4_ctrl_end_of_multiframe_i, usr_tx4_ctrl_end_of_frame_i, usr_tx4_test_i, usr_tx4_data_i, usr_tx4_test_o, usr_rx4_data_o, usr_rx4_ctrl_ovs_bit_sel_i, usr_rx4_test_i, usr_rx4_ctrl_char_is_comma_o, usr_rx4_ctrl_char_is_k_o, usr_rx4_ctrl_not_in_table_o, usr_rx4_ctrl_disp_err_o, usr_rx4_ctrl_char_is_a_o, usr_rx4_ctrl_char_is_f_o, usr_rx4_test_o
+, usr_tx5_ctrl_enc_en_i, usr_tx5_ctrl_char_is_k_i, usr_tx5_ctrl_scr_en_i, usr_tx5_ctrl_end_of_multiframe_i, usr_tx5_ctrl_end_of_frame_i, usr_tx5_test_i, usr_tx5_data_i, usr_tx5_test_o, usr_rx5_data_o, usr_rx5_ctrl_ovs_bit_sel_i, usr_rx5_test_i, usr_rx5_ctrl_char_is_comma_o, usr_rx5_ctrl_char_is_k_o, usr_rx5_ctrl_not_in_table_o, usr_rx5_ctrl_disp_err_o, usr_rx5_ctrl_char_is_a_o, usr_rx5_ctrl_char_is_f_o, usr_rx5_test_o, usr_com_tx_pma_pre_input_sel_i);
+ input hssl_clk_ref_i;
+ input hssl_clk_user_i;
+ output hssl_clock_o;
+ input pma_clk_ext_i;
+ input pma_rx0_i;
+ input pma_rx1_i;
+ input pma_rx2_i;
+ input pma_rx3_i;
+ input pma_rx4_i;
+ input pma_rx5_i;
+ output pma_tx0_o;
+ output pma_tx1_o;
+ output pma_tx2_o;
+ output pma_tx3_o;
+ output pma_tx4_o;
+ output pma_tx5_o;
+ input usr_calibrate_pma_en_i;
+ output usr_calibrate_pma_out_o;
+ input [7:0] usr_calibrate_pma_res_n2_i;
+ input [7:0] usr_calibrate_pma_res_n3_i;
+ input [7:0] usr_calibrate_pma_res_p1_i;
+ input [7:0] usr_calibrate_pma_res_p4_i;
+ input [3:0] usr_calibrate_pma_sel_i;
+ input [5:0] usr_com_ctrl_rx_sel_i;
+ input [5:0] usr_com_ctrl_tx_sel_i;
+ input [3:0] usr_com_rx_pma_ctle_cap_i;
+ input [3:0] usr_com_rx_pma_ctle_resn_i;
+ input [3:0] usr_com_rx_pma_ctle_resp_i;
+ input usr_com_rx_pma_m_eye_i;
+ input [5:0] usr_com_tx_pma_main_en_i;
+ input usr_com_tx_pma_main_sign_i;
+ input [3:0] usr_com_tx_pma_margin_input_sel_i;
+ input [4:0] usr_com_tx_pma_margin_input_sel_var_i;
+ input [3:0] usr_com_tx_pma_margin_sel_i;
+ input [4:0] usr_com_tx_pma_margin_sel_var_i;
+ input [4:0] usr_com_tx_pma_post_en_i;
+ input [3:0] usr_com_tx_pma_post_input_sel_i;
+ input [3:0] usr_com_tx_pma_post_input_sel_var_i;
+ input usr_com_tx_pma_post_sign_i;
+ input usr_com_tx_pma_pre_en_i;
+ input [3:0] usr_com_tx_pma_pre_input_sel_i;
+ input usr_com_tx_pma_pre_sign_i;
+ input usr_main_rst_n_i;
+ input [7:0] usr_main_test_i;
+ output [7:0] usr_main_test_o;
+ input usr_pcs_ctrl_ovs_en_i;
+ input usr_pcs_ctrl_pll_lock_en_i;
+ output usr_pll_lock_o;
+ input usr_pll_pma_rst_n_i;
+ output usr_rx0_busy_o;
+ input usr_rx0_ctrl_align_en_i;
+ input usr_rx0_ctrl_align_sync_i;
+ output [7:0] usr_rx0_ctrl_char_is_a_o;
+ output usr_rx0_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx0_ctrl_char_is_comma_o;
+ output [7:0] usr_rx0_ctrl_char_is_f_o;
+ output [7:0] usr_rx0_ctrl_char_is_k_o;
+ input usr_rx0_ctrl_dec_en_i;
+ output [7:0] usr_rx0_ctrl_disp_err_o;
+ input usr_rx0_ctrl_dscr_en_i;
+ input usr_rx0_ctrl_el_buff_fifo_en_i;
+ input usr_rx0_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx0_ctrl_not_in_table_o;
+ input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
+ input usr_rx0_ctrl_replace_en_i;
+ output [63:0] usr_rx0_data_o;
+ output usr_rx0_pll_lock_o;
+ input usr_rx0_pma_cdr_rst_i;
+ input usr_rx0_pma_ckgen_rst_n_i;
+ output usr_rx0_pma_loss_of_signal_o;
+ input usr_rx0_pma_pll_rst_n_i;
+ input usr_rx0_rst_n_i;
+ input [3:0] usr_rx0_test_i;
+ output [7:0] usr_rx0_test_o;
+ output usr_rx1_busy_o;
+ input usr_rx1_ctrl_align_en_i;
+ input usr_rx1_ctrl_align_sync_i;
+ output [7:0] usr_rx1_ctrl_char_is_a_o;
+ output usr_rx1_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx1_ctrl_char_is_comma_o;
+ output [7:0] usr_rx1_ctrl_char_is_f_o;
+ output [7:0] usr_rx1_ctrl_char_is_k_o;
+ input usr_rx1_ctrl_dec_en_i;
+ output [7:0] usr_rx1_ctrl_disp_err_o;
+ input usr_rx1_ctrl_dscr_en_i;
+ input usr_rx1_ctrl_el_buff_fifo_en_i;
+ input usr_rx1_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx1_ctrl_not_in_table_o;
+ input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
+ input usr_rx1_ctrl_replace_en_i;
+ output [63:0] usr_rx1_data_o;
+ output usr_rx1_pll_lock_o;
+ input usr_rx1_pma_cdr_rst_i;
+ input usr_rx1_pma_ckgen_rst_n_i;
+ output usr_rx1_pma_loss_of_signal_o;
+ input usr_rx1_pma_pll_rst_n_i;
+ input usr_rx1_rst_n_i;
+ input [3:0] usr_rx1_test_i;
+ output [7:0] usr_rx1_test_o;
+ output usr_rx2_busy_o;
+ input usr_rx2_ctrl_align_en_i;
+ input usr_rx2_ctrl_align_sync_i;
+ output [7:0] usr_rx2_ctrl_char_is_a_o;
+ output usr_rx2_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx2_ctrl_char_is_comma_o;
+ output [7:0] usr_rx2_ctrl_char_is_f_o;
+ output [7:0] usr_rx2_ctrl_char_is_k_o;
+ input usr_rx2_ctrl_dec_en_i;
+ output [7:0] usr_rx2_ctrl_disp_err_o;
+ input usr_rx2_ctrl_dscr_en_i;
+ input usr_rx2_ctrl_el_buff_fifo_en_i;
+ input usr_rx2_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx2_ctrl_not_in_table_o;
+ input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
+ input usr_rx2_ctrl_replace_en_i;
+ output [63:0] usr_rx2_data_o;
+ output usr_rx2_pll_lock_o;
+ input usr_rx2_pma_cdr_rst_i;
+ input usr_rx2_pma_ckgen_rst_n_i;
+ output usr_rx2_pma_loss_of_signal_o;
+ input usr_rx2_pma_pll_rst_n_i;
+ input usr_rx2_rst_n_i;
+ input [3:0] usr_rx2_test_i;
+ output [7:0] usr_rx2_test_o;
+ output usr_rx3_busy_o;
+ input usr_rx3_ctrl_align_en_i;
+ input usr_rx3_ctrl_align_sync_i;
+ output [7:0] usr_rx3_ctrl_char_is_a_o;
+ output usr_rx3_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx3_ctrl_char_is_comma_o;
+ output [7:0] usr_rx3_ctrl_char_is_f_o;
+ output [7:0] usr_rx3_ctrl_char_is_k_o;
+ input usr_rx3_ctrl_dec_en_i;
+ output [7:0] usr_rx3_ctrl_disp_err_o;
+ input usr_rx3_ctrl_dscr_en_i;
+ input usr_rx3_ctrl_el_buff_fifo_en_i;
+ input usr_rx3_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx3_ctrl_not_in_table_o;
+ input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
+ input usr_rx3_ctrl_replace_en_i;
+ output [63:0] usr_rx3_data_o;
+ output usr_rx3_pll_lock_o;
+ input usr_rx3_pma_cdr_rst_i;
+ input usr_rx3_pma_ckgen_rst_n_i;
+ output usr_rx3_pma_loss_of_signal_o;
+ input usr_rx3_pma_pll_rst_n_i;
+ input usr_rx3_rst_n_i;
+ input [3:0] usr_rx3_test_i;
+ output [7:0] usr_rx3_test_o;
+ output usr_rx4_busy_o;
+ input usr_rx4_ctrl_align_en_i;
+ input usr_rx4_ctrl_align_sync_i;
+ output [7:0] usr_rx4_ctrl_char_is_a_o;
+ output usr_rx4_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx4_ctrl_char_is_comma_o;
+ output [7:0] usr_rx4_ctrl_char_is_f_o;
+ output [7:0] usr_rx4_ctrl_char_is_k_o;
+ input usr_rx4_ctrl_dec_en_i;
+ output [7:0] usr_rx4_ctrl_disp_err_o;
+ input usr_rx4_ctrl_dscr_en_i;
+ input usr_rx4_ctrl_el_buff_fifo_en_i;
+ input usr_rx4_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx4_ctrl_not_in_table_o;
+ input [1:0] usr_rx4_ctrl_ovs_bit_sel_i;
+ input usr_rx4_ctrl_replace_en_i;
+ output [63:0] usr_rx4_data_o;
+ output usr_rx4_pll_lock_o;
+ input usr_rx4_pma_cdr_rst_i;
+ input usr_rx4_pma_ckgen_rst_n_i;
+ output usr_rx4_pma_loss_of_signal_o;
+ input usr_rx4_pma_pll_rst_n_i;
+ input usr_rx4_rst_n_i;
+ input [3:0] usr_rx4_test_i;
+ output [7:0] usr_rx4_test_o;
+ output usr_rx5_busy_o;
+ input usr_rx5_ctrl_align_en_i;
+ input usr_rx5_ctrl_align_sync_i;
+ output [7:0] usr_rx5_ctrl_char_is_a_o;
+ output usr_rx5_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx5_ctrl_char_is_comma_o;
+ output [7:0] usr_rx5_ctrl_char_is_f_o;
+ output [7:0] usr_rx5_ctrl_char_is_k_o;
+ input usr_rx5_ctrl_dec_en_i;
+ output [7:0] usr_rx5_ctrl_disp_err_o;
+ input usr_rx5_ctrl_dscr_en_i;
+ input usr_rx5_ctrl_el_buff_fifo_en_i;
+ input usr_rx5_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx5_ctrl_not_in_table_o;
+ input [1:0] usr_rx5_ctrl_ovs_bit_sel_i;
+ input usr_rx5_ctrl_replace_en_i;
+ output [63:0] usr_rx5_data_o;
+ output usr_rx5_pll_lock_o;
+ input usr_rx5_pma_cdr_rst_i;
+ input usr_rx5_pma_ckgen_rst_n_i;
+ output usr_rx5_pma_loss_of_signal_o;
+ input usr_rx5_pma_pll_rst_n_i;
+ input usr_rx5_rst_n_i;
+ input [3:0] usr_rx5_test_i;
+ output [7:0] usr_rx5_test_o;
+ output usr_tx0_busy_o;
+ input [7:0] usr_tx0_ctrl_char_is_k_i;
+ input [7:0] usr_tx0_ctrl_enc_en_i;
+ input [7:0] usr_tx0_ctrl_end_of_frame_i;
+ input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
+ input usr_tx0_ctrl_replace_en_i;
+ input [7:0] usr_tx0_ctrl_scr_en_i;
+ input [63:0] usr_tx0_data_i;
+ input usr_tx0_pma_clk_en_i;
+ input usr_tx0_rst_n_i;
+ input [3:0] usr_tx0_test_i;
+ output [3:0] usr_tx0_test_o;
+ output usr_tx1_busy_o;
+ input [7:0] usr_tx1_ctrl_char_is_k_i;
+ input [7:0] usr_tx1_ctrl_enc_en_i;
+ input [7:0] usr_tx1_ctrl_end_of_frame_i;
+ input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
+ input usr_tx1_ctrl_replace_en_i;
+ input [7:0] usr_tx1_ctrl_scr_en_i;
+ input [63:0] usr_tx1_data_i;
+ input usr_tx1_pma_clk_en_i;
+ input usr_tx1_rst_n_i;
+ input [3:0] usr_tx1_test_i;
+ output [3:0] usr_tx1_test_o;
+ output usr_tx2_busy_o;
+ input [7:0] usr_tx2_ctrl_char_is_k_i;
+ input [7:0] usr_tx2_ctrl_enc_en_i;
+ input [7:0] usr_tx2_ctrl_end_of_frame_i;
+ input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
+ input usr_tx2_ctrl_replace_en_i;
+ input [7:0] usr_tx2_ctrl_scr_en_i;
+ input [63:0] usr_tx2_data_i;
+ input usr_tx2_pma_clk_en_i;
+ input usr_tx2_rst_n_i;
+ input [3:0] usr_tx2_test_i;
+ output [3:0] usr_tx2_test_o;
+ output usr_tx3_busy_o;
+ input [7:0] usr_tx3_ctrl_char_is_k_i;
+ input [7:0] usr_tx3_ctrl_enc_en_i;
+ input [7:0] usr_tx3_ctrl_end_of_frame_i;
+ input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
+ input usr_tx3_ctrl_replace_en_i;
+ input [7:0] usr_tx3_ctrl_scr_en_i;
+ input [63:0] usr_tx3_data_i;
+ input usr_tx3_pma_clk_en_i;
+ input usr_tx3_rst_n_i;
+ input [3:0] usr_tx3_test_i;
+ output [3:0] usr_tx3_test_o;
+ output usr_tx4_busy_o;
+ input [7:0] usr_tx4_ctrl_char_is_k_i;
+ input [7:0] usr_tx4_ctrl_enc_en_i;
+ input [7:0] usr_tx4_ctrl_end_of_frame_i;
+ input [7:0] usr_tx4_ctrl_end_of_multiframe_i;
+ input usr_tx4_ctrl_replace_en_i;
+ input [7:0] usr_tx4_ctrl_scr_en_i;
+ input [63:0] usr_tx4_data_i;
+ input usr_tx4_pma_clk_en_i;
+ input usr_tx4_rst_n_i;
+ input [3:0] usr_tx4_test_i;
+ output [3:0] usr_tx4_test_o;
+ output usr_tx5_busy_o;
+ input [7:0] usr_tx5_ctrl_char_is_k_i;
+ input [7:0] usr_tx5_ctrl_enc_en_i;
+ input [7:0] usr_tx5_ctrl_end_of_frame_i;
+ input [7:0] usr_tx5_ctrl_end_of_multiframe_i;
+ input usr_tx5_ctrl_replace_en_i;
+ input [7:0] usr_tx5_ctrl_scr_en_i;
+ input [63:0] usr_tx5_data_i;
+ input usr_tx5_pma_clk_en_i;
+ input usr_tx5_rst_n_i;
+ input [3:0] usr_tx5_test_i;
+ output [3:0] usr_tx5_test_o;
+ parameter cfg_main_i = 34'b0000000000000000000000000000000000;
+ parameter cfg_rx0_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter cfg_rx1_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter cfg_rx2_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter cfg_rx3_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter cfg_rx4_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter cfg_rx5_i = 160'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
+ parameter cfg_tx0_i = 0;
+ parameter cfg_tx1_i = 0;
+ parameter cfg_tx2_i = 0;
+ parameter cfg_tx3_i = 0;
+ parameter cfg_tx4_i = 0;
+ parameter cfg_tx5_i = 0;
+ parameter location = "";
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_m.v b/techlibs/nanoxplore/cells_wrap_m.v
new file mode 100644
index 000000000..ff4c011c7
--- /dev/null
+++ b/techlibs/nanoxplore/cells_wrap_m.v
@@ -0,0 +1,1501 @@
+module NX_DSP_SPLIT(CK, R, RZ, WE, CI, CCI, CO, CO36, CO48, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO , CZO);
+ input [23:0] A;
+ input [17:0] B;
+ input [35:0] C;
+ input [17:0] CAI;
+ output [17:0] CAO;
+ input [17:0] CBI;
+ output [17:0] CBO;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO;
+ output CO36;
+ output CO48;
+ input [55:0] CZI;
+ output [55:0] CZO;
+ input [17:0] D;
+ output OVF;
+ input R;
+ input RZ;
+ input WE;
+ output [55:0] Z;
+ parameter ALU_DYNAMIC_OP = 1'b0;
+ parameter ALU_MUX = 1'b0;
+ parameter ALU_OP = 6'b000000;
+ parameter CO_SEL = 1'b0;
+ parameter ENABLE_PR_ALU_RST = 1'b0;
+ parameter ENABLE_PR_A_RST = 1'b0;
+ parameter ENABLE_PR_B_RST = 1'b0;
+ parameter ENABLE_PR_CI_RST = 1'b0;
+ parameter ENABLE_PR_CO_RST = 1'b0;
+ parameter ENABLE_PR_C_RST = 1'b0;
+ parameter ENABLE_PR_D_RST = 1'b0;
+ parameter ENABLE_PR_MULT_RST = 1'b0;
+ parameter ENABLE_PR_OV_RST = 1'b0;
+ parameter ENABLE_PR_P_RST = 1'b0;
+ parameter ENABLE_PR_X_RST = 1'b0;
+ parameter ENABLE_PR_Y_RST = 1'b0;
+ parameter ENABLE_PR_Z_RST = 1'b0;
+ parameter ENABLE_SATURATION = 1'b0;
+ parameter MUX_A = 1'b0;
+ parameter MUX_B = 1'b0;
+ parameter MUX_CI = 1'b0;
+ parameter MUX_P = 1'b0;
+ parameter MUX_X = 2'b00;
+ parameter MUX_Y = 1'b0;
+ parameter MUX_Z = 1'b0;
+ parameter PRE_ADDER_OP = 1'b0;
+ parameter PR_ALU_MUX = 1'b0;
+ parameter PR_A_CASCADE_MUX = 2'b00;
+ parameter PR_A_MUX = 2'b00;
+ parameter PR_B_CASCADE_MUX = 2'b00;
+ parameter PR_B_MUX = 2'b00;
+ parameter PR_CI_MUX = 1'b0;
+ parameter PR_CO_MUX = 1'b0;
+ parameter PR_C_MUX = 1'b0;
+ parameter PR_D_MUX = 1'b0;
+ parameter PR_MULT_MUX = 1'b0;
+ parameter PR_OV_MUX = 1'b0;
+ parameter PR_P_MUX = 1'b0;
+ parameter PR_X_MUX = 1'b0;
+ parameter PR_Y_MUX = 1'b0;
+ parameter PR_Z_MUX = 1'b0;
+ parameter SATURATION_RANK = 6'b000000;
+ parameter SIGNED_MODE = 1'b0;
+ parameter Z_FEEDBACK_SHL12 = 1'b0;
+
+localparam RAW_CONFIG0_GEN = { CO_SEL, ALU_DYNAMIC_OP, SATURATION_RANK, ENABLE_SATURATION, Z_FEEDBACK_SHL12, MUX_Z,
+ MUX_CI, MUX_Y, MUX_X, MUX_P, MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };
+
+localparam RAW_CONFIG1_GEN = { PR_OV_MUX, PR_CO_MUX, PR_Z_MUX, PR_ALU_MUX, PR_MULT_MUX, PR_Y_MUX, PR_X_MUX,
+ PR_P_MUX, PR_CI_MUX, PR_D_MUX, PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };
+
+localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_Z_RST, ENABLE_PR_ALU_RST,
+ ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,
+ ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };
+
+localparam RAW_CONFIG3_GEN = { ALU_MUX, ALU_OP };
+
+ NX_DSP #(
+ .std_mode(""),
+ .raw_config0(RAW_CONFIG0_GEN),
+ .raw_config1(RAW_CONFIG1_GEN),
+ .raw_config2(RAW_CONFIG2_GEN),
+ .raw_config3(RAW_CONFIG3_GEN),
+ ) _TECHMAP_REPLACE_ (
+ .A1(A[0]),
+ .A2(A[1]),
+ .A3(A[2]),
+ .A4(A[3]),
+ .A5(A[4]),
+ .A6(A[5]),
+ .A7(A[6]),
+ .A8(A[7]),
+ .A9(A[8]),
+ .A10(A[9]),
+ .A11(A[10]),
+ .A12(A[11]),
+ .A13(A[12]),
+ .A14(A[13]),
+ .A15(A[14]),
+ .A16(A[15]),
+ .A17(A[16]),
+ .A18(A[17]),
+ .A19(A[18]),
+ .A20(A[19]),
+ .A21(A[20]),
+ .A22(A[21]),
+ .A23(A[22]),
+ .A24(A[23]),
+
+ .B1(B[0]),
+ .B2(B[1]),
+ .B3(B[2]),
+ .B4(B[3]),
+ .B5(B[4]),
+ .B6(B[5]),
+ .B7(B[6]),
+ .B8(B[7]),
+ .B9(B[8]),
+ .B10(B[9]),
+ .B11(B[10]),
+ .B12(B[11]),
+ .B13(B[12]),
+ .B14(B[13]),
+ .B15(B[14]),
+ .B16(B[15]),
+ .B17(B[16]),
+ .B18(B[17]),
+
+ .C1(C[0]),
+ .C2(C[1]),
+ .C3(C[2]),
+ .C4(C[3]),
+ .C5(C[4]),
+ .C6(C[5]),
+ .C7(C[6]),
+ .C8(C[7]),
+ .C9(C[8]),
+ .C10(C[9]),
+ .C11(C[10]),
+ .C12(C[11]),
+ .C13(C[12]),
+ .C14(C[13]),
+ .C15(C[14]),
+ .C16(C[15]),
+ .C17(C[16]),
+ .C18(C[17]),
+ .C19(C[18]),
+ .C20(C[19]),
+ .C21(C[20]),
+ .C22(C[21]),
+ .C23(C[22]),
+ .C24(C[23]),
+ .C25(C[24]),
+ .C26(C[25]),
+ .C27(C[26]),
+ .C28(C[27]),
+ .C29(C[28]),
+ .C30(C[29]),
+ .C31(C[30]),
+ .C32(C[31]),
+ .C33(C[32]),
+ .C34(C[33]),
+ .C35(C[34]),
+ .C36(C[35]),
+
+ .CAI1(CAI[0]),
+ .CAI2(CAI[1]),
+ .CAI3(CAI[2]),
+ .CAI4(CAI[3]),
+ .CAI5(CAI[4]),
+ .CAI6(CAI[5]),
+ .CAI7(CAI[6]),
+ .CAI8(CAI[7]),
+ .CAI9(CAI[8]),
+ .CAI10(CAI[9]),
+ .CAI11(CAI[10]),
+ .CAI12(CAI[11]),
+ .CAI13(CAI[12]),
+ .CAI14(CAI[13]),
+ .CAI15(CAI[14]),
+ .CAI16(CAI[15]),
+ .CAI17(CAI[16]),
+ .CAI18(CAI[17]),
+
+ .CAO1(CAO[0]),
+ .CAO2(CAO[1]),
+ .CAO3(CAO[2]),
+ .CAO4(CAO[3]),
+ .CAO5(CAO[4]),
+ .CAO6(CAO[5]),
+ .CAO7(CAO[6]),
+ .CAO8(CAO[7]),
+ .CAO9(CAO[8]),
+ .CAO10(CAO[9]),
+ .CAO11(CAO[10]),
+ .CAO12(CAO[11]),
+ .CAO13(CAO[12]),
+ .CAO14(CAO[13]),
+ .CAO15(CAO[14]),
+ .CAO16(CAO[15]),
+ .CAO17(CAO[16]),
+ .CAO18(CAO[17]),
+
+ .CBI1(CBI[0]),
+ .CBI2(CBI[1]),
+ .CBI3(CBI[2]),
+ .CBI4(CBI[3]),
+ .CBI5(CBI[4]),
+ .CBI6(CBI[5]),
+ .CBI7(CBI[6]),
+ .CBI8(CBI[7]),
+ .CBI9(CBI[8]),
+ .CBI10(CBI[9]),
+ .CBI11(CBI[10]),
+ .CBI12(CBI[11]),
+ .CBI13(CBI[12]),
+ .CBI14(CBI[13]),
+ .CBI15(CBI[14]),
+ .CBI16(CBI[15]),
+ .CBI17(CBI[16]),
+ .CBI18(CBI[17]),
+
+ .CBO1(CBO[0]),
+ .CBO2(CBO[1]),
+ .CBO3(CBO[2]),
+ .CBO4(CBO[3]),
+ .CBO5(CBO[4]),
+ .CBO6(CBO[5]),
+ .CBO7(CBO[6]),
+ .CBO8(CBO[7]),
+ .CBO9(CBO[8]),
+ .CBO10(CBO[9]),
+ .CBO11(CBO[10]),
+ .CBO12(CBO[11]),
+ .CBO13(CBO[12]),
+ .CBO14(CBO[13]),
+ .CBO15(CBO[14]),
+ .CBO16(CBO[15]),
+ .CBO17(CBO[16]),
+ .CBO18(CBO[17]),
+
+ .CCI(CCI),
+ .CCO(CCO),
+ .CI(CI),
+ .CK(CK),
+ .CO(CO),
+ .CO37(CO36),
+ .CO49(CO48),
+
+ .CZI1(CZI[0]),
+ .CZI2(CZI[1]),
+ .CZI3(CZI[2]),
+ .CZI4(CZI[3]),
+ .CZI5(CZI[4]),
+ .CZI6(CZI[5]),
+ .CZI7(CZI[6]),
+ .CZI8(CZI[7]),
+ .CZI9(CZI[8]),
+ .CZI10(CZI[9]),
+ .CZI11(CZI[10]),
+ .CZI12(CZI[11]),
+ .CZI13(CZI[12]),
+ .CZI14(CZI[13]),
+ .CZI15(CZI[14]),
+ .CZI16(CZI[15]),
+ .CZI17(CZI[16]),
+ .CZI18(CZI[17]),
+ .CZI19(CZI[18]),
+ .CZI20(CZI[19]),
+ .CZI21(CZI[20]),
+ .CZI22(CZI[21]),
+ .CZI23(CZI[22]),
+ .CZI24(CZI[23]),
+ .CZI25(CZI[24]),
+ .CZI26(CZI[25]),
+ .CZI27(CZI[26]),
+ .CZI28(CZI[27]),
+ .CZI29(CZI[28]),
+ .CZI30(CZI[29]),
+ .CZI31(CZI[30]),
+ .CZI32(CZI[31]),
+ .CZI33(CZI[32]),
+ .CZI34(CZI[33]),
+ .CZI35(CZI[34]),
+ .CZI36(CZI[35]),
+ .CZI37(CZI[36]),
+ .CZI38(CZI[37]),
+ .CZI39(CZI[38]),
+ .CZI40(CZI[39]),
+ .CZI41(CZI[40]),
+ .CZI42(CZI[41]),
+ .CZI43(CZI[42]),
+ .CZI44(CZI[43]),
+ .CZI45(CZI[44]),
+ .CZI46(CZI[45]),
+ .CZI47(CZI[46]),
+ .CZI48(CZI[47]),
+ .CZI49(CZI[48]),
+ .CZI50(CZI[49]),
+ .CZI51(CZI[50]),
+ .CZI52(CZI[51]),
+ .CZI53(CZI[52]),
+ .CZI54(CZI[53]),
+ .CZI55(CZI[54]),
+ .CZI56(CZI[55]),
+
+ .CZO1(CZO[0]),
+ .CZO2(CZO[1]),
+ .CZO3(CZO[2]),
+ .CZO4(CZO[3]),
+ .CZO5(CZO[4]),
+ .CZO6(CZO[5]),
+ .CZO7(CZO[6]),
+ .CZO8(CZO[7]),
+ .CZO9(CZO[8]),
+ .CZO10(CZO[9]),
+ .CZO11(CZO[10]),
+ .CZO12(CZO[11]),
+ .CZO13(CZO[12]),
+ .CZO14(CZO[13]),
+ .CZO15(CZO[14]),
+ .CZO16(CZO[15]),
+ .CZO17(CZO[16]),
+ .CZO18(CZO[17]),
+ .CZO19(CZO[18]),
+ .CZO20(CZO[19]),
+ .CZO21(CZO[20]),
+ .CZO22(CZO[21]),
+ .CZO23(CZO[22]),
+ .CZO24(CZO[23]),
+ .CZO25(CZO[24]),
+ .CZO26(CZO[25]),
+ .CZO27(CZO[26]),
+ .CZO28(CZO[27]),
+ .CZO29(CZO[28]),
+ .CZO30(CZO[29]),
+ .CZO31(CZO[30]),
+ .CZO32(CZO[31]),
+ .CZO33(CZO[32]),
+ .CZO34(CZO[33]),
+ .CZO35(CZO[34]),
+ .CZO36(CZO[35]),
+ .CZO37(CZO[36]),
+ .CZO38(CZO[37]),
+ .CZO39(CZO[38]),
+ .CZO40(CZO[39]),
+ .CZO41(CZO[40]),
+ .CZO42(CZO[41]),
+ .CZO43(CZO[42]),
+ .CZO44(CZO[43]),
+ .CZO45(CZO[44]),
+ .CZO46(CZO[45]),
+ .CZO47(CZO[46]),
+ .CZO48(CZO[47]),
+ .CZO49(CZO[48]),
+ .CZO50(CZO[49]),
+ .CZO51(CZO[50]),
+ .CZO52(CZO[51]),
+ .CZO53(CZO[52]),
+ .CZO54(CZO[53]),
+ .CZO55(CZO[54]),
+ .CZO56(CZO[55]),
+
+ .D1(D[0]),
+ .D2(D[1]),
+ .D3(D[2]),
+ .D4(D[3]),
+ .D5(D[4]),
+ .D6(D[5]),
+ .D7(D[6]),
+ .D8(D[7]),
+ .D9(D[8]),
+ .D10(D[9]),
+ .D11(D[10]),
+ .D12(D[11]),
+ .D13(D[12]),
+ .D14(D[13]),
+ .D15(D[14]),
+ .D16(D[15]),
+ .D17(D[16]),
+ .D18(D[17]),
+
+ .OVF(OVF),
+ .R(R),
+ .RZ(RZ),
+ .WE(WE),
+
+ .Z1(Z[0]),
+ .Z2(Z[1]),
+ .Z3(Z[2]),
+ .Z4(Z[3]),
+ .Z5(Z[4]),
+ .Z6(Z[5]),
+ .Z7(Z[6]),
+ .Z8(Z[7]),
+ .Z9(Z[8]),
+ .Z10(Z[9]),
+ .Z11(Z[10]),
+ .Z12(Z[11]),
+ .Z13(Z[12]),
+ .Z14(Z[13]),
+ .Z15(Z[14]),
+ .Z16(Z[15]),
+ .Z17(Z[16]),
+ .Z18(Z[17]),
+ .Z19(Z[18]),
+ .Z20(Z[19]),
+ .Z21(Z[20]),
+ .Z22(Z[21]),
+ .Z23(Z[22]),
+ .Z24(Z[23]),
+ .Z25(Z[24]),
+ .Z26(Z[25]),
+ .Z27(Z[26]),
+ .Z28(Z[27]),
+ .Z29(Z[28]),
+ .Z30(Z[29]),
+ .Z31(Z[30]),
+ .Z32(Z[31]),
+ .Z33(Z[32]),
+ .Z34(Z[33]),
+ .Z35(Z[34]),
+ .Z36(Z[35]),
+ .Z37(Z[36]),
+ .Z38(Z[37]),
+ .Z39(Z[38]),
+ .Z40(Z[39]),
+ .Z41(Z[40]),
+ .Z42(Z[41]),
+ .Z43(Z[42]),
+ .Z44(Z[43]),
+ .Z45(Z[44]),
+ .Z46(Z[45]),
+ .Z47(Z[46]),
+ .Z48(Z[47]),
+ .Z49(Z[48]),
+ .Z50(Z[49]),
+ .Z51(Z[50]),
+ .Z52(Z[51]),
+ .Z53(Z[52]),
+ .Z54(Z[53]),
+ .Z55(Z[54]),
+ .Z56(Z[55])
+ );
+endmodule
+
+module NX_DSP_WRAP(CCI, CCO, CI, CK, CO, CO37, CO49, OVF, R, RZ, WE, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+ input [23:0] A;
+ input [17:0] B;
+ input [35:0] C;
+ input [17:0] CAI;
+ output [17:0] CAO;
+ input [17:0] CBI;
+ output [17:0] CBO;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO;
+ output CO37;
+ output CO49;
+ input [55:0] CZI;
+ output [55:0] CZO;
+ input [17:0] D;
+ output OVF;
+ input R;
+ input RZ;
+ input WE;
+ output [55:0] Z;
+ parameter raw_config0 = 20'b00000000000000000000;
+ parameter raw_config1 = 19'b0000000000000000000;
+ parameter raw_config2 = 13'b0000000000000;
+ parameter raw_config3 = 7'b0000000;
+ parameter std_mode = "";
+
+ NX_DSP #(
+ .std_mode(std_mode),
+ .raw_config0(raw_config0),
+ .raw_config1(raw_config1),
+ .raw_config2(raw_config2),
+ .raw_config3(raw_config3),
+ ) _TECHMAP_REPLACE_ (
+ .A1(A[0]),
+ .A2(A[1]),
+ .A3(A[2]),
+ .A4(A[3]),
+ .A5(A[4]),
+ .A6(A[5]),
+ .A7(A[6]),
+ .A8(A[7]),
+ .A9(A[8]),
+ .A10(A[9]),
+ .A11(A[10]),
+ .A12(A[11]),
+ .A13(A[12]),
+ .A14(A[13]),
+ .A15(A[14]),
+ .A16(A[15]),
+ .A17(A[16]),
+ .A18(A[17]),
+ .A19(A[18]),
+ .A20(A[19]),
+ .A21(A[20]),
+ .A22(A[21]),
+ .A23(A[22]),
+ .A24(A[23]),
+
+ .B1(B[0]),
+ .B2(B[1]),
+ .B3(B[2]),
+ .B4(B[3]),
+ .B5(B[4]),
+ .B6(B[5]),
+ .B7(B[6]),
+ .B8(B[7]),
+ .B9(B[8]),
+ .B10(B[9]),
+ .B11(B[10]),
+ .B12(B[11]),
+ .B13(B[12]),
+ .B14(B[13]),
+ .B15(B[14]),
+ .B16(B[15]),
+ .B17(B[16]),
+ .B18(B[17]),
+
+ .C1(C[0]),
+ .C2(C[1]),
+ .C3(C[2]),
+ .C4(C[3]),
+ .C5(C[4]),
+ .C6(C[5]),
+ .C7(C[6]),
+ .C8(C[7]),
+ .C9(C[8]),
+ .C10(C[9]),
+ .C11(C[10]),
+ .C12(C[11]),
+ .C13(C[12]),
+ .C14(C[13]),
+ .C15(C[14]),
+ .C16(C[15]),
+ .C17(C[16]),
+ .C18(C[17]),
+ .C19(C[18]),
+ .C20(C[19]),
+ .C21(C[20]),
+ .C22(C[21]),
+ .C23(C[22]),
+ .C24(C[23]),
+ .C25(C[24]),
+ .C26(C[25]),
+ .C27(C[26]),
+ .C28(C[27]),
+ .C29(C[28]),
+ .C30(C[29]),
+ .C31(C[30]),
+ .C32(C[31]),
+ .C33(C[32]),
+ .C34(C[33]),
+ .C35(C[34]),
+ .C36(C[35]),
+
+ .CAI1(CAI[0]),
+ .CAI2(CAI[1]),
+ .CAI3(CAI[2]),
+ .CAI4(CAI[3]),
+ .CAI5(CAI[4]),
+ .CAI6(CAI[5]),
+ .CAI7(CAI[6]),
+ .CAI8(CAI[7]),
+ .CAI9(CAI[8]),
+ .CAI10(CAI[9]),
+ .CAI11(CAI[10]),
+ .CAI12(CAI[11]),
+ .CAI13(CAI[12]),
+ .CAI14(CAI[13]),
+ .CAI15(CAI[14]),
+ .CAI16(CAI[15]),
+ .CAI17(CAI[16]),
+ .CAI18(CAI[17]),
+
+ .CAO1(CAO[0]),
+ .CAO2(CAO[1]),
+ .CAO3(CAO[2]),
+ .CAO4(CAO[3]),
+ .CAO5(CAO[4]),
+ .CAO6(CAO[5]),
+ .CAO7(CAO[6]),
+ .CAO8(CAO[7]),
+ .CAO9(CAO[8]),
+ .CAO10(CAO[9]),
+ .CAO11(CAO[10]),
+ .CAO12(CAO[11]),
+ .CAO13(CAO[12]),
+ .CAO14(CAO[13]),
+ .CAO15(CAO[14]),
+ .CAO16(CAO[15]),
+ .CAO17(CAO[16]),
+ .CAO18(CAO[17]),
+
+ .CBI1(CBI[0]),
+ .CBI2(CBI[1]),
+ .CBI3(CBI[2]),
+ .CBI4(CBI[3]),
+ .CBI5(CBI[4]),
+ .CBI6(CBI[5]),
+ .CBI7(CBI[6]),
+ .CBI8(CBI[7]),
+ .CBI9(CBI[8]),
+ .CBI10(CBI[9]),
+ .CBI11(CBI[10]),
+ .CBI12(CBI[11]),
+ .CBI13(CBI[12]),
+ .CBI14(CBI[13]),
+ .CBI15(CBI[14]),
+ .CBI16(CBI[15]),
+ .CBI17(CBI[16]),
+ .CBI18(CBI[17]),
+
+ .CBO1(CBO[0]),
+ .CBO2(CBO[1]),
+ .CBO3(CBO[2]),
+ .CBO4(CBO[3]),
+ .CBO5(CBO[4]),
+ .CBO6(CBO[5]),
+ .CBO7(CBO[6]),
+ .CBO8(CBO[7]),
+ .CBO9(CBO[8]),
+ .CBO10(CBO[9]),
+ .CBO11(CBO[10]),
+ .CBO12(CBO[11]),
+ .CBO13(CBO[12]),
+ .CBO14(CBO[13]),
+ .CBO15(CBO[14]),
+ .CBO16(CBO[15]),
+ .CBO17(CBO[16]),
+ .CBO18(CBO[17]),
+
+ .CCI(CCI),
+ .CCO(CCO),
+ .CI(CI),
+ .CK(CK),
+ .CO(CO),
+ .CO37(CO37),
+ .CO49(CO49),
+
+ .CZI1(CZI[0]),
+ .CZI2(CZI[1]),
+ .CZI3(CZI[2]),
+ .CZI4(CZI[3]),
+ .CZI5(CZI[4]),
+ .CZI6(CZI[5]),
+ .CZI7(CZI[6]),
+ .CZI8(CZI[7]),
+ .CZI9(CZI[8]),
+ .CZI10(CZI[9]),
+ .CZI11(CZI[10]),
+ .CZI12(CZI[11]),
+ .CZI13(CZI[12]),
+ .CZI14(CZI[13]),
+ .CZI15(CZI[14]),
+ .CZI16(CZI[15]),
+ .CZI17(CZI[16]),
+ .CZI18(CZI[17]),
+ .CZI19(CZI[18]),
+ .CZI20(CZI[19]),
+ .CZI21(CZI[20]),
+ .CZI22(CZI[21]),
+ .CZI23(CZI[22]),
+ .CZI24(CZI[23]),
+ .CZI25(CZI[24]),
+ .CZI26(CZI[25]),
+ .CZI27(CZI[26]),
+ .CZI28(CZI[27]),
+ .CZI29(CZI[28]),
+ .CZI30(CZI[29]),
+ .CZI31(CZI[30]),
+ .CZI32(CZI[31]),
+ .CZI33(CZI[32]),
+ .CZI34(CZI[33]),
+ .CZI35(CZI[34]),
+ .CZI36(CZI[35]),
+ .CZI37(CZI[36]),
+ .CZI38(CZI[37]),
+ .CZI39(CZI[38]),
+ .CZI40(CZI[39]),
+ .CZI41(CZI[40]),
+ .CZI42(CZI[41]),
+ .CZI43(CZI[42]),
+ .CZI44(CZI[43]),
+ .CZI45(CZI[44]),
+ .CZI46(CZI[45]),
+ .CZI47(CZI[46]),
+ .CZI48(CZI[47]),
+ .CZI49(CZI[48]),
+ .CZI50(CZI[49]),
+ .CZI51(CZI[50]),
+ .CZI52(CZI[51]),
+ .CZI53(CZI[52]),
+ .CZI54(CZI[53]),
+ .CZI55(CZI[54]),
+ .CZI56(CZI[55]),
+
+ .CZO1(CZO[0]),
+ .CZO2(CZO[1]),
+ .CZO3(CZO[2]),
+ .CZO4(CZO[3]),
+ .CZO5(CZO[4]),
+ .CZO6(CZO[5]),
+ .CZO7(CZO[6]),
+ .CZO8(CZO[7]),
+ .CZO9(CZO[8]),
+ .CZO10(CZO[9]),
+ .CZO11(CZO[10]),
+ .CZO12(CZO[11]),
+ .CZO13(CZO[12]),
+ .CZO14(CZO[13]),
+ .CZO15(CZO[14]),
+ .CZO16(CZO[15]),
+ .CZO17(CZO[16]),
+ .CZO18(CZO[17]),
+ .CZO19(CZO[18]),
+ .CZO20(CZO[19]),
+ .CZO21(CZO[20]),
+ .CZO22(CZO[21]),
+ .CZO23(CZO[22]),
+ .CZO24(CZO[23]),
+ .CZO25(CZO[24]),
+ .CZO26(CZO[25]),
+ .CZO27(CZO[26]),
+ .CZO28(CZO[27]),
+ .CZO29(CZO[28]),
+ .CZO30(CZO[29]),
+ .CZO31(CZO[30]),
+ .CZO32(CZO[31]),
+ .CZO33(CZO[32]),
+ .CZO34(CZO[33]),
+ .CZO35(CZO[34]),
+ .CZO36(CZO[35]),
+ .CZO37(CZO[36]),
+ .CZO38(CZO[37]),
+ .CZO39(CZO[38]),
+ .CZO40(CZO[39]),
+ .CZO41(CZO[40]),
+ .CZO42(CZO[41]),
+ .CZO43(CZO[42]),
+ .CZO44(CZO[43]),
+ .CZO45(CZO[44]),
+ .CZO46(CZO[45]),
+ .CZO47(CZO[46]),
+ .CZO48(CZO[47]),
+ .CZO49(CZO[48]),
+ .CZO50(CZO[49]),
+ .CZO51(CZO[50]),
+ .CZO52(CZO[51]),
+ .CZO53(CZO[52]),
+ .CZO54(CZO[53]),
+ .CZO55(CZO[54]),
+ .CZO56(CZO[55]),
+
+ .D1(D[0]),
+ .D2(D[1]),
+ .D3(D[2]),
+ .D4(D[3]),
+ .D5(D[4]),
+ .D6(D[5]),
+ .D7(D[6]),
+ .D8(D[7]),
+ .D9(D[8]),
+ .D10(D[9]),
+ .D11(D[10]),
+ .D12(D[11]),
+ .D13(D[12]),
+ .D14(D[13]),
+ .D15(D[14]),
+ .D16(D[15]),
+ .D17(D[16]),
+ .D18(D[17]),
+
+ .OVF(OVF),
+ .R(R),
+ .RZ(RZ),
+ .WE(WE),
+
+ .Z1(Z[0]),
+ .Z2(Z[1]),
+ .Z3(Z[2]),
+ .Z4(Z[3]),
+ .Z5(Z[4]),
+ .Z6(Z[5]),
+ .Z7(Z[6]),
+ .Z8(Z[7]),
+ .Z9(Z[8]),
+ .Z10(Z[9]),
+ .Z11(Z[10]),
+ .Z12(Z[11]),
+ .Z13(Z[12]),
+ .Z14(Z[13]),
+ .Z15(Z[14]),
+ .Z16(Z[15]),
+ .Z17(Z[16]),
+ .Z18(Z[17]),
+ .Z19(Z[18]),
+ .Z20(Z[19]),
+ .Z21(Z[20]),
+ .Z22(Z[21]),
+ .Z23(Z[22]),
+ .Z24(Z[23]),
+ .Z25(Z[24]),
+ .Z26(Z[25]),
+ .Z27(Z[26]),
+ .Z28(Z[27]),
+ .Z29(Z[28]),
+ .Z30(Z[29]),
+ .Z31(Z[30]),
+ .Z32(Z[31]),
+ .Z33(Z[32]),
+ .Z34(Z[33]),
+ .Z35(Z[34]),
+ .Z36(Z[35]),
+ .Z37(Z[36]),
+ .Z38(Z[37]),
+ .Z39(Z[38]),
+ .Z40(Z[39]),
+ .Z41(Z[40]),
+ .Z42(Z[41]),
+ .Z43(Z[42]),
+ .Z44(Z[43]),
+ .Z45(Z[44]),
+ .Z46(Z[45]),
+ .Z47(Z[46]),
+ .Z48(Z[47]),
+ .Z49(Z[48]),
+ .Z50(Z[49]),
+ .Z51(Z[50]),
+ .Z52(Z[51]),
+ .Z53(Z[52]),
+ .Z54(Z[53]),
+ .Z55(Z[54]),
+ .Z56(Z[55])
+ );
+endmodule
+
+module NX_RFB_WRAP(RCK, WCK, COR, ERR, RE, WE, I, O, RA, WA);
+ output COR;
+ output ERR;
+ input [15:0] I;
+ output [15:0] O;
+ input [5:0] RA;
+ input RCK;
+ input RE;
+ input [5:0] WA;
+ input WCK;
+ input WE;
+ parameter mem_ctxt = "";
+ parameter rck_edge = 1'b0;
+ parameter wck_edge = 1'b0;
+
+ NX_RFB_M #(
+ .mem_ctxt(mem_ctxt),
+ .rck_edge(rck_edge),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(RCK),
+ .WCK(WCK),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .COR(COR),
+ .ERR(ERR),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .RA1(RA[0]),
+ .RA2(RA[1]),
+ .RA3(RA[2]),
+ .RA4(RA[3]),
+ .RA5(RA[4]),
+ .RA6(RA[5]),
+ .RE(RE),
+ .WA1(WA[0]),
+ .WA2(WA[1]),
+ .WA3(WA[2]),
+ .WA4(WA[3]),
+ .WA5(WA[4]),
+ .WA6(WA[5]),
+ .WE(WE)
+ );
+endmodule
+
+module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+ output COR;
+ output ERR;
+ input I1;
+ input I10;
+ input I11;
+ input I12;
+ input I13;
+ input I14;
+ input I15;
+ input I16;
+ input I2;
+ input I3;
+ input I4;
+ input I5;
+ input I6;
+ input I7;
+ input I8;
+ input I9;
+ output O1;
+ output O10;
+ output O11;
+ output O12;
+ output O13;
+ output O14;
+ output O15;
+ output O16;
+ output O2;
+ output O3;
+ output O4;
+ output O5;
+ output O6;
+ output O7;
+ output O8;
+ output O9;
+ input RA1;
+ input RA2;
+ input RA3;
+ input RA4;
+ input RA5;
+ input RA6;
+ input RCK;
+ input RE;
+ input WA1;
+ input WA2;
+ input WA3;
+ input WA4;
+ input WA5;
+ input WA6;
+ input WCK;
+ input WE;
+ parameter addr_mask = 5'b00000;
+ parameter mem_ctxt = "";
+ parameter rck_edge = 1'b0;
+ parameter wck_edge = 1'b0;
+ parameter we_mask = 1'b0;
+ parameter wea_mask = 1'b0;
+
+ NX_RFB_M #(
+ .mem_ctxt(mem_ctxt),
+ .rck_edge(rck_edge),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(RCK),
+ .WCK(WCK),
+ .I1(I1),
+ .I2(I2),
+ .I3(I3),
+ .I4(I4),
+ .I5(I5),
+ .I6(I6),
+ .I7(I7),
+ .I8(I8),
+ .I9(I9),
+ .I10(I10),
+ .I11(I11),
+ .I12(I12),
+ .I13(I13),
+ .I14(I14),
+ .I15(I15),
+ .I16(I16),
+ .COR(COR),
+ .ERR(ERR),
+ .O1(O1),
+ .O2(O2),
+ .O3(O3),
+ .O4(O4),
+ .O5(O5),
+ .O6(O6),
+ .O7(O7),
+ .O8(O8),
+ .O9(O9),
+ .O10(O10),
+ .O11(O11),
+ .O12(O12),
+ .O13(O13),
+ .O14(O14),
+ .O15(O15),
+ .O16(O16),
+ .RA1(RA1),
+ .RA2(RA2),
+ .RA3(RA3),
+ .RA4(RA4),
+ .RA5(RA5),
+ .RA6(RA6),
+ .RE(RE),
+ .WA1(WA1),
+ .WA2(WA2),
+ .WA3(WA3),
+ .WA4(WA4),
+ .WA5(WA5),
+ .WA6(WA6),
+ .WE(WE)
+ );
+endmodule
+
+module NX_IOM_CONTROL(RTCK1, RRCK1, WTCK1, WRCK1, RTCK2, RRCK2, WTCK2, WRCK2, CTCK, C1TW, C1TS, C1RW1, C1RW2, C1RW3, C1RNE, C1RS, C2TW, C2TS, C2RW1, C2RW2, C2RW3
+, C2RNE, C2RS, FA1, FA2, FA3, FA4, FA5, FA6, FZ, DC, CCK, DCK, DRI1, DRI2, DRI3, DRI4, DRI5, DRI6, DRA1, DRA2, DRA3
+, DRA4, DRA5, DRA6, DRL, DOS, DOG, DIS, DIG, DPAS, DPAG, DQSS, DQSG, DS1, DS2, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CAP1
+, CAP2, CAP3, CAP4, CAN1, CAN2, CAN3, CAN4, CAT1, CAT2, CAT3, CAT4, SPI1, SPI2, SPI3, CKO1, CKO2, FLD, FLG, C1RED, C2RED, DRO1
+, DRO2, DRO3, DRO4, DRO5, DRO6, CAL, LINK2, LINK3, LINK4, LINK5, LINK6, LINK7, LINK8, LINK9, LINK10, LINK11, LINK12, LINK13, LINK14, LINK15, LINK16
+, LINK17, LINK18, LINK19, LINK20, LINK21, LINK22, LINK23, LINK24, LINK25, LINK26, LINK27, LINK28, LINK29, LINK30, LINK31, LINK32, LINK33, LINK34, LINK1);
+ output C1RED;
+ input C1RNE;
+ input C1RS;
+ input C1RW1;
+ input C1RW2;
+ input C1RW3;
+ input C1TS;
+ input C1TW;
+ output C2RED;
+ input C2RNE;
+ input C2RS;
+ input C2RW1;
+ input C2RW2;
+ input C2RW3;
+ input C2TS;
+ input C2TW;
+ input CAD1;
+ input CAD2;
+ input CAD3;
+ input CAD4;
+ input CAD5;
+ input CAD6;
+ output CAL;
+ input CAN1;
+ input CAN2;
+ input CAN3;
+ input CAN4;
+ input CAP1;
+ input CAP2;
+ input CAP3;
+ input CAP4;
+ input CAT1;
+ input CAT2;
+ input CAT3;
+ input CAT4;
+ input CCK;
+ output CKO1;
+ output CKO2;
+ input CTCK;
+ input DC;
+ input DCK;
+ input DIG;
+ input DIS;
+ input DOG;
+ input DOS;
+ input DPAG;
+ input DPAS;
+ input DQSG;
+ input DQSS;
+ input DRA1;
+ input DRA2;
+ input DRA3;
+ input DRA4;
+ input DRA5;
+ input DRA6;
+ input DRI1;
+ input DRI2;
+ input DRI3;
+ input DRI4;
+ input DRI5;
+ input DRI6;
+ input DRL;
+ output DRO1;
+ output DRO2;
+ output DRO3;
+ output DRO4;
+ output DRO5;
+ output DRO6;
+ input DS1;
+ input DS2;
+ input FA1;
+ input FA2;
+ input FA3;
+ input FA4;
+ input FA5;
+ input FA6;
+ output FLD;
+ output FLG;
+ input FZ;
+ inout [41:0] LINK1;
+ inout [41:0] LINK10;
+ inout [41:0] LINK11;
+ inout [41:0] LINK12;
+ inout [41:0] LINK13;
+ inout [41:0] LINK14;
+ inout [41:0] LINK15;
+ inout [41:0] LINK16;
+ inout [41:0] LINK17;
+ inout [41:0] LINK18;
+ inout [41:0] LINK19;
+ inout [41:0] LINK2;
+ inout [41:0] LINK20;
+ inout [41:0] LINK21;
+ inout [41:0] LINK22;
+ inout [41:0] LINK23;
+ inout [41:0] LINK24;
+ inout [41:0] LINK25;
+ inout [41:0] LINK26;
+ inout [41:0] LINK27;
+ inout [41:0] LINK28;
+ inout [41:0] LINK29;
+ inout [41:0] LINK3;
+ inout [41:0] LINK30;
+ inout [41:0] LINK31;
+ inout [41:0] LINK32;
+ inout [41:0] LINK33;
+ inout [41:0] LINK34;
+ inout [41:0] LINK4;
+ inout [41:0] LINK5;
+ inout [41:0] LINK6;
+ inout [41:0] LINK7;
+ inout [41:0] LINK8;
+ inout [41:0] LINK9;
+ input RRCK1;
+ input RRCK2;
+ input RTCK1;
+ input RTCK2;
+ input SPI1;
+ input SPI2;
+ input SPI3;
+ input WRCK1;
+ input WRCK2;
+ input WTCK1;
+ input WTCK2;
+ parameter div_rx1 = 4'b0000;
+ parameter div_rx2 = 4'b0000;
+ parameter div_tx1 = 4'b0000;
+ parameter div_tx2 = 4'b0000;
+ parameter inv_di_fclk1 = 1'b0;
+ parameter inv_di_fclk2 = 1'b0;
+ parameter latency1 = 1'b0;
+ parameter latency2 = 1'b0;
+ parameter location = "";
+ parameter mode_cpath = "";
+ parameter mode_epath = "";
+ parameter mode_io_cal = 1'b0;
+ parameter mode_rpath = "";
+ parameter mode_side1 = 0;
+ parameter mode_side2 = 0;
+ parameter mode_tpath = "";
+ parameter sel_clk_out1 = 1'b0;
+ parameter sel_clk_out2 = 1'b0;
+ parameter sel_clkr_rx1 = 1'b0;
+ parameter sel_clkr_rx2 = 1'b0;
+ parameter sel_clkw_rx1 = 2'b00;
+ parameter sel_clkw_rx2 = 2'b00;
+
+ NX_IOM_CONTROL_M #(
+ .div_rx1(div_rx1),
+ .div_rx2(div_rx2),
+ .div_tx1(div_tx1),
+ .div_tx2(div_tx2),
+ .inv_di_fclk1(inv_di_fclk1),
+ .inv_di_fclk2(inv_di_fclk2),
+ .latency1(latency1),
+ .latency2(latency2),
+ .location(location),
+ .mode_cpath(mode_cpath),
+ .mode_epath(mode_epath),
+ .mode_io_cal(mode_io_cal),
+ .mode_rpath(mode_rpath),
+ .mode_side1(mode_side1),
+ .mode_side2(mode_side2),
+ .mode_tpath(mode_tpath),
+ .sel_clk_out1(sel_clk_out1),
+ .sel_clk_out2(sel_clk_out2),
+ .sel_clkr_rx1(sel_clkr_rx1),
+ .sel_clkr_rx2(sel_clkr_rx2),
+ .sel_clkw_rx1(sel_clkw_rx1),
+ .sel_clkw_rx2(sel_clkw_rx2)
+ ) _TECHMAP_REPLACE_ (
+ .C1RED(C1RED),
+ .C1RNE(C1RNE),
+ .C1RS(C1RS),
+ .C1RW1(C1RW1),
+ .C1RW2(C1RW2),
+ .C1RW3(C1RW3),
+ .C1TS(C1TS),
+ .C1TW(C1TW),
+ .C2RED(C2RED),
+ .C2RNE(C2RNE),
+ .C2RS(C2RS),
+ .C2RW1(C2RW1),
+ .C2RW2(C2RW2),
+ .C2RW3(C2RW3),
+ .C2TS(C2TS),
+ .C2TW(C2TW),
+ .CAD1(CAD1),
+ .CAD2(CAD2),
+ .CAD3(CAD3),
+ .CAD4(CAD4),
+ .CAD5(CAD5),
+ .CAD6(CAD6),
+ .CAL(CAL),
+ .CAN1(CAN1),
+ .CAN2(CAN2),
+ .CAN3(CAN3),
+ .CAN4(CAN4),
+ .CAP1(CAP1),
+ .CAP2(CAP2),
+ .CAP3(CAP3),
+ .CAP4(CAP4),
+ .CAT1(CAT1),
+ .CAT2(CAT2),
+ .CAT3(CAT3),
+ .CAT4(CAT4),
+ .CCK(CCK),
+ .CKO1(CKO1),
+ .CKO2(CKO2),
+ .CTCK(CTCK),
+ .DC(DC),
+ .DCK(DCK),
+ .DIG(DIG),
+ .DIS(DIS),
+ .DOG(DOG),
+ .DOS(DOS),
+ .DPAG(DPAG),
+ .DPAS(DPAS),
+ .DQSG(DQSG),
+ .DQSS(DQSS),
+ .DRA1(DRA1),
+ .DRA2(DRA2),
+ .DRA3(DRA3),
+ .DRA4(DRA4),
+ .DRA5(DRA5),
+ .DRA6(DRA6),
+ .DRI1(DRI1),
+ .DRI2(DRI2),
+ .DRI3(DRI3),
+ .DRI4(DRI4),
+ .DRI5(DRI5),
+ .DRI6(DRI6),
+ .DRL(DRL),
+ .DRO1(DRO1),
+ .DRO2(DRO2),
+ .DRO3(DRO3),
+ .DRO4(DRO4),
+ .DRO5(DRO5),
+ .DRO6(DRO6),
+ .DS1(DS1),
+ .DS2(DS2),
+ .FA1(FA1),
+ .FA2(FA2),
+ .FA3(FA3),
+ .FA4(FA4),
+ .FA5(FA5),
+ .FA6(FA6),
+ .FLD(FLD),
+ .FLG(FLG),
+ .FZ(FZ),
+ .LINK1(LINK1),
+ .LINK10(LINK10),
+ .LINK11(LINK11),
+ .LINK12(LINK12),
+ .LINK13(LINK13),
+ .LINK14(LINK14),
+ .LINK15(LINK15),
+ .LINK16(LINK16),
+ .LINK17(LINK17),
+ .LINK18(LINK18),
+ .LINK19(LINK19),
+ .LINK2(LINK2),
+ .LINK20(LINK20),
+ .LINK21(LINK21),
+ .LINK22(LINK22),
+ .LINK23(LINK23),
+ .LINK24(LINK24),
+ .LINK25(LINK25),
+ .LINK26(LINK26),
+ .LINK27(LINK27),
+ .LINK28(LINK28),
+ .LINK29(LINK29),
+ .LINK3(LINK3),
+ .LINK30(LINK30),
+ .LINK31(LINK31),
+ .LINK32(LINK32),
+ .LINK33(LINK33),
+ .LINK34(LINK34),
+ .LINK4(LINK4),
+ .LINK5(LINK5),
+ .LINK6(LINK6),
+ .LINK7(LINK7),
+ .LINK8(LINK8),
+ .LINK9(LINK9),
+ .RRCK1(RRCK1),
+ .RRCK2(RRCK2),
+ .RTCK1(RTCK1),
+ .RTCK2(RTCK2),
+ .SPI1(SPI1),
+ .SPI2(SPI2),
+ .SPI3(SPI3),
+ .WRCK1(WRCK1),
+ .WRCK2(WRCK2),
+ .WTCK1(WTCK1),
+ .WTCK2(WTCK2)
+ );
+endmodule
+
+module NX_IOM_DRIVER(EI1, EI2, EI3, EI4, EI5, EL, ER, CI1, CI2, CI3, CI4, CI5, CL, CR, CTI, RI, RL, RR, CO, EO, RO1
+, RO2, RO3, RO4, RO5, CTO, LINK);
+ input CI1;
+ input CI2;
+ input CI3;
+ input CI4;
+ input CI5;
+ input CL;
+ output CO;
+ input CR;
+ input CTI;
+ output CTO;
+ input EI1;
+ input EI2;
+ input EI3;
+ input EI4;
+ input EI5;
+ input EL;
+ output EO;
+ input ER;
+ inout [41:0] LINK;
+ input RI;
+ input RL;
+ output RO1;
+ output RO2;
+ output RO3;
+ output RO4;
+ output RO5;
+ input RR;
+ parameter chained = 1'b0;
+ parameter cpath_edge = 1'b0;
+ parameter cpath_init = 1'b0;
+ parameter cpath_inv = 1'b0;
+ parameter cpath_load = 1'b0;
+ parameter cpath_mode = 4'b0000;
+ parameter cpath_sync = 1'b0;
+ parameter epath_dynamic = 1'b0;
+ parameter epath_edge = 1'b0;
+ parameter epath_init = 1'b0;
+ parameter epath_load = 1'b0;
+ parameter epath_mode = 4'b0000;
+ parameter epath_sync = 1'b0;
+ parameter location = "";
+ parameter rpath_dynamic = 1'b0;
+ parameter rpath_edge = 1'b0;
+ parameter rpath_init = 1'b0;
+ parameter rpath_load = 1'b0;
+ parameter rpath_mode = 4'b0000;
+ parameter rpath_sync = 1'b0;
+ parameter symbol = "";
+ parameter tpath_mode = 2'b00;
+ parameter variant = "";
+
+ NX_IOM_DRIVER_M #(
+ .chained(chained),
+ .cpath_edge(cpath_edge),
+ .cpath_init(cpath_init),
+ .cpath_inv(cpath_inv),
+ .cpath_load(cpath_load),
+ .cpath_mode(cpath_mode),
+ .cpath_sync(cpath_sync),
+ .epath_dynamic(epath_dynamic),
+ .epath_edge(epath_edge),
+ .epath_init(epath_init),
+ .epath_load(epath_load),
+ .epath_mode(epath_mode),
+ .epath_sync(epath_sync),
+ .location(location),
+ .rpath_dynamic(rpath_dynamic),
+ .rpath_edge(rpath_edge),
+ .rpath_init(rpath_init),
+ .rpath_load(rpath_load),
+ .rpath_mode(rpath_mode),
+ .rpath_sync(rpath_sync),
+ .symbol(symbol),
+ .tpath_mode(tpath_mode),
+ .variant(variant)
+ ) _TECHMAP_REPLACE_ (
+ .CI1(CI1),
+ .CI2(CI2),
+ .CI3(CI3),
+ .CI4(CI4),
+ .CI5(CI5),
+ .CL(CL),
+ .CO(CO),
+ .CR(CR),
+ .CTI(CTI),
+ .CTO(CTO),
+ .EI1(EI1),
+ .EI2(EI2),
+ .EI3(EI3),
+ .EI4(EI4),
+ .EI5(EI5),
+ .EL(EL),
+ .EO(EO),
+ .ER(ER),
+ .LINK(LINK),
+ .RI(RI),
+ .RL(RL),
+ .RO1(RO1),
+ .RO2(RO2),
+ .RO3(RO3),
+ .RO4(RO4),
+ .RO5(RO5),
+ .RR(RR)
+ );
+endmodule
+
+module NX_IOM_SERDES(RTCK, WRCK, WTCK, RRCK, TRST, RRST, CTCK, DCK, DRL, DIG, FZ, FLD, FLG, DS, DRA, DRI, DRO, DID, LINKN, LINKP);
+ input CTCK;
+ input DCK;
+ output [5:0] DID;
+ input DIG;
+ input [5:0] DRA;
+ input [5:0] DRI;
+ input DRL;
+ output [5:0] DRO;
+ input [1:0] DS;
+ output FLD;
+ output FLG;
+ input FZ;
+ inout [41:0] LINKN;
+ inout [41:0] LINKP;
+ input RRCK;
+ input RRST;
+ input RTCK;
+ input TRST;
+ input WRCK;
+ input WTCK;
+ parameter data_size = 5;
+ parameter location = "";
+
+ NX_IOM_SERDES_M #(
+ .data_size(data_size),
+ .location(location)
+ ) _TECHMAP_REPLACE_ (
+ .CTCK(CTCK),
+ .DCK(DCK),
+ .DID(DID),
+ .DIG(DIG),
+ .DRA(DRA),
+ .DRI(DRI),
+ .DRL(DRL),
+ .DRO(DRO),
+ .DS(DS),
+ .FLD(FLD),
+ .FLG(FLG),
+ .FZ(FZ),
+ .LINKN(LINKN),
+ .LINKP(LINKP),
+ .RRCK(RRCK),
+ .RRST(RRST),
+ .RTCK(RTCK),
+ .TRST(TRST),
+ .WRCK(WRCK),
+ .WTCK(WTCK)
+ );
+endmodule
diff --git a/techlibs/nanoxplore/cells_wrap_u.v b/techlibs/nanoxplore/cells_wrap_u.v
new file mode 100644
index 000000000..e504f7344
--- /dev/null
+++ b/techlibs/nanoxplore/cells_wrap_u.v
@@ -0,0 +1,3506 @@
+
+module NX_ODDFR_U(CK,R,I1,I2,L,O);
+ input CK;
+ input R;
+ input I1;
+ input I2;
+ input L;
+ output O;
+
+ parameter location = "";
+ parameter path = 0;
+ parameter dff_type = 1'b0;
+ parameter dff_sync = 1'b0;
+ parameter dff_load = 1'b0;
+
+ NX_DDFR_U #(
+ .location(location),
+ .path(path),
+ .dff_type(dff_type),
+ .dff_sync(dff_sync),
+ .dff_load(dff_load)
+ ) _TECHMAP_REPLACE_ (
+ .CK(CK),
+ .CKF(CK),
+ .R(R),
+ .I(I1),
+ .I2(I2),
+ .L(L),
+ .O(O),
+ .O2()
+ );
+endmodule
+
+module NX_IDDFR_U(CK,R,I,L,O1,O2);
+ input CK;
+ input R;
+ input I;
+ input L;
+ output O1;
+ output O2;
+
+ parameter location = "";
+ parameter dff_type = 1'b0;
+ parameter dff_sync = 1'b0;
+ parameter dff_load = 1'b0;
+
+ NX_DDFR_U #(
+ .location(location),
+ .path(1),
+ .dff_type(dff_type),
+ .dff_sync(dff_sync),
+ .dff_load(dff_load)
+ ) _TECHMAP_REPLACE_ (
+ .CK(CK),
+ .CKF(CK),
+ .R(R),
+ .I(I),
+ .I2(1'b0),
+ .L(L),
+ .O(O1),
+ .O2(O2)
+ );
+endmodule
+
+module NX_CKS_U(CKI, CMD, CKO);
+ input CKI;
+ output CKO;
+ input CMD;
+
+ NX_GCK_U #(
+ .inv_in(1'b0),
+ .inv_out(1'b0),
+ .std_mode("CKS")
+ ) _TECHMAP_REPLACE_ (
+ .CMD(CMD),
+ .SI1(CKI),
+ .SI2(),
+ .SO(CKO)
+ );
+endmodule
+
+module NX_CMUX_U(CKI0, CKI1, SEL, CKO);
+ input CKI0;
+ input CKI1;
+ output CKO;
+ input SEL;
+
+ NX_GCK_U #(
+ .inv_in(1'b0),
+ .inv_out(1'b0),
+ .std_mode("MUX")
+ ) _TECHMAP_REPLACE_ (
+ .CMD(SEL),
+ .SI1(CKI0),
+ .SI2(CKI1),
+ .SO(CKO)
+ );
+endmodule
+
+module NX_CDC_U_2DFF(CK1, CK2, ADRSTI, ADRSTO, BDRSTI, BDRSTO, BI, AO, BO, AI);
+ input ADRSTI;
+ output ADRSTO;
+ input [5:0] AI;
+ output [5:0] AO;
+ input BDRSTI;
+ output BDRSTO;
+ input [5:0] BI;
+ output [5:0] BO;
+ input CK1;
+ input CK2;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter use_adest_arst = 1'b0;
+ parameter use_bdest_arst = 1'b0;
+
+ NX_CDC_U #(
+ .mode(0), // -- 0: 2DFF
+ .ck0_edge(ck0_edge),
+ .ck1_edge(ck1_edge),
+ .ack_sel(ack_sel),
+ .bck_sel(bck_sel),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(1'b0),
+ .use_adest_arst(use_adest_arst),
+ .use_bsrc_arst(1'b0),
+ .use_bdest_arst(use_bdest_arst),
+ .use_csrc_arst(1'b0),
+ .use_cdest_arst(1'b0),
+ .use_dsrc_arst(1'b0),
+ .use_ddest_arst(1'b0),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(CK1),
+ .CK2(CK2),
+ .ASRSTI(1'b0),
+ .ADRSTI(ADRSTI),
+ .ADRSTO(ADRSTO),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BSRSTI(1'b0),
+ .BDRSTI(BDRSTI),
+ .BDRSTO(BDRSTO),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CSRSTI(1'b0),
+ .CDRSTI(1'b0),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DSRSTI(1'b0),
+ .DDRSTI(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0),
+ );
+endmodule
+
+module NX_CDC_U_3DFF(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);
+ input ADRSTI;
+ output ADRSTO;
+ input [5:0] AI;
+ output [5:0] AO;
+ input ASRSTI;
+ output ASRSTO;
+ input BDRSTI;
+ output BDRSTO;
+ input [5:0] BI;
+ output [5:0] BO;
+ input BSRSTI;
+ output BSRSTO;
+ input CK1;
+ input CK2;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter use_adest_arst = 1'b0;
+ parameter use_asrc_arst = 1'b0;
+ parameter use_bdest_arst = 1'b0;
+ parameter use_bsrc_arst = 1'b0;
+
+ NX_CDC_U #(
+ .mode(1), // -- 1: 3DFF
+ .ck0_edge(ck0_edge),
+ .ck1_edge(ck1_edge),
+ .ack_sel(ack_sel),
+ .bck_sel(bck_sel),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(use_asrc_arst),
+ .use_adest_arst(use_adest_arst),
+ .use_bsrc_arst(use_bsrc_arst),
+ .use_bdest_arst(use_bdest_arst),
+ .use_csrc_arst(1'b0),
+ .use_cdest_arst(1'b0),
+ .use_dsrc_arst(1'b0),
+ .use_ddest_arst(1'b0),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(CK1),
+ .CK2(CK2),
+ .ASRSTI(ASRSTI),
+ .ADRSTI(ADRSTI),
+ .ASRSTO(ASRSTO),
+ .ADRSTO(ADRSTO),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BSRSTI(BSRSTI),
+ .BDRSTI(BDRSTI),
+ .BSRSTO(BSRSTO),
+ .BDRSTO(BDRSTO),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CSRSTI(1'b0),
+ .CDRSTI(1'b0),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DSRSTI(1'b0),
+ .DDRSTI(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0),
+ );
+endmodule
+
+module NX_CDC_U_FULL(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, BI, AO, BO, AI);
+ input ADRSTI;
+ output ADRSTO;
+ input [5:0] AI;
+ output [5:0] AO;
+ input ASRSTI;
+ output ASRSTO;
+ input BDRSTI;
+ output BDRSTO;
+ input [5:0] BI;
+ output [5:0] BO;
+ input BSRSTI;
+ output BSRSTO;
+ input CK1;
+ input CK2;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter use_adest_arst = 1'b0;
+ parameter use_asrc_arst = 1'b0;
+ parameter use_bdest_arst = 1'b0;
+ parameter use_bsrc_arst = 1'b0;
+
+ NX_CDC_U #(
+ .mode(2), // -- 2: bin2gray + 3DFF + gray2bin
+ .ck0_edge(ck0_edge),
+ .ck1_edge(ck1_edge),
+ .ack_sel(ack_sel),
+ .bck_sel(bck_sel),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(use_asrc_arst),
+ .use_adest_arst(use_adest_arst),
+ .use_bsrc_arst(use_bsrc_arst),
+ .use_bdest_arst(use_bdest_arst),
+ .use_csrc_arst(1'b0),
+ .use_cdest_arst(1'b0),
+ .use_dsrc_arst(1'b0),
+ .use_ddest_arst(1'b0),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(CK1),
+ .CK2(CK2),
+ .ASRSTI(ASRSTI),
+ .ADRSTI(ADRSTI),
+ .ASRSTO(ASRSTO),
+ .ADRSTO(ADRSTO),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BSRSTI(BSRSTI),
+ .BDRSTI(BDRSTI),
+ .BSRSTO(BSRSTO),
+ .BDRSTO(BDRSTO),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CSRSTI(1'b0),
+ .CDRSTI(1'b0),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DSRSTI(1'b0),
+ .DDRSTI(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0),
+ );
+endmodule
+
+module NX_CDC_U_BIN2GRAY(BI, AO, BO, AI);
+ input [5:0] AI;
+ output [5:0] AO;
+ input [5:0] BI;
+ output [5:0] BO;
+
+ NX_CDC_U #(
+ .mode(3), // -- 3: bin2gray
+ .ck0_edge(1'b0),
+ .ck1_edge(1'b0),
+ .ack_sel(1'b0),
+ .bck_sel(1'b0),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(1'b0),
+ .use_adest_arst(1'b0),
+ .use_bsrc_arst(1'b0),
+ .use_bdest_arst(1'b0),
+ .use_csrc_arst(1'b0),
+ .use_cdest_arst(1'b0),
+ .use_dsrc_arst(1'b0),
+ .use_ddest_arst(1'b0),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(1'b0),
+ .CK2(1'b0),
+ .ASRSTI(1'b0),
+ .ADRSTI(1'b0),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BSRSTI(1'b0),
+ .BDRSTI(1'b0),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CSRSTI(1'b0),
+ .CDRSTI(1'b0),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DSRSTI(1'b0),
+ .DDRSTI(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0),
+ );
+endmodule
+
+module NX_CDC_U_GRAY2BIN(BI, AO, BO, AI);
+ input [5:0] AI;
+ output [5:0] AO;
+ input [5:0] BI;
+ output [5:0] BO;
+
+ NX_CDC_U #(
+ .mode(4), // -- 4: gray2bin
+ .ck0_edge(1'b0),
+ .ck1_edge(1'b0),
+ .ack_sel(1'b0),
+ .bck_sel(1'b0),
+ .cck_sel(1'b0),
+ .dck_sel(1'b0),
+ .use_asrc_arst(1'b0),
+ .use_adest_arst(1'b0),
+ .use_bsrc_arst(1'b0),
+ .use_bdest_arst(1'b0),
+ .use_csrc_arst(1'b0),
+ .use_cdest_arst(1'b0),
+ .use_dsrc_arst(1'b0),
+ .use_ddest_arst(1'b0),
+ .link_BA(1'b0),
+ .link_CB(1'b0),
+ .link_DC(1'b0),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(1'b0),
+ .CK2(1'b0),
+ .ASRSTI(1'b0),
+ .ADRSTI(1'b0),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BSRSTI(1'b0),
+ .BDRSTI(1'b0),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CSRSTI(1'b0),
+ .CDRSTI(1'b0),
+ .CI1(1'b0),
+ .CI2(1'b0),
+ .CI3(1'b0),
+ .CI4(1'b0),
+ .CI5(1'b0),
+ .CI6(1'b0),
+ .DSRSTI(1'b0),
+ .DDRSTI(1'b0),
+ .DI1(1'b0),
+ .DI2(1'b0),
+ .DI3(1'b0),
+ .DI4(1'b0),
+ .DI5(1'b0),
+ .DI6(1'b0),
+ );
+endmodule
+
+module NX_XCDC_U(CK1, CK2, ASRSTI, ADRSTI, ASRSTO, ADRSTO, BSRSTI, BDRSTI, BSRSTO, BDRSTO, CSRSTI, CDRSTI, CSRSTO, CDRSTO, DSRSTI, DDRSTI, DSRSTO, DDRSTO, BI, CI, CO
+, AO, BO, AI, DI, DO);
+ input ADRSTI;
+ output ADRSTO;
+ input [5:0] AI;
+ output [5:0] AO;
+ input ASRSTI;
+ output ASRSTO;
+ input BDRSTI;
+ output BDRSTO;
+ input [5:0] BI;
+ output [5:0] BO;
+ input BSRSTI;
+ output BSRSTO;
+ input CDRSTI;
+ output CDRSTO;
+ input [5:0] CI;
+ input CK1;
+ input CK2;
+ output [5:0] CO;
+ input CSRSTI;
+ output CSRSTO;
+ input DDRSTI;
+ output DDRSTO;
+ input [5:0] DI;
+ output [5:0] DO;
+ input DSRSTI;
+ output DSRSTO;
+ parameter ack_sel = 1'b0;
+ parameter bck_sel = 1'b0;
+ parameter cck_sel = 1'b0;
+ parameter ck0_edge = 1'b0;
+ parameter ck1_edge = 1'b0;
+ parameter dck_sel = 1'b0;
+ parameter link_BA = 1'b0;
+ parameter link_CB = 1'b0;
+ parameter link_DC = 1'b0;
+ parameter use_adest_arst = 1'b0;
+ parameter use_asrc_arst = 1'b0;
+ parameter use_bdest_arst = 1'b0;
+ parameter use_bsrc_arst = 1'b0;
+ parameter use_cdest_arst = 1'b0;
+ parameter use_csrc_arst = 1'b0;
+ parameter use_ddest_arst = 1'b0;
+ parameter use_dsrc_arst = 1'b0;
+
+ NX_CDC_U #(
+ .mode(5), // -- 5: XCDC
+ .ck0_edge(ck0_edge),
+ .ck1_edge(ck1_edge),
+ .ack_sel(ack_sel),
+ .bck_sel(bck_sel),
+ .cck_sel(cck_sel),
+ .dck_sel(dck_sel),
+ .use_asrc_arst(use_asrc_arst),
+ .use_adest_arst(use_adest_arst),
+ .use_bsrc_arst(use_bsrc_arst),
+ .use_bdest_arst(use_bdest_arst),
+ .use_csrc_arst(use_csrc_arst),
+ .use_cdest_arst(use_cdest_arst),
+ .use_dsrc_arst(use_dsrc_arst),
+ .use_ddest_arst(use_ddest_arst),
+ .link_BA(link_BA),
+ .link_CB(link_CB),
+ .link_DC(link_DC),
+ ) _TECHMAP_REPLACE_ (
+ .CK1(CK1),
+ .CK2(CK2),
+ .ASRSTI(ASRSTI),
+ .ADRSTI(ADRSTI),
+ .ASRSTO(ASRSTO),
+ .ADRSTO(ADRSTO),
+ .AI1(AI[0]),
+ .AI2(AI[1]),
+ .AI3(AI[2]),
+ .AI4(AI[3]),
+ .AI5(AI[4]),
+ .AI6(AI[5]),
+ .AO1(AO[0]),
+ .AO2(AO[1]),
+ .AO3(AO[2]),
+ .AO4(AO[3]),
+ .AO5(AO[4]),
+ .AO6(AO[5]),
+ .BSRSTI(BSRSTI),
+ .BDRSTI(BDRSTI),
+ .BSRSTO(BSRSTO),
+ .BDRSTO(BDRSTO),
+ .BI1(BI[0]),
+ .BI2(BI[1]),
+ .BI3(BI[2]),
+ .BI4(BI[3]),
+ .BI5(BI[4]),
+ .BI6(BI[5]),
+ .BO1(BO[0]),
+ .BO2(BO[1]),
+ .BO3(BO[2]),
+ .BO4(BO[3]),
+ .BO5(BO[4]),
+ .BO6(BO[5]),
+ .CSRSTI(CSRSTI),
+ .CDRSTI(CDRSTI),
+ .CSRSTO(CSRSTO),
+ .CDRSTO(CDRSTO),
+ .CI1(CI[0]),
+ .CI2(CI[1]),
+ .CI3(CI[2]),
+ .CI4(CI[3]),
+ .CI5(CI[4]),
+ .CI6(CI[5]),
+ .CO1(CO[0]),
+ .CO2(CO[1]),
+ .CO3(CO[2]),
+ .CO4(CO[3]),
+ .CO5(CO[4]),
+ .CO6(CO[5]),
+ .DSRSTI(DSRSTI),
+ .DDRSTI(DDRSTI),
+ .DSRSTO(DSRSTO),
+ .DDRSTO(DDRSTO),
+ .DI1(DI[0]),
+ .DI2(DI[1]),
+ .DI3(DI[2]),
+ .DI4(DI[3]),
+ .DI5(DI[4]),
+ .DI6(DI[5]),
+ .DO1(DO[0]),
+ .DO2(DO[1]),
+ .DO3(DO[2]),
+ .DO4(DO[3]),
+ .DO5(DO[4]),
+ .DO6(DO[5]),
+ );
+endmodule
+
+module NX_DSP_U_SPLIT(CK, R, RZ, WE, WEZ, CI, CCI, CO42, CO56, OVF, CCO, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO, CZO);
+ input [23:0] A;
+ input [17:0] B;
+ input [35:0] C;
+ input [23:0] CAI;
+ output [23:0] CAO;
+ input [17:0] CBI;
+ output [17:0] CBO;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO42;
+ output CO56;
+ input [55:0] CZI;
+ output [55:0] CZO;
+ input [17:0] D;
+ output OVF;
+ input R;
+ input RZ;
+ input WE;
+ input WEZ;
+ output [55:0] Z;
+ parameter ALU_DYNAMIC_OP = 2'b00;
+ parameter ALU_OP = 3'b000;
+ parameter ENABLE_PR_A_RST = 1'b0;
+ parameter ENABLE_PR_B_RST = 1'b0;
+ parameter ENABLE_PR_CCO_RST = 1'b0;
+ parameter ENABLE_PR_CI_RST = 1'b0;
+ parameter ENABLE_PR_CO_RST = 1'b0;
+ parameter ENABLE_PR_CZ_RST = 1'b0;
+ parameter ENABLE_PR_C_RST = 1'b0;
+ parameter ENABLE_PR_D_RST = 1'b0;
+ parameter ENABLE_PR_MULT_RST = 1'b0;
+ parameter ENABLE_PR_OV_RST = 1'b0;
+ parameter ENABLE_PR_P_RST = 1'b0;
+ parameter ENABLE_PR_X_RST = 1'b0;
+ parameter ENABLE_PR_Y_RST = 1'b0;
+ parameter ENABLE_PR_Z_RST = 1'b0;
+ parameter ENABLE_SATURATION = 1'b0;
+ parameter INV_RST = 1'b0;
+ parameter INV_RSTZ = 1'b0;
+ parameter INV_WE = 1'b0;
+ parameter INV_WEZ = 1'b0;
+ parameter MUX_A = 1'b0;
+ parameter MUX_B = 1'b0;
+ parameter MUX_CCI = 1'b0;
+ parameter MUX_CCO = 1'b0;
+ parameter MUX_CI = 1'b0;
+ parameter MUX_CZ = 1'b0;
+ parameter MUX_P = 1'b0;
+ parameter MUX_X = 3'b000;
+ parameter MUX_Y = 1'b0;
+ parameter MUX_Z = 1'b0;
+ parameter PRE_ADDER_OP = 1'b0;
+ parameter PR_A_CASCADE_MUX = 2'b00;
+ parameter PR_A_MUX = 2'b00;
+ parameter PR_B_CASCADE_MUX = 2'b00;
+ parameter PR_B_MUX = 2'b00;
+ parameter PR_CCO_MUX = 1'b0;
+ parameter PR_CI_MUX = 1'b0;
+ parameter PR_CO_MUX = 1'b0;
+ parameter PR_CZ_MUX = 1'b0;
+ parameter PR_C_MUX = 1'b0;
+ parameter PR_D_MUX = 1'b0;
+ parameter PR_MULT_MUX = 1'b0;
+ parameter PR_OV_MUX = 1'b0;
+ parameter PR_P_MUX = 1'b0;
+ parameter PR_RSTZ_MUX = 1'b0;
+ parameter PR_RST_MUX = 1'b0;
+ parameter PR_WEZ_MUX = 1'b0;
+ parameter PR_WE_MUX = 1'b0;
+ parameter PR_X_MUX = 1'b0;
+ parameter PR_Y_MUX = 1'b0;
+ parameter PR_Z_MUX = 1'b0;
+ parameter SATURATION_RANK = 6'b000000;
+ parameter SIGNED_MODE = 1'b0;
+
+ localparam RAW_CONFIG0_GEN = { INV_WE, INV_WEZ, INV_RST, INV_RSTZ, MUX_CCO, ALU_DYNAMIC_OP, SATURATION_RANK,
+ ENABLE_SATURATION, MUX_Z, MUX_CCI, MUX_CI, MUX_Y, MUX_CZ, MUX_X, MUX_P,
+ MUX_B, MUX_A, PRE_ADDER_OP, SIGNED_MODE };
+
+ localparam RAW_CONFIG1_GEN = { PR_WE_MUX, PR_WEZ_MUX, PR_RST_MUX, PR_RSTZ_MUX, PR_OV_MUX, PR_CO_MUX, PR_CCO_MUX,
+ PR_Z_MUX, PR_CZ_MUX, PR_Y_MUX, PR_X_MUX, PR_CI_MUX, PR_MULT_MUX, PR_P_MUX, PR_D_MUX,
+ PR_C_MUX, PR_B_CASCADE_MUX, PR_B_MUX, PR_A_CASCADE_MUX, PR_A_MUX };
+
+ localparam RAW_CONFIG2_GEN = { ENABLE_PR_OV_RST, ENABLE_PR_CO_RST, ENABLE_PR_CCO_RST, ENABLE_PR_Z_RST, ENABLE_PR_CZ_RST,
+ ENABLE_PR_MULT_RST, ENABLE_PR_Y_RST, ENABLE_PR_X_RST, ENABLE_PR_P_RST, ENABLE_PR_CI_RST,
+ ENABLE_PR_D_RST, ENABLE_PR_C_RST, ENABLE_PR_B_RST, ENABLE_PR_A_RST };
+
+ localparam RAW_CONFIG3_GEN = { ALU_OP };
+
+ NX_DSP_U #(
+ .std_mode(""),
+ .raw_config0(RAW_CONFIG0_GEN),
+ .raw_config1(RAW_CONFIG1_GEN),
+ .raw_config2(RAW_CONFIG2_GEN),
+ .raw_config3(RAW_CONFIG3_GEN)
+ ) _TECHMAP_REPLACE_ (
+ .A1(A[0]),
+ .A2(A[1]),
+ .A3(A[2]),
+ .A4(A[3]),
+ .A5(A[4]),
+ .A6(A[5]),
+ .A7(A[6]),
+ .A8(A[7]),
+ .A9(A[8]),
+ .A10(A[9]),
+ .A11(A[10]),
+ .A12(A[11]),
+ .A13(A[12]),
+ .A14(A[13]),
+ .A15(A[14]),
+ .A16(A[15]),
+ .A17(A[16]),
+ .A18(A[17]),
+ .A19(A[18]),
+ .A20(A[19]),
+ .A21(A[20]),
+ .A22(A[21]),
+ .A23(A[22]),
+ .A24(A[23]),
+
+ .B1(B[0]),
+ .B2(B[1]),
+ .B3(B[2]),
+ .B4(B[3]),
+ .B5(B[4]),
+ .B6(B[5]),
+ .B7(B[6]),
+ .B8(B[7]),
+ .B9(B[8]),
+ .B10(B[9]),
+ .B11(B[10]),
+ .B12(B[11]),
+ .B13(B[12]),
+ .B14(B[13]),
+ .B15(B[14]),
+ .B16(B[15]),
+ .B17(B[16]),
+ .B18(B[17]),
+
+ .C1(C[0]),
+ .C2(C[1]),
+ .C3(C[2]),
+ .C4(C[3]),
+ .C5(C[4]),
+ .C6(C[5]),
+ .C7(C[6]),
+ .C8(C[7]),
+ .C9(C[8]),
+ .C10(C[9]),
+ .C11(C[10]),
+ .C12(C[11]),
+ .C13(C[12]),
+ .C14(C[13]),
+ .C15(C[14]),
+ .C16(C[15]),
+ .C17(C[16]),
+ .C18(C[17]),
+ .C19(C[18]),
+ .C20(C[19]),
+ .C21(C[20]),
+ .C22(C[21]),
+ .C23(C[22]),
+ .C24(C[23]),
+ .C25(C[24]),
+ .C26(C[25]),
+ .C27(C[26]),
+ .C28(C[27]),
+ .C29(C[28]),
+ .C30(C[29]),
+ .C31(C[30]),
+ .C32(C[31]),
+ .C33(C[32]),
+ .C34(C[33]),
+ .C35(C[34]),
+ .C36(C[35]),
+
+ .CAI1(CAI[0]),
+ .CAI2(CAI[1]),
+ .CAI3(CAI[2]),
+ .CAI4(CAI[3]),
+ .CAI5(CAI[4]),
+ .CAI6(CAI[5]),
+ .CAI7(CAI[6]),
+ .CAI8(CAI[7]),
+ .CAI9(CAI[8]),
+ .CAI10(CAI[9]),
+ .CAI11(CAI[10]),
+ .CAI12(CAI[11]),
+ .CAI13(CAI[12]),
+ .CAI14(CAI[13]),
+ .CAI15(CAI[14]),
+ .CAI16(CAI[15]),
+ .CAI17(CAI[16]),
+ .CAI18(CAI[17]),
+ .CAI19(CAI[18]),
+ .CAI20(CAI[19]),
+ .CAI21(CAI[20]),
+ .CAI22(CAI[21]),
+ .CAI23(CAI[22]),
+ .CAI24(CAI[23]),
+
+ .CAO1(CAO[0]),
+ .CAO2(CAO[1]),
+ .CAO3(CAO[2]),
+ .CAO4(CAO[3]),
+ .CAO5(CAO[4]),
+ .CAO6(CAO[5]),
+ .CAO7(CAO[6]),
+ .CAO8(CAO[7]),
+ .CAO9(CAO[8]),
+ .CAO10(CAO[9]),
+ .CAO11(CAO[10]),
+ .CAO12(CAO[11]),
+ .CAO13(CAO[12]),
+ .CAO14(CAO[13]),
+ .CAO15(CAO[14]),
+ .CAO16(CAO[15]),
+ .CAO17(CAO[16]),
+ .CAO18(CAO[17]),
+ .CAO19(CAO[18]),
+ .CAO20(CAO[19]),
+ .CAO21(CAO[20]),
+ .CAO22(CAO[21]),
+ .CAO23(CAO[22]),
+ .CAO24(CAO[23]),
+
+ .CBI1(CBI[0]),
+ .CBI2(CBI[1]),
+ .CBI3(CBI[2]),
+ .CBI4(CBI[3]),
+ .CBI5(CBI[4]),
+ .CBI6(CBI[5]),
+ .CBI7(CBI[6]),
+ .CBI8(CBI[7]),
+ .CBI9(CBI[8]),
+ .CBI10(CBI[9]),
+ .CBI11(CBI[10]),
+ .CBI12(CBI[11]),
+ .CBI13(CBI[12]),
+ .CBI14(CBI[13]),
+ .CBI15(CBI[14]),
+ .CBI16(CBI[15]),
+ .CBI17(CBI[16]),
+ .CBI18(CBI[17]),
+
+ .CBO1(CBO[0]),
+ .CBO2(CBO[1]),
+ .CBO3(CBO[2]),
+ .CBO4(CBO[3]),
+ .CBO5(CBO[4]),
+ .CBO6(CBO[5]),
+ .CBO7(CBO[6]),
+ .CBO8(CBO[7]),
+ .CBO9(CBO[8]),
+ .CBO10(CBO[9]),
+ .CBO11(CBO[10]),
+ .CBO12(CBO[11]),
+ .CBO13(CBO[12]),
+ .CBO14(CBO[13]),
+ .CBO15(CBO[14]),
+ .CBO16(CBO[15]),
+ .CBO17(CBO[16]),
+ .CBO18(CBO[17]),
+
+ .CCI(CCI),
+ .CCO(CCO),
+ .CI(CI),
+ .CK(CK),
+ .CO43(CO42),
+ .CO57(CO56),
+
+ .CZI1(CZI[0]),
+ .CZI2(CZI[1]),
+ .CZI3(CZI[2]),
+ .CZI4(CZI[3]),
+ .CZI5(CZI[4]),
+ .CZI6(CZI[5]),
+ .CZI7(CZI[6]),
+ .CZI8(CZI[7]),
+ .CZI9(CZI[8]),
+ .CZI10(CZI[9]),
+ .CZI11(CZI[10]),
+ .CZI12(CZI[11]),
+ .CZI13(CZI[12]),
+ .CZI14(CZI[13]),
+ .CZI15(CZI[14]),
+ .CZI16(CZI[15]),
+ .CZI17(CZI[16]),
+ .CZI18(CZI[17]),
+ .CZI19(CZI[18]),
+ .CZI20(CZI[19]),
+ .CZI21(CZI[20]),
+ .CZI22(CZI[21]),
+ .CZI23(CZI[22]),
+ .CZI24(CZI[23]),
+ .CZI25(CZI[24]),
+ .CZI26(CZI[25]),
+ .CZI27(CZI[26]),
+ .CZI28(CZI[27]),
+ .CZI29(CZI[28]),
+ .CZI30(CZI[29]),
+ .CZI31(CZI[30]),
+ .CZI32(CZI[31]),
+ .CZI33(CZI[32]),
+ .CZI34(CZI[33]),
+ .CZI35(CZI[34]),
+ .CZI36(CZI[35]),
+ .CZI37(CZI[36]),
+ .CZI38(CZI[37]),
+ .CZI39(CZI[38]),
+ .CZI40(CZI[39]),
+ .CZI41(CZI[40]),
+ .CZI42(CZI[41]),
+ .CZI43(CZI[42]),
+ .CZI44(CZI[43]),
+ .CZI45(CZI[44]),
+ .CZI46(CZI[45]),
+ .CZI47(CZI[46]),
+ .CZI48(CZI[47]),
+ .CZI49(CZI[48]),
+ .CZI50(CZI[49]),
+ .CZI51(CZI[50]),
+ .CZI52(CZI[51]),
+ .CZI53(CZI[52]),
+ .CZI54(CZI[53]),
+ .CZI55(CZI[54]),
+ .CZI56(CZI[55]),
+
+ .CZO1(CZO[0]),
+ .CZO2(CZO[1]),
+ .CZO3(CZO[2]),
+ .CZO4(CZO[3]),
+ .CZO5(CZO[4]),
+ .CZO6(CZO[5]),
+ .CZO7(CZO[6]),
+ .CZO8(CZO[7]),
+ .CZO9(CZO[8]),
+ .CZO10(CZO[9]),
+ .CZO11(CZO[10]),
+ .CZO12(CZO[11]),
+ .CZO13(CZO[12]),
+ .CZO14(CZO[13]),
+ .CZO15(CZO[14]),
+ .CZO16(CZO[15]),
+ .CZO17(CZO[16]),
+ .CZO18(CZO[17]),
+ .CZO19(CZO[18]),
+ .CZO20(CZO[19]),
+ .CZO21(CZO[20]),
+ .CZO22(CZO[21]),
+ .CZO23(CZO[22]),
+ .CZO24(CZO[23]),
+ .CZO25(CZO[24]),
+ .CZO26(CZO[25]),
+ .CZO27(CZO[26]),
+ .CZO28(CZO[27]),
+ .CZO29(CZO[28]),
+ .CZO30(CZO[29]),
+ .CZO31(CZO[30]),
+ .CZO32(CZO[31]),
+ .CZO33(CZO[32]),
+ .CZO34(CZO[33]),
+ .CZO35(CZO[34]),
+ .CZO36(CZO[35]),
+ .CZO37(CZO[36]),
+ .CZO38(CZO[37]),
+ .CZO39(CZO[38]),
+ .CZO40(CZO[39]),
+ .CZO41(CZO[40]),
+ .CZO42(CZO[41]),
+ .CZO43(CZO[42]),
+ .CZO44(CZO[43]),
+ .CZO45(CZO[44]),
+ .CZO46(CZO[45]),
+ .CZO47(CZO[46]),
+ .CZO48(CZO[47]),
+ .CZO49(CZO[48]),
+ .CZO50(CZO[49]),
+ .CZO51(CZO[50]),
+ .CZO52(CZO[51]),
+ .CZO53(CZO[52]),
+ .CZO54(CZO[53]),
+ .CZO55(CZO[54]),
+ .CZO56(CZO[55]),
+
+ .D1(D[0]),
+ .D2(D[1]),
+ .D3(D[2]),
+ .D4(D[3]),
+ .D5(D[4]),
+ .D6(D[5]),
+ .D7(D[6]),
+ .D8(D[7]),
+ .D9(D[8]),
+ .D10(D[9]),
+ .D11(D[10]),
+ .D12(D[11]),
+ .D13(D[12]),
+ .D14(D[13]),
+ .D15(D[14]),
+ .D16(D[15]),
+ .D17(D[16]),
+ .D18(D[17]),
+
+ .OVF(OVF),
+ .R(R),
+ .RZ(RZ),
+ .WE(WE),
+ .WEZ(WEZ),
+
+ .Z1(Z[0]),
+ .Z2(Z[1]),
+ .Z3(Z[2]),
+ .Z4(Z[3]),
+ .Z5(Z[4]),
+ .Z6(Z[5]),
+ .Z7(Z[6]),
+ .Z8(Z[7]),
+ .Z9(Z[8]),
+ .Z10(Z[9]),
+ .Z11(Z[10]),
+ .Z12(Z[11]),
+ .Z13(Z[12]),
+ .Z14(Z[13]),
+ .Z15(Z[14]),
+ .Z16(Z[15]),
+ .Z17(Z[16]),
+ .Z18(Z[17]),
+ .Z19(Z[18]),
+ .Z20(Z[19]),
+ .Z21(Z[20]),
+ .Z22(Z[21]),
+ .Z23(Z[22]),
+ .Z24(Z[23]),
+ .Z25(Z[24]),
+ .Z26(Z[25]),
+ .Z27(Z[26]),
+ .Z28(Z[27]),
+ .Z29(Z[28]),
+ .Z30(Z[29]),
+ .Z31(Z[30]),
+ .Z32(Z[31]),
+ .Z33(Z[32]),
+ .Z34(Z[33]),
+ .Z35(Z[34]),
+ .Z36(Z[35]),
+ .Z37(Z[36]),
+ .Z38(Z[37]),
+ .Z39(Z[38]),
+ .Z40(Z[39]),
+ .Z41(Z[40]),
+ .Z42(Z[41]),
+ .Z43(Z[42]),
+ .Z44(Z[43]),
+ .Z45(Z[44]),
+ .Z46(Z[45]),
+ .Z47(Z[46]),
+ .Z48(Z[47]),
+ .Z49(Z[48]),
+ .Z50(Z[49]),
+ .Z51(Z[50]),
+ .Z52(Z[51]),
+ .Z53(Z[52]),
+ .Z54(Z[53]),
+ .Z55(Z[54]),
+ .Z56(Z[55])
+ );
+endmodule
+
+module NX_DSP_U_WRAP(CCI, CCO, CI, CK, CO43, CO57, OVF, R, RZ, WE, WEZ, A, B, C, D, Z, CAI, CBI, CZI, CAO, CBO
+, CZO);
+ input [23:0] A;
+ input [17:0] B;
+ input [35:0] C;
+ input [23:0] CAI;
+ output [23:0] CAO;
+ input [17:0] CBI;
+ output [17:0] CBO;
+ input CCI;
+ output CCO;
+ input CI;
+ input CK;
+ output CO43;
+ output CO57;
+ input [55:0] CZI;
+ output [55:0] CZO;
+ input [17:0] D;
+ output OVF;
+ input R;
+ input RZ;
+ input WE;
+ input WEZ;
+ output [55:0] Z;
+ parameter raw_config0 = 27'b000000000000000000000000000;
+ parameter raw_config1 = 24'b000000000000000000000000;
+ parameter raw_config2 = 14'b00000000000000;
+ parameter raw_config3 = 3'b000;
+ parameter std_mode = "";
+
+ NX_DSP_U #(
+ .std_mode(std_mode),
+ .raw_config0(raw_config0),
+ .raw_config1(raw_config1),
+ .raw_config2(raw_config2),
+ .raw_config3(raw_config3)
+ ) _TECHMAP_REPLACE_ (
+ .A1(A[0]),
+ .A2(A[1]),
+ .A3(A[2]),
+ .A4(A[3]),
+ .A5(A[4]),
+ .A6(A[5]),
+ .A7(A[6]),
+ .A8(A[7]),
+ .A9(A[8]),
+ .A10(A[9]),
+ .A11(A[10]),
+ .A12(A[11]),
+ .A13(A[12]),
+ .A14(A[13]),
+ .A15(A[14]),
+ .A16(A[15]),
+ .A17(A[16]),
+ .A18(A[17]),
+ .A19(A[18]),
+ .A20(A[19]),
+ .A21(A[20]),
+ .A22(A[21]),
+ .A23(A[22]),
+ .A24(A[23]),
+
+ .B1(B[0]),
+ .B2(B[1]),
+ .B3(B[2]),
+ .B4(B[3]),
+ .B5(B[4]),
+ .B6(B[5]),
+ .B7(B[6]),
+ .B8(B[7]),
+ .B9(B[8]),
+ .B10(B[9]),
+ .B11(B[10]),
+ .B12(B[11]),
+ .B13(B[12]),
+ .B14(B[13]),
+ .B15(B[14]),
+ .B16(B[15]),
+ .B17(B[16]),
+ .B18(B[17]),
+
+ .C1(C[0]),
+ .C2(C[1]),
+ .C3(C[2]),
+ .C4(C[3]),
+ .C5(C[4]),
+ .C6(C[5]),
+ .C7(C[6]),
+ .C8(C[7]),
+ .C9(C[8]),
+ .C10(C[9]),
+ .C11(C[10]),
+ .C12(C[11]),
+ .C13(C[12]),
+ .C14(C[13]),
+ .C15(C[14]),
+ .C16(C[15]),
+ .C17(C[16]),
+ .C18(C[17]),
+ .C19(C[18]),
+ .C20(C[19]),
+ .C21(C[20]),
+ .C22(C[21]),
+ .C23(C[22]),
+ .C24(C[23]),
+ .C25(C[24]),
+ .C26(C[25]),
+ .C27(C[26]),
+ .C28(C[27]),
+ .C29(C[28]),
+ .C30(C[29]),
+ .C31(C[30]),
+ .C32(C[31]),
+ .C33(C[32]),
+ .C34(C[33]),
+ .C35(C[34]),
+ .C36(C[35]),
+
+ .CAI1(CAI[0]),
+ .CAI2(CAI[1]),
+ .CAI3(CAI[2]),
+ .CAI4(CAI[3]),
+ .CAI5(CAI[4]),
+ .CAI6(CAI[5]),
+ .CAI7(CAI[6]),
+ .CAI8(CAI[7]),
+ .CAI9(CAI[8]),
+ .CAI10(CAI[9]),
+ .CAI11(CAI[10]),
+ .CAI12(CAI[11]),
+ .CAI13(CAI[12]),
+ .CAI14(CAI[13]),
+ .CAI15(CAI[14]),
+ .CAI16(CAI[15]),
+ .CAI17(CAI[16]),
+ .CAI18(CAI[17]),
+ .CAI19(CAI[18]),
+ .CAI20(CAI[19]),
+ .CAI21(CAI[20]),
+ .CAI22(CAI[21]),
+ .CAI23(CAI[22]),
+ .CAI24(CAI[23]),
+
+ .CAO1(CAO[0]),
+ .CAO2(CAO[1]),
+ .CAO3(CAO[2]),
+ .CAO4(CAO[3]),
+ .CAO5(CAO[4]),
+ .CAO6(CAO[5]),
+ .CAO7(CAO[6]),
+ .CAO8(CAO[7]),
+ .CAO9(CAO[8]),
+ .CAO10(CAO[9]),
+ .CAO11(CAO[10]),
+ .CAO12(CAO[11]),
+ .CAO13(CAO[12]),
+ .CAO14(CAO[13]),
+ .CAO15(CAO[14]),
+ .CAO16(CAO[15]),
+ .CAO17(CAO[16]),
+ .CAO18(CAO[17]),
+ .CAO19(CAO[18]),
+ .CAO20(CAO[19]),
+ .CAO21(CAO[20]),
+ .CAO22(CAO[21]),
+ .CAO23(CAO[22]),
+ .CAO24(CAO[23]),
+
+ .CBI1(CBI[0]),
+ .CBI2(CBI[1]),
+ .CBI3(CBI[2]),
+ .CBI4(CBI[3]),
+ .CBI5(CBI[4]),
+ .CBI6(CBI[5]),
+ .CBI7(CBI[6]),
+ .CBI8(CBI[7]),
+ .CBI9(CBI[8]),
+ .CBI10(CBI[9]),
+ .CBI11(CBI[10]),
+ .CBI12(CBI[11]),
+ .CBI13(CBI[12]),
+ .CBI14(CBI[13]),
+ .CBI15(CBI[14]),
+ .CBI16(CBI[15]),
+ .CBI17(CBI[16]),
+ .CBI18(CBI[17]),
+
+ .CBO1(CBO[0]),
+ .CBO2(CBO[1]),
+ .CBO3(CBO[2]),
+ .CBO4(CBO[3]),
+ .CBO5(CBO[4]),
+ .CBO6(CBO[5]),
+ .CBO7(CBO[6]),
+ .CBO8(CBO[7]),
+ .CBO9(CBO[8]),
+ .CBO10(CBO[9]),
+ .CBO11(CBO[10]),
+ .CBO12(CBO[11]),
+ .CBO13(CBO[12]),
+ .CBO14(CBO[13]),
+ .CBO15(CBO[14]),
+ .CBO16(CBO[15]),
+ .CBO17(CBO[16]),
+ .CBO18(CBO[17]),
+
+ .CCI(CCI),
+ .CCO(CCO),
+ .CI(CI),
+ .CK(CK),
+ .CO43(CO43),
+ .CO57(CO57),
+
+ .CZI1(CZI[0]),
+ .CZI2(CZI[1]),
+ .CZI3(CZI[2]),
+ .CZI4(CZI[3]),
+ .CZI5(CZI[4]),
+ .CZI6(CZI[5]),
+ .CZI7(CZI[6]),
+ .CZI8(CZI[7]),
+ .CZI9(CZI[8]),
+ .CZI10(CZI[9]),
+ .CZI11(CZI[10]),
+ .CZI12(CZI[11]),
+ .CZI13(CZI[12]),
+ .CZI14(CZI[13]),
+ .CZI15(CZI[14]),
+ .CZI16(CZI[15]),
+ .CZI17(CZI[16]),
+ .CZI18(CZI[17]),
+ .CZI19(CZI[18]),
+ .CZI20(CZI[19]),
+ .CZI21(CZI[20]),
+ .CZI22(CZI[21]),
+ .CZI23(CZI[22]),
+ .CZI24(CZI[23]),
+ .CZI25(CZI[24]),
+ .CZI26(CZI[25]),
+ .CZI27(CZI[26]),
+ .CZI28(CZI[27]),
+ .CZI29(CZI[28]),
+ .CZI30(CZI[29]),
+ .CZI31(CZI[30]),
+ .CZI32(CZI[31]),
+ .CZI33(CZI[32]),
+ .CZI34(CZI[33]),
+ .CZI35(CZI[34]),
+ .CZI36(CZI[35]),
+ .CZI37(CZI[36]),
+ .CZI38(CZI[37]),
+ .CZI39(CZI[38]),
+ .CZI40(CZI[39]),
+ .CZI41(CZI[40]),
+ .CZI42(CZI[41]),
+ .CZI43(CZI[42]),
+ .CZI44(CZI[43]),
+ .CZI45(CZI[44]),
+ .CZI46(CZI[45]),
+ .CZI47(CZI[46]),
+ .CZI48(CZI[47]),
+ .CZI49(CZI[48]),
+ .CZI50(CZI[49]),
+ .CZI51(CZI[50]),
+ .CZI52(CZI[51]),
+ .CZI53(CZI[52]),
+ .CZI54(CZI[53]),
+ .CZI55(CZI[54]),
+ .CZI56(CZI[55]),
+
+ .CZO1(CZO[0]),
+ .CZO2(CZO[1]),
+ .CZO3(CZO[2]),
+ .CZO4(CZO[3]),
+ .CZO5(CZO[4]),
+ .CZO6(CZO[5]),
+ .CZO7(CZO[6]),
+ .CZO8(CZO[7]),
+ .CZO9(CZO[8]),
+ .CZO10(CZO[9]),
+ .CZO11(CZO[10]),
+ .CZO12(CZO[11]),
+ .CZO13(CZO[12]),
+ .CZO14(CZO[13]),
+ .CZO15(CZO[14]),
+ .CZO16(CZO[15]),
+ .CZO17(CZO[16]),
+ .CZO18(CZO[17]),
+ .CZO19(CZO[18]),
+ .CZO20(CZO[19]),
+ .CZO21(CZO[20]),
+ .CZO22(CZO[21]),
+ .CZO23(CZO[22]),
+ .CZO24(CZO[23]),
+ .CZO25(CZO[24]),
+ .CZO26(CZO[25]),
+ .CZO27(CZO[26]),
+ .CZO28(CZO[27]),
+ .CZO29(CZO[28]),
+ .CZO30(CZO[29]),
+ .CZO31(CZO[30]),
+ .CZO32(CZO[31]),
+ .CZO33(CZO[32]),
+ .CZO34(CZO[33]),
+ .CZO35(CZO[34]),
+ .CZO36(CZO[35]),
+ .CZO37(CZO[36]),
+ .CZO38(CZO[37]),
+ .CZO39(CZO[38]),
+ .CZO40(CZO[39]),
+ .CZO41(CZO[40]),
+ .CZO42(CZO[41]),
+ .CZO43(CZO[42]),
+ .CZO44(CZO[43]),
+ .CZO45(CZO[44]),
+ .CZO46(CZO[45]),
+ .CZO47(CZO[46]),
+ .CZO48(CZO[47]),
+ .CZO49(CZO[48]),
+ .CZO50(CZO[49]),
+ .CZO51(CZO[50]),
+ .CZO52(CZO[51]),
+ .CZO53(CZO[52]),
+ .CZO54(CZO[53]),
+ .CZO55(CZO[54]),
+ .CZO56(CZO[55]),
+
+ .D1(D[0]),
+ .D2(D[1]),
+ .D3(D[2]),
+ .D4(D[3]),
+ .D5(D[4]),
+ .D6(D[5]),
+ .D7(D[6]),
+ .D8(D[7]),
+ .D9(D[8]),
+ .D10(D[9]),
+ .D11(D[10]),
+ .D12(D[11]),
+ .D13(D[12]),
+ .D14(D[13]),
+ .D15(D[14]),
+ .D16(D[15]),
+ .D17(D[16]),
+ .D18(D[17]),
+
+ .OVF(OVF),
+ .R(R),
+ .RZ(RZ),
+ .WE(WE),
+ .WEZ(WEZ),
+
+ .Z1(Z[0]),
+ .Z2(Z[1]),
+ .Z3(Z[2]),
+ .Z4(Z[3]),
+ .Z5(Z[4]),
+ .Z6(Z[5]),
+ .Z7(Z[6]),
+ .Z8(Z[7]),
+ .Z9(Z[8]),
+ .Z10(Z[9]),
+ .Z11(Z[10]),
+ .Z12(Z[11]),
+ .Z13(Z[12]),
+ .Z14(Z[13]),
+ .Z15(Z[14]),
+ .Z16(Z[15]),
+ .Z17(Z[16]),
+ .Z18(Z[17]),
+ .Z19(Z[18]),
+ .Z20(Z[19]),
+ .Z21(Z[20]),
+ .Z22(Z[21]),
+ .Z23(Z[22]),
+ .Z24(Z[23]),
+ .Z25(Z[24]),
+ .Z26(Z[25]),
+ .Z27(Z[26]),
+ .Z28(Z[27]),
+ .Z29(Z[28]),
+ .Z30(Z[29]),
+ .Z31(Z[30]),
+ .Z32(Z[31]),
+ .Z33(Z[32]),
+ .Z34(Z[33]),
+ .Z35(Z[34]),
+ .Z36(Z[35]),
+ .Z37(Z[36]),
+ .Z38(Z[37]),
+ .Z39(Z[38]),
+ .Z40(Z[39]),
+ .Z41(Z[40]),
+ .Z42(Z[41]),
+ .Z43(Z[42]),
+ .Z44(Z[43]),
+ .Z45(Z[44]),
+ .Z46(Z[45]),
+ .Z47(Z[46]),
+ .Z48(Z[47]),
+ .Z49(Z[48]),
+ .Z50(Z[49]),
+ .Z51(Z[50]),
+ .Z52(Z[51]),
+ .Z53(Z[52]),
+ .Z54(Z[53]),
+ .Z55(Z[54]),
+ .Z56(Z[55])
+ );
+endmodule
+
+module NX_PLL_U_WRAP(R, REF, FBK, OSC, VCO, LDFO, REFO, PLL_LOCKED, PLL_LOCKEDA, ARST_CAL, CLK_CAL, CLK_CAL_DIV, CAL_LOCKED, EXT_CAL_LOCKED, CAL, CLK_DIVD, EXT_CAL, CLK_DIV);
+ input ARST_CAL;
+ output [4:0] CAL;
+ output CAL_LOCKED;
+ input CLK_CAL;
+ output CLK_CAL_DIV;
+ output [3:0] CLK_DIV;
+ output [4:0] CLK_DIVD;
+ input [4:0] EXT_CAL;
+ input EXT_CAL_LOCKED;
+ input FBK;
+ output LDFO;
+ output OSC;
+ output PLL_LOCKED;
+ output PLL_LOCKEDA;
+ input R;
+ input REF;
+ output REFO;
+ output VCO;
+ parameter cal_delay = 6'b011011;
+ parameter cal_div = 4'b0111;
+ parameter clk_cal_sel = 2'b01;
+ parameter clk_outdiv1 = 3'b000;
+ parameter clk_outdiv2 = 3'b000;
+ parameter clk_outdiv3 = 3'b000;
+ parameter clk_outdiv4 = 3'b000;
+ parameter clk_outdivd1 = 4'b0000;
+ parameter clk_outdivd2 = 4'b0000;
+ parameter clk_outdivd3 = 4'b0000;
+ parameter clk_outdivd4 = 4'b0000;
+ parameter clk_outdivd5 = 4'b0000;
+ parameter ext_fbk_on = 1'b0;
+ parameter fbk_delay = 6'b000000;
+ parameter fbk_delay_on = 1'b0;
+ parameter fbk_intdiv = 7'b0000000;
+ parameter location = "";
+ parameter pll_cpump = 4'b0000;
+ parameter pll_lock = 4'b0000;
+ parameter pll_lpf_cap = 4'b0000;
+ parameter pll_lpf_res = 4'b0000;
+ parameter pll_odf = 2'b00;
+ parameter ref_intdiv = 5'b00000;
+ parameter ref_osc_on = 1'b0;
+ parameter use_cal = 1'b0;
+ parameter use_pll = 1'b1;
+
+ NX_PLL_U #(
+ .cal_delay(cal_delay),
+ .cal_div(cal_div),
+ .clk_cal_sel(clk_cal_sel),
+ .clk_outdiv1(clk_outdiv1),
+ .clk_outdiv2(clk_outdiv2),
+ .clk_outdiv3(clk_outdiv3),
+ .clk_outdiv4(clk_outdiv4),
+ .clk_outdivd1(clk_outdivd1),
+ .clk_outdivd2(clk_outdivd2),
+ .clk_outdivd3(clk_outdivd3),
+ .clk_outdivd4(clk_outdivd4),
+ .clk_outdivd5(clk_outdivd5),
+ .ext_fbk_on(ext_fbk_on),
+ .fbk_delay(fbk_delay),
+ .fbk_delay_on(fbk_delay_on),
+ .fbk_intdiv(fbk_intdiv),
+ .location(location),
+ .pll_cpump(pll_cpump),
+ .pll_lock(pll_lock),
+ .pll_lpf_cap(pll_lpf_cap),
+ .pll_lpf_res(pll_lpf_res),
+ .pll_odf(pll_odf),
+ .ref_intdiv(ref_intdiv),
+ .ref_osc_on(ref_osc_on),
+ .use_cal(use_cal),
+ .use_pll(use_pll)
+ ) _TECHMAP_REPLACE_ (
+ .ARST_CAL(ARST_CAL),
+ .CAL1(CAL[0]),
+ .CAL2(CAL[1]),
+ .CAL3(CAL[2]),
+ .CAL4(CAL[3]),
+ .CAL5(CAL[4]),
+ .CAL_LOCKED(CAL_LOCKED),
+ .CLK_CAL(CLK_CAL),
+ .CLK_CAL_DIV(CLK_CAL_DIV),
+ .CLK_DIV1(CLK_DIV[0]),
+ .CLK_DIV2(CLK_DIV[1]),
+ .CLK_DIV3(CLK_DIV[2]),
+ .CLK_DIV4(CLK_DIV[3]),
+ .CLK_DIVD1(CLK_DIVD[0]),
+ .CLK_DIVD2(CLK_DIVD[1]),
+ .CLK_DIVD3(CLK_DIVD[2]),
+ .CLK_DIVD4(CLK_DIVD[3]),
+ .CLK_DIVD5(CLK_DIVD[4]),
+ .EXT_CAL1(EXT_CAL[0]),
+ .EXT_CAL2(EXT_CAL[1]),
+ .EXT_CAL3(EXT_CAL[2]),
+ .EXT_CAL4(EXT_CAL[3]),
+ .EXT_CAL5(EXT_CAL[4]),
+ .EXT_CAL_LOCKED(EXT_CAL_LOCKED),
+ .FBK(FBK),
+ .LDFO(LDFO),
+ .OSC(OSC),
+ .PLL_LOCKED(PLL_LOCKED),
+ .PLL_LOCKEDA(PLL_LOCKEDA),
+ .R(R),
+ .REF(REF),
+ .REFO(REFO),
+ .VCO(VCO)
+ );
+endmodule
+
+module NX_RFBDP_U_WRAP(WCK, WE, WEA, I, O, RA, WA);
+ input [17:0] I;
+ output [17:0] O;
+ input [4:0] RA;
+ input [4:0] WA;
+ input WCK;
+ input WE;
+ input WEA;
+ parameter mem_ctxt = "";
+ parameter wck_edge = 1'b0;
+
+ NX_RFB_U #(
+ .mode(0),
+ .mem_ctxt(mem_ctxt),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(WCK),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .I17(I[16]),
+ .I18(I[17]),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .O17(O[16]),
+ .O18(O[17]),
+ .RA1(RA[0]),
+ .RA2(RA[1]),
+ .RA3(RA[2]),
+ .RA4(RA[3]),
+ .RA5(RA[4]),
+ .RA6(),
+ .RA7(),
+ .RA8(),
+ .RA9(),
+ .RA10(),
+ .WA1(WA[0]),
+ .WA2(WA[1]),
+ .WA3(WA[2]),
+ .WA4(WA[3]),
+ .WA5(WA[4]),
+ .WA6(),
+ .WE(WE),
+ .WEA(WEA)
+ );
+
+endmodule
+
+module NX_RFBSP_U_WRAP(WCK, WE, WEA, I, O, WA);
+ input [17:0] I;
+ output [17:0] O;
+ input [4:0] WA;
+ input WCK;
+ input WE;
+ input WEA;
+ parameter mem_ctxt = "";
+ parameter wck_edge = 1'b0;
+
+ NX_RFB_U #(
+ .mode(1),
+ .mem_ctxt(mem_ctxt),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(WCK),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .I17(I[16]),
+ .I18(I[17]),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .O17(O[16]),
+ .O18(O[17]),
+ .RA1(),
+ .RA2(),
+ .RA3(),
+ .RA4(),
+ .RA5(),
+ .RA6(),
+ .RA7(),
+ .RA8(),
+ .RA9(),
+ .RA10(),
+ .WA1(WA[0]),
+ .WA2(WA[1]),
+ .WA3(WA[2]),
+ .WA4(WA[3]),
+ .WA5(WA[4]),
+ .WA6(),
+ .WE(WE),
+ .WEA(WEA)
+ );
+endmodule
+
+module NX_XRFB_64x18(WCK, WE, WEA, I, O, RA, WA);
+ input [17:0] I;
+ output [17:0] O;
+ input [5:0] RA;
+ input [5:0] WA;
+ input WCK;
+ input WE;
+ input WEA;
+ parameter mem_ctxt = "";
+ parameter wck_edge = 1'b0;
+
+ NX_RFB_U #(
+ .mode(2),
+ .mem_ctxt(mem_ctxt),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(WCK),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .I17(I[16]),
+ .I18(I[17]),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .O17(O[16]),
+ .O18(O[17]),
+ .RA1(RA[0]),
+ .RA2(RA[1]),
+ .RA3(RA[2]),
+ .RA4(RA[3]),
+ .RA5(RA[4]),
+ .RA6(RA[5]),
+ .RA7(),
+ .RA8(),
+ .RA9(),
+ .RA10(),
+ .WA1(WA[0]),
+ .WA2(WA[1]),
+ .WA3(WA[2]),
+ .WA4(WA[3]),
+ .WA5(WA[4]),
+ .WA6(WA[5]),
+ .WE(WE),
+ .WEA(WEA)
+ );
+endmodule
+
+module NX_XRFB_32x36(WCK, WE, WEA, I, O, RA, WA);
+ input [35:0] I;
+ output [35:0] O;
+ input [4:0] RA;
+ input [4:0] WA;
+ input WCK;
+ input WE;
+ input WEA;
+ parameter mem_ctxt = "";
+ parameter wck_edge = 1'b0;
+
+ NX_RFB_U #(
+ .mode(3),
+ .mem_ctxt(mem_ctxt),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(WCK),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .I17(I[16]),
+ .I18(I[17]),
+ .I19(I[18]),
+ .I20(I[19]),
+ .I21(I[20]),
+ .I22(I[21]),
+ .I23(I[22]),
+ .I24(I[23]),
+ .I25(I[24]),
+ .I26(I[25]),
+ .I27(I[26]),
+ .I28(I[27]),
+ .I29(I[28]),
+ .I30(I[29]),
+ .I31(I[30]),
+ .I32(I[31]),
+ .I33(I[32]),
+ .I34(I[33]),
+ .I35(I[34]),
+ .I36(I[35]),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .O17(O[16]),
+ .O18(O[17]),
+ .O19(O[18]),
+ .O20(O[19]),
+ .O21(O[20]),
+ .O22(O[21]),
+ .O23(O[22]),
+ .O24(O[23]),
+ .O25(O[24]),
+ .O26(O[25]),
+ .O27(O[26]),
+ .O28(O[27]),
+ .O29(O[28]),
+ .O30(O[29]),
+ .O31(O[30]),
+ .O32(O[31]),
+ .O33(O[32]),
+ .O34(O[33]),
+ .O35(O[34]),
+ .O36(O[35]),
+ .RA1(RA[0]),
+ .RA2(RA[1]),
+ .RA3(RA[2]),
+ .RA4(RA[3]),
+ .RA5(RA[4]),
+ .RA6(),
+ .RA7(),
+ .RA8(),
+ .RA9(),
+ .RA10(),
+ .WA1(WA[0]),
+ .WA2(WA[1]),
+ .WA3(WA[2]),
+ .WA4(WA[3]),
+ .WA5(WA[4]),
+ .WA6(),
+ .WE(WE),
+ .WEA(WEA)
+ );
+endmodule
+
+module NX_XRFB_2R_1W(WCK, WE, WEA, I, AO, BO, WA, ARA, BRA);
+ output [17:0] AO;
+ input [4:0] ARA;
+ output [17:0] BO;
+ input [4:0] BRA;
+ input [17:0] I;
+ input [4:0] WA;
+ input WCK;
+ input WE;
+ input WEA;
+ parameter mem_ctxt = "";
+ parameter wck_edge = 1'b0;
+
+ NX_RFB_U #(
+ .mode(32'd4),
+ .mem_ctxt(mem_ctxt),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(WCK),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .I17(I[16]),
+ .I18(I[17]),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(AO[0]),
+ .O2(AO[1]),
+ .O3(AO[2]),
+ .O4(AO[3]),
+ .O5(AO[4]),
+ .O6(AO[5]),
+ .O7(AO[6]),
+ .O8(AO[7]),
+ .O9(AO[8]),
+ .O10(AO[9]),
+ .O11(AO[10]),
+ .O12(AO[11]),
+ .O13(AO[12]),
+ .O14(AO[13]),
+ .O15(AO[14]),
+ .O16(AO[15]),
+ .O17(AO[16]),
+ .O18(AO[17]),
+ .O19(BO[0]),
+ .O20(BO[1]),
+ .O21(BO[2]),
+ .O22(BO[3]),
+ .O23(BO[4]),
+ .O24(BO[5]),
+ .O25(BO[6]),
+ .O26(BO[7]),
+ .O27(BO[8]),
+ .O28(BO[9]),
+ .O29(BO[10]),
+ .O30(BO[11]),
+ .O31(BO[12]),
+ .O32(BO[13]),
+ .O33(BO[14]),
+ .O34(BO[15]),
+ .O35(BO[16]),
+ .O36(BO[17]),
+ .RA1(ARA[0]),
+ .RA2(ARA[1]),
+ .RA3(ARA[2]),
+ .RA4(ARA[3]),
+ .RA5(ARA[4]),
+ .RA6(BRA[0]),
+ .RA7(BRA[1]),
+ .RA8(BRA[2]),
+ .RA9(BRA[3]),
+ .RA10(BRA[4]),
+ .WA1(WA[0]),
+ .WA2(WA[1]),
+ .WA3(WA[2]),
+ .WA4(WA[3]),
+ .WA5(WA[4]),
+ .WA6(),
+ .WE(WE),
+ .WEA(WEA)
+ );
+endmodule
+
+module NX_RFB(RCK, WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, COR, ERR, O1
+, O2, O3, O4, O5, O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, RA1, RA2, RA3, RA4, RA5, RA6
+, RE, WA1, WA2, WA3, WA4, WA5, WA6, WE);
+ output COR;
+ output ERR;
+ input I1;
+ input I10;
+ input I11;
+ input I12;
+ input I13;
+ input I14;
+ input I15;
+ input I16;
+ input I2;
+ input I3;
+ input I4;
+ input I5;
+ input I6;
+ input I7;
+ input I8;
+ input I9;
+ output O1;
+ output O10;
+ output O11;
+ output O12;
+ output O13;
+ output O14;
+ output O15;
+ output O16;
+ output O2;
+ output O3;
+ output O4;
+ output O5;
+ output O6;
+ output O7;
+ output O8;
+ output O9;
+ input RA1;
+ input RA2;
+ input RA3;
+ input RA4;
+ input RA5;
+ input RA6;
+ input RCK;
+ input RE;
+ input WA1;
+ input WA2;
+ input WA3;
+ input WA4;
+ input WA5;
+ input WA6;
+ input WCK;
+ input WE;
+ parameter addr_mask = 5'b00000;
+ parameter mem_ctxt = "";
+ parameter rck_edge = 1'b0;
+ parameter wck_edge = 1'b0;
+ parameter we_mask = 1'b0;
+ parameter wea_mask = 1'b0;
+
+ wire [15:0] D;
+ wire [15:0] Q;
+
+ NX_RFB_U #(
+ .mem_ctxt(mem_ctxt),
+ .mode(2),
+ .wck_edge(wck_edge)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(WCK),
+ .I1(I1),
+ .I2(I2),
+ .I3(I3),
+ .I4(I4),
+ .I5(I5),
+ .I6(I6),
+ .I7(I7),
+ .I8(I8),
+ .I9(I9),
+ .I10(I10),
+ .I11(I11),
+ .I12(I12),
+ .I13(I13),
+ .I14(I14),
+ .I15(I15),
+ .I16(I16),
+ .I17(),
+ .I18(),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(D[0]),
+ .O2(D[1]),
+ .O3(D[2]),
+ .O4(D[3]),
+ .O5(D[4]),
+ .O6(D[5]),
+ .O7(D[6]),
+ .O8(D[7]),
+ .O9(D[8]),
+ .O10(D[9]),
+ .O11(D[10]),
+ .O12(D[11]),
+ .O13(D[12]),
+ .O14(D[13]),
+ .O15(D[14]),
+ .O16(D[15]),
+ .RA1(RA1),
+ .RA2(RA2),
+ .RA3(RA3),
+ .RA4(RA4),
+ .RA5(RA5),
+ .RA6(RA6),
+ .RA7(),
+ .RA8(),
+ .RA9(),
+ .RA10(),
+ .WA1(WA1),
+ .WA2(WA2),
+ .WA3(WA3),
+ .WA4(WA4),
+ .WA5(WA5),
+ .WA6(WA6),
+ .WE(WE),
+ .WEA()
+ );
+
+ genvar i;
+ generate for (i = 0; i < 16; i = i + 1) begin:q_reg
+ NX_DFF #(
+ .dff_edge(rck_edge),
+ .dff_init(1'b0),
+ .dff_load(1'b1)
+ ) out_reg_i (
+ .CK(RCK),
+ .I(D[i]),
+ .L(RE),
+ .R(),
+ .O(Q[i])
+ );
+ end endgenerate;
+ assign O1=Q[0];
+ assign O2=Q[1];
+ assign O3=Q[2];
+ assign O4=Q[3];
+ assign O5=Q[4];
+ assign O6=Q[5];
+ assign O7=Q[6];
+ assign O8=Q[7];
+ assign O9=Q[8];
+ assign O10=Q[9];
+ assign O11=Q[10];
+ assign O12=Q[11];
+ assign O13=Q[12];
+ assign O14=Q[13];
+ assign O15=Q[14];
+ assign O16=Q[15];
+
+ assign COR=1'b0;
+ assign ERR=1'b0;
+endmodule
+
+module NX_FIFO_DPREG(RCK, WCK, WE, WEA, WRSTI, WRSTO, WEQ, RRSTI, RRSTO, REQ, I, O, WAI, WAO, RAI, RAO);
+ input [17:0] I;
+ output [17:0] O;
+ input [5:0] RAI;
+ output [5:0] RAO;
+ input RCK;
+ output REQ;
+ input RRSTI;
+ output RRSTO;
+ input [5:0] WAI;
+ output [5:0] WAO;
+ input WCK;
+ input WE;
+ input WEA;
+ output WEQ;
+ input WRSTI;
+ output WRSTO;
+ parameter rck_edge = 1'b0;
+ parameter read_addr_inv = 6'b000000;
+ parameter use_read_arst = 1'b0;
+ parameter use_write_arst = 1'b0;
+ parameter wck_edge = 1'b0;
+
+ NX_FIFO_U #(
+ .mode(0),
+ .wck_edge(wck_edge),
+ .rck_edge(rck_edge),
+ .read_addr_inv(read_addr_inv),
+ .use_write_arst(use_write_arst),
+ .use_read_arst(use_read_arst)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(RCK),
+ .WCK(WCK),
+ .WE(WE),
+ .WEA(WEA),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .I17(I[16]),
+ .I18(I[17]),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .O17(O[16]),
+ .O18(O[17]),
+ .WRSTI(WRSTI),
+ .WAI1(WAI[0]),
+ .WAI2(WAI[1]),
+ .WAI3(WAI[2]),
+ .WAI4(WAI[3]),
+ .WAI5(WAI[4]),
+ .WAI6(WAI[5]),
+ .WAI7(),
+ .WRSTO(WRSTO),
+ .WAO1(WAO[0]),
+ .WAO2(WAO[1]),
+ .WAO3(WAO[2]),
+ .WAO4(WAO[3]),
+ .WAO5(WAO[4]),
+ .WAO6(WAO[5]),
+ .WEQ1(WEQ),
+ .RRSTI(RRSTI),
+ .RAI1(RAI[0]),
+ .RAI2(RAI[1]),
+ .RAI3(RAI[2]),
+ .RAI4(RAI[3]),
+ .RAI5(RAI[4]),
+ .RAI6(RAI[5]),
+ .RAI7(),
+ .RRSTO(RRSTO),
+ .RAO1(RAO[0]),
+ .RAO2(RAO[1]),
+ .RAO3(RAO[2]),
+ .RAO4(RAO[3]),
+ .RAO5(RAO[4]),
+ .RAO6(RAO[5]),
+ .REQ1(REQ)
+ );
+endmodule
+
+module NX_XFIFO_64x18(RCK, WCK, WE, WEA, WRSTI, RRSTI, I, O, WEQ, REQ, WAI, WAO, RAI, RAO);
+ input [17:0] I;
+ output [17:0] O;
+ input [6:0] RAI;
+ output [6:0] RAO;
+ input RCK;
+ output [1:0] REQ;
+ input RRSTI;
+ input [6:0] WAI;
+ output [6:0] WAO;
+ input WCK;
+ input WE;
+ input WEA;
+ output [1:0] WEQ;
+ input WRSTI;
+ parameter rck_edge = 1'b0;
+ parameter read_addr_inv = 7'b0000000;
+ parameter use_read_arst = 1'b0;
+ parameter use_write_arst = 1'b0;
+ parameter wck_edge = 1'b0;
+
+ NX_FIFO_U #(
+ .mode(1),
+ .wck_edge(wck_edge),
+ .rck_edge(rck_edge),
+ .read_addr_inv(read_addr_inv),
+ .use_write_arst(use_write_arst),
+ .use_read_arst(use_read_arst)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(RCK),
+ .WCK(WCK),
+ .WE(WE),
+ .WEA(WEA),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .I17(I[16]),
+ .I18(I[17]),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .O17(O[16]),
+ .O18(O[17]),
+ .WRSTI(WRSTI),
+ .WAI1(WAI[0]),
+ .WAI2(WAI[1]),
+ .WAI3(WAI[2]),
+ .WAI4(WAI[3]),
+ .WAI5(WAI[4]),
+ .WAI6(WAI[5]),
+ .WAI7(WAI[6]),
+ .WAO1(WAO[0]),
+ .WAO2(WAO[1]),
+ .WAO3(WAO[2]),
+ .WAO4(WAO[3]),
+ .WAO5(WAO[4]),
+ .WAO6(WAO[5]),
+ .WAO7(WAO[6]),
+ .WEQ1(WEQ[0]),
+ .WEQ2(WEQ[1]),
+ .RRSTI(RRSTI),
+ .RAI1(RAI[0]),
+ .RAI2(RAI[1]),
+ .RAI3(RAI[2]),
+ .RAI4(RAI[3]),
+ .RAI5(RAI[4]),
+ .RAI6(RAI[5]),
+ .RAI7(RAI[6]),
+ .RAO1(RAO[0]),
+ .RAO2(RAO[1]),
+ .RAO3(RAO[2]),
+ .RAO4(RAO[3]),
+ .RAO5(RAO[4]),
+ .RAO6(RAO[5]),
+ .RAO7(RAO[6]),
+ .REQ1(REQ[0]),
+ .REQ2(REQ[1])
+ );
+endmodule
+
+module NX_XFIFO_32x36(RCK, WCK, WE, WEA, WRSTI, WEQ, RRSTI, REQ, I, O, WAI, WAO, RAI, RAO);
+ input [35:0] I;
+ output [35:0] O;
+ input [5:0] RAI;
+ output [5:0] RAO;
+ input RCK;
+ output REQ;
+ input RRSTI;
+ input [5:0] WAI;
+ output [5:0] WAO;
+ input WCK;
+ input WE;
+ input WEA;
+ output WEQ;
+ input WRSTI;
+ parameter rck_edge = 1'b0;
+ parameter read_addr_inv = 7'b0000000;
+ parameter use_read_arst = 1'b0;
+ parameter use_write_arst = 1'b0;
+ parameter wck_edge = 1'b0;
+
+ NX_FIFO_U #(
+ .mode(2),
+ .wck_edge(wck_edge),
+ .rck_edge(rck_edge),
+ .read_addr_inv(read_addr_inv),
+ .use_write_arst(use_write_arst),
+ .use_read_arst(use_read_arst)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(RCK),
+ .WCK(WCK),
+ .WE(WE),
+ .WEA(WEA),
+ .I1(I[0]),
+ .I2(I[1]),
+ .I3(I[2]),
+ .I4(I[3]),
+ .I5(I[4]),
+ .I6(I[5]),
+ .I7(I[6]),
+ .I8(I[7]),
+ .I9(I[8]),
+ .I10(I[9]),
+ .I11(I[10]),
+ .I12(I[11]),
+ .I13(I[12]),
+ .I14(I[13]),
+ .I15(I[14]),
+ .I16(I[15]),
+ .I17(I[16]),
+ .I18(I[17]),
+ .I19(I[18]),
+ .I20(I[19]),
+ .I21(I[20]),
+ .I22(I[21]),
+ .I23(I[22]),
+ .I24(I[23]),
+ .I25(I[24]),
+ .I26(I[25]),
+ .I27(I[26]),
+ .I28(I[27]),
+ .I29(I[28]),
+ .I30(I[29]),
+ .I31(I[30]),
+ .I32(I[31]),
+ .I33(I[32]),
+ .I34(I[33]),
+ .I35(I[34]),
+ .I36(I[35]),
+ .O1(O[0]),
+ .O2(O[1]),
+ .O3(O[2]),
+ .O4(O[3]),
+ .O5(O[4]),
+ .O6(O[5]),
+ .O7(O[6]),
+ .O8(O[7]),
+ .O9(O[8]),
+ .O10(O[9]),
+ .O11(O[10]),
+ .O12(O[11]),
+ .O13(O[12]),
+ .O14(O[13]),
+ .O15(O[14]),
+ .O16(O[15]),
+ .O17(O[16]),
+ .O18(O[17]),
+ .O19(O[18]),
+ .O20(O[19]),
+ .O21(O[20]),
+ .O22(O[21]),
+ .O23(O[22]),
+ .O24(O[23]),
+ .O25(O[24]),
+ .O26(O[25]),
+ .O27(O[26]),
+ .O28(O[27]),
+ .O29(O[28]),
+ .O30(O[29]),
+ .O31(O[30]),
+ .O32(O[31]),
+ .O33(O[32]),
+ .O34(O[33]),
+ .O35(O[34]),
+ .O36(O[35]),
+ .WRSTI(WRSTI),
+ .WAI1(WAI[0]),
+ .WAI2(WAI[1]),
+ .WAI3(WAI[2]),
+ .WAI4(WAI[3]),
+ .WAI5(WAI[4]),
+ .WAI6(WAI[5]),
+ .WAI7(),
+ .WAO1(WAO[0]),
+ .WAO2(WAO[1]),
+ .WAO3(WAO[2]),
+ .WAO4(WAO[3]),
+ .WAO5(WAO[4]),
+ .WAO6(WAO[5]),
+ .WEQ1(WEQ),
+ .RRSTI(RRSTI),
+ .RAI1(RAI[0]),
+ .RAI2(RAI[1]),
+ .RAI3(RAI[2]),
+ .RAI4(RAI[3]),
+ .RAI5(RAI[4]),
+ .RAI6(RAI[5]),
+ .RAI7(),
+ .RAO1(RAO[0]),
+ .RAO2(RAO[1]),
+ .RAO3(RAO[2]),
+ .RAO4(RAO[3]),
+ .RAO5(RAO[4]),
+ .RAO6(RAO[5]),
+ .REQ1(REQ)
+ );
+endmodule
+
+//TODO
+module ACC84_2DSP(clk, rst, X, Z);
+ input [83:0] X;
+ output [84:0] Z;
+ input clk;
+ input rst;
+ parameter g_pipe = 2;
+endmodule
+
+//TODO
+module ACC92_2DSP(clk, rst, X, Z);
+ input [55:0] X;
+ output [91:0] Z;
+ input clk;
+ input rst;
+ parameter g_pipe = 2;
+endmodule
+
+//TODO
+module ACC98_2DSP(clk, rst, X, Z);
+ input [55:0] X;
+ output [97:0] Z;
+ input clk;
+ input rst;
+ parameter g_pipe = 2;
+endmodule
+
+//TODO
+module ADD84_1DSP_2CYCLES(clk, rst, X, Y, Z);
+ input [41:0] X;
+ input [41:0] Y;
+ output [84:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module ADD84_2DSP(clk, rst, X, Y, Z);
+ input [83:0] X;
+ input [83:0] Y;
+ output [84:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module SMACC24x18_1DSP(clk, rst, A, B, Z);
+ input [23:0] A;
+ input [17:0] B;
+ output [55:0] Z;
+ input clk;
+ input rst;
+ parameter g_pipe = 1;
+endmodule
+
+//TODO
+module SMACC24x32_2DSP(clk, rst, A, B, Z);
+ input [23:0] A;
+ input [31:0] B;
+ output [55:0] Z;
+ input clk;
+ input rst;
+ parameter g_pipe = 1;
+endmodule
+
+//TODO
+module SMACC24x32_enable_2DSP(clk, rst, we, A, B, Z);
+ input [23:0] A;
+ input [31:0] B;
+ output [55:0] Z;
+ input clk;
+ input rst;
+ input we;
+ parameter STAGE_1 = "false";
+ parameter STAGE_2 = "false";
+ parameter STAGE_3 = "false";
+ parameter STAGE_4 = "false";
+endmodule
+
+//TODO
+module SMUL24x32_2DSP(clk, rst, A, B, Z);
+ input [23:0] A;
+ input [31:0] B;
+ output [54:0] Z;
+ input clk;
+ input rst;
+ parameter g_pipe = 1;
+endmodule
+
+//TODO
+module SMUL24x32_2DSP_ACC_2DSP(clk, rst, we, A, B, Z);
+ input [23:0] A;
+ input [31:0] B;
+ output [97:0] Z;
+ input clk;
+ input rst;
+ input we;
+ parameter STAGE_1 = "false";
+ parameter STAGE_2 = "false";
+ parameter STAGE_3 = "false";
+endmodule
+
+//TODO
+module SMUL47x35_4DSP(clk, rst, A, B, Z);
+ input [46:0] A;
+ input [34:0] B;
+ output [80:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module UMADD24_2DSP(clk, rst, A, B, C, Z);
+ input [23:0] A;
+ input [31:0] B;
+ input [55:0] C;
+ output [55:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL24x32_1DSP_2CYCLES(clk, rst, A, B, Z);
+ input [23:0] A;
+ input [15:0] B;
+ output [55:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL24x32_2DSP(clk, rst, A, B, Z);
+ input [23:0] A;
+ input [31:0] B;
+ output [55:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL24x36_1DSP_2CYCLES(clk, rst, A, B, Z);
+ input [23:0] A;
+ input [17:0] B;
+ output [59:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL24x36_2DSP(clk, rst, A, B, Z);
+ input [23:0] A;
+ input [35:0] B;
+ output [59:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL48x36_1DSP_4CYCLES(clk, rst, A, B, Z);
+ input [23:0] A;
+ input [17:0] B;
+ output [83:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module UMUL48x36_4DSP(clk, rst, A, B, Z);
+ input [47:0] A;
+ input [35:0] B;
+ output [83:0] Z;
+ input clk;
+ input rst;
+ parameter piped = "true";
+endmodule
+
+//TODO
+module NX_HSSL_U_FULL(hssl_clk_user_tx_i, hssl_clk_user_rx_i, hssl_clk_ref_i, hssl_clock_o, hssl_rclock_o, usr_dyn_cfg_en_i, usr_dyn_cfg_calibration_cs_n_i, usr_dyn_cfg_we_n_i, usr_dyn_cfg_wdata_sel_i, usr_pll_pma_rst_n_i, usr_pll_pma_pwr_down_n_i, usr_main_rst_n_i, usr_pll_lock_o, usr_pll_pma_lock_analog_o, usr_pll_ckfb_lock_o, usr_calibrate_pma_out_o, usr_main_async_debug_ack_i, usr_main_async_debug_req_o, scan_en_i, usr_tx0_ctrl_replace_en_i, usr_tx0_rst_n_i
+, usr_tx0_busy_o, usr_tx0_ctrl_invalid_k_o, usr_tx0_ctrl_driver_pwrdwn_n_i, usr_tx0_pma_clk_en_i, usr_tx0_pma_tx_clk_o, usr_rx0_ctrl_dscr_en_i, usr_rx0_ctrl_dec_en_i, usr_rx0_ctrl_align_en_i, usr_rx0_ctrl_align_sync_i, usr_rx0_ctrl_replace_en_i, usr_rx0_ctrl_el_buff_rst_i, usr_rx0_rst_n_i, usr_rx0_pma_rst_n_i, usr_rx0_pma_m_eye_rst_i, usr_rx0_pma_pwr_down_n_i, usr_rx0_ctrl_char_is_aligned_o, usr_rx0_ctrl_valid_realign_o, usr_rx0_busy_o, usr_rx0_pma_loss_of_signal_o, usr_rx0_pma_ll_fast_locked_o, usr_rx0_pma_ll_slow_locked_o
+, usr_rx0_pma_pll_lock_o, usr_rx0_pma_pll_lock_track_o, usr_tx1_ctrl_replace_en_i, usr_tx1_rst_n_i, usr_tx1_busy_o, usr_tx1_ctrl_invalid_k_o, usr_tx1_ctrl_driver_pwrdwn_n_i, usr_tx1_pma_clk_en_i, usr_tx1_pma_tx_clk_o, usr_rx1_ctrl_dscr_en_i, usr_rx1_ctrl_dec_en_i, usr_rx1_ctrl_align_en_i, usr_rx1_ctrl_align_sync_i, usr_rx1_ctrl_replace_en_i, usr_rx1_ctrl_el_buff_rst_i, usr_rx1_rst_n_i, usr_rx1_pma_rst_n_i, usr_rx1_pma_m_eye_rst_i, usr_rx1_pma_pwr_down_n_i, usr_rx1_ctrl_char_is_aligned_o, usr_rx1_ctrl_valid_realign_o
+, usr_rx1_busy_o, usr_rx1_pma_loss_of_signal_o, usr_rx1_pma_ll_fast_locked_o, usr_rx1_pma_ll_slow_locked_o, usr_rx1_pma_pll_lock_o, usr_rx1_pma_pll_lock_track_o, usr_tx2_ctrl_replace_en_i, usr_tx2_rst_n_i, usr_tx2_busy_o, usr_tx2_ctrl_invalid_k_o, usr_tx2_ctrl_driver_pwrdwn_n_i, usr_tx2_pma_clk_en_i, usr_tx2_pma_tx_clk_o, usr_rx2_ctrl_dscr_en_i, usr_rx2_ctrl_dec_en_i, usr_rx2_ctrl_align_en_i, usr_rx2_ctrl_align_sync_i, usr_rx2_ctrl_replace_en_i, usr_rx2_ctrl_el_buff_rst_i, usr_rx2_rst_n_i, usr_rx2_pma_rst_n_i
+, usr_rx2_pma_m_eye_rst_i, usr_rx2_pma_pwr_down_n_i, usr_rx2_ctrl_char_is_aligned_o, usr_rx2_ctrl_valid_realign_o, usr_rx2_busy_o, usr_rx2_pma_loss_of_signal_o, usr_rx2_pma_ll_fast_locked_o, usr_rx2_pma_ll_slow_locked_o, usr_rx2_pma_pll_lock_o, usr_rx2_pma_pll_lock_track_o, usr_tx3_ctrl_replace_en_i, usr_tx3_rst_n_i, usr_tx3_busy_o, usr_tx3_ctrl_invalid_k_o, usr_tx3_ctrl_driver_pwrdwn_n_i, usr_tx3_pma_clk_en_i, usr_tx3_pma_tx_clk_o, usr_rx3_ctrl_dscr_en_i, usr_rx3_ctrl_dec_en_i, usr_rx3_ctrl_align_en_i, usr_rx3_ctrl_align_sync_i
+, usr_rx3_ctrl_replace_en_i, usr_rx3_ctrl_el_buff_rst_i, usr_rx3_rst_n_i, usr_rx3_pma_rst_n_i, usr_rx3_pma_m_eye_rst_i, usr_rx3_pma_pwr_down_n_i, usr_rx3_ctrl_char_is_aligned_o, usr_rx3_ctrl_valid_realign_o, usr_rx3_busy_o, usr_rx3_pma_loss_of_signal_o, usr_rx3_pma_ll_fast_locked_o, usr_rx3_pma_ll_slow_locked_o, usr_rx3_pma_pll_lock_o, usr_rx3_pma_pll_lock_track_o, usr_tx0_ctrl_enc_en_i, usr_tx0_ctrl_char_is_k_i, usr_tx0_ctrl_scr_en_i, usr_tx0_ctrl_end_of_multiframe_i, usr_tx0_ctrl_end_of_frame_i, usr_tx0_data_i, usr_rx0_data_o
+, usr_rx0_ctrl_ovs_bit_sel_i, usr_rx0_ctrl_char_is_comma_o, usr_rx0_ctrl_char_is_k_o, usr_rx0_ctrl_not_in_table_o, usr_rx0_ctrl_disp_err_o, usr_rx0_ctrl_char_is_a_o, usr_rx0_ctrl_char_is_f_o, usr_rx0_test_o, usr_tx1_ctrl_enc_en_i, usr_tx1_ctrl_char_is_k_i, usr_tx1_ctrl_scr_en_i, usr_tx1_ctrl_end_of_multiframe_i, usr_tx1_ctrl_end_of_frame_i, usr_tx1_data_i, usr_rx1_data_o, usr_rx1_ctrl_ovs_bit_sel_i, usr_rx1_ctrl_char_is_comma_o, usr_rx1_ctrl_char_is_k_o, usr_rx1_ctrl_not_in_table_o, usr_rx1_ctrl_disp_err_o, usr_rx1_ctrl_char_is_a_o
+, usr_rx1_ctrl_char_is_f_o, usr_rx1_test_o, usr_tx2_ctrl_enc_en_i, usr_tx2_ctrl_char_is_k_i, usr_tx2_ctrl_scr_en_i, usr_tx2_ctrl_end_of_multiframe_i, usr_tx2_ctrl_end_of_frame_i, usr_tx2_data_i, usr_rx2_data_o, usr_rx2_ctrl_ovs_bit_sel_i, usr_rx2_ctrl_char_is_comma_o, usr_rx2_ctrl_char_is_k_o, usr_rx2_ctrl_not_in_table_o, usr_rx2_ctrl_disp_err_o, usr_rx2_ctrl_char_is_a_o, usr_rx2_ctrl_char_is_f_o, usr_rx2_test_o, usr_tx3_ctrl_enc_en_i, usr_tx3_ctrl_char_is_k_i, usr_tx3_ctrl_scr_en_i, usr_tx3_ctrl_end_of_multiframe_i
+, usr_tx3_ctrl_end_of_frame_i, usr_tx3_data_i, usr_rx3_data_o, usr_rx3_ctrl_ovs_bit_sel_i, usr_rx3_ctrl_char_is_comma_o, usr_rx3_ctrl_char_is_k_o, usr_rx3_ctrl_not_in_table_o, usr_rx3_ctrl_disp_err_o, usr_rx3_ctrl_char_is_a_o, usr_rx3_ctrl_char_is_f_o, usr_rx3_test_o, usr_dyn_cfg_addr_i, usr_dyn_cfg_wdata_i, usr_main_async_debug_lane_sel_i, usr_main_rx_pma_ll_out_o, scan_in_i, scan_out_o, usr_rx0_ctrl_debug_sel_i, usr_rx1_ctrl_debug_sel_i, usr_rx2_ctrl_debug_sel_i, usr_rx3_ctrl_debug_sel_i
+, usr_dyn_cfg_lane_cs_n_i);
+ input hssl_clk_ref_i;
+ input hssl_clk_user_rx_i;
+ input hssl_clk_user_tx_i;
+ output hssl_clock_o;
+ output hssl_rclock_o;
+ input scan_en_i;
+ input [7:0] scan_in_i;
+ output [7:0] scan_out_o;
+ output usr_calibrate_pma_out_o;
+ input [3:0] usr_dyn_cfg_addr_i;
+ input usr_dyn_cfg_calibration_cs_n_i;
+ input usr_dyn_cfg_en_i;
+ input [3:0] usr_dyn_cfg_lane_cs_n_i;
+ input [11:0] usr_dyn_cfg_wdata_i;
+ input usr_dyn_cfg_wdata_sel_i;
+ input usr_dyn_cfg_we_n_i;
+ input usr_main_async_debug_ack_i;
+ input [1:0] usr_main_async_debug_lane_sel_i;
+ output usr_main_async_debug_req_o;
+ input usr_main_rst_n_i;
+ output [19:0] usr_main_rx_pma_ll_out_o;
+ output usr_pll_ckfb_lock_o;
+ output usr_pll_lock_o;
+ output usr_pll_pma_lock_analog_o;
+ input usr_pll_pma_pwr_down_n_i;
+ input usr_pll_pma_rst_n_i;
+ output usr_rx0_busy_o;
+ input usr_rx0_ctrl_align_en_i;
+ input usr_rx0_ctrl_align_sync_i;
+ output [7:0] usr_rx0_ctrl_char_is_a_o;
+ output usr_rx0_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx0_ctrl_char_is_comma_o;
+ output [7:0] usr_rx0_ctrl_char_is_f_o;
+ output [7:0] usr_rx0_ctrl_char_is_k_o;
+ input [2:0] usr_rx0_ctrl_debug_sel_i;
+ input usr_rx0_ctrl_dec_en_i;
+ output [7:0] usr_rx0_ctrl_disp_err_o;
+ input usr_rx0_ctrl_dscr_en_i;
+ input usr_rx0_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx0_ctrl_not_in_table_o;
+ input [1:0] usr_rx0_ctrl_ovs_bit_sel_i;
+ input usr_rx0_ctrl_replace_en_i;
+ output usr_rx0_ctrl_valid_realign_o;
+ output [63:0] usr_rx0_data_o;
+ output usr_rx0_pma_ll_fast_locked_o;
+ output usr_rx0_pma_ll_slow_locked_o;
+ output usr_rx0_pma_loss_of_signal_o;
+ input usr_rx0_pma_m_eye_rst_i;
+ output usr_rx0_pma_pll_lock_o;
+ output usr_rx0_pma_pll_lock_track_o;
+ input usr_rx0_pma_pwr_down_n_i;
+ input usr_rx0_pma_rst_n_i;
+ input usr_rx0_rst_n_i;
+ output [7:0] usr_rx0_test_o;
+ output usr_rx1_busy_o;
+ input usr_rx1_ctrl_align_en_i;
+ input usr_rx1_ctrl_align_sync_i;
+ output [7:0] usr_rx1_ctrl_char_is_a_o;
+ output usr_rx1_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx1_ctrl_char_is_comma_o;
+ output [7:0] usr_rx1_ctrl_char_is_f_o;
+ output [7:0] usr_rx1_ctrl_char_is_k_o;
+ input [2:0] usr_rx1_ctrl_debug_sel_i;
+ input usr_rx1_ctrl_dec_en_i;
+ output [7:0] usr_rx1_ctrl_disp_err_o;
+ input usr_rx1_ctrl_dscr_en_i;
+ input usr_rx1_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx1_ctrl_not_in_table_o;
+ input [1:0] usr_rx1_ctrl_ovs_bit_sel_i;
+ input usr_rx1_ctrl_replace_en_i;
+ output usr_rx1_ctrl_valid_realign_o;
+ output [63:0] usr_rx1_data_o;
+ output usr_rx1_pma_ll_fast_locked_o;
+ output usr_rx1_pma_ll_slow_locked_o;
+ output usr_rx1_pma_loss_of_signal_o;
+ input usr_rx1_pma_m_eye_rst_i;
+ output usr_rx1_pma_pll_lock_o;
+ output usr_rx1_pma_pll_lock_track_o;
+ input usr_rx1_pma_pwr_down_n_i;
+ input usr_rx1_pma_rst_n_i;
+ input usr_rx1_rst_n_i;
+ output [7:0] usr_rx1_test_o;
+ output usr_rx2_busy_o;
+ input usr_rx2_ctrl_align_en_i;
+ input usr_rx2_ctrl_align_sync_i;
+ output [7:0] usr_rx2_ctrl_char_is_a_o;
+ output usr_rx2_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx2_ctrl_char_is_comma_o;
+ output [7:0] usr_rx2_ctrl_char_is_f_o;
+ output [7:0] usr_rx2_ctrl_char_is_k_o;
+ input [2:0] usr_rx2_ctrl_debug_sel_i;
+ input usr_rx2_ctrl_dec_en_i;
+ output [7:0] usr_rx2_ctrl_disp_err_o;
+ input usr_rx2_ctrl_dscr_en_i;
+ input usr_rx2_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx2_ctrl_not_in_table_o;
+ input [1:0] usr_rx2_ctrl_ovs_bit_sel_i;
+ input usr_rx2_ctrl_replace_en_i;
+ output usr_rx2_ctrl_valid_realign_o;
+ output [63:0] usr_rx2_data_o;
+ output usr_rx2_pma_ll_fast_locked_o;
+ output usr_rx2_pma_ll_slow_locked_o;
+ output usr_rx2_pma_loss_of_signal_o;
+ input usr_rx2_pma_m_eye_rst_i;
+ output usr_rx2_pma_pll_lock_o;
+ output usr_rx2_pma_pll_lock_track_o;
+ input usr_rx2_pma_pwr_down_n_i;
+ input usr_rx2_pma_rst_n_i;
+ input usr_rx2_rst_n_i;
+ output [7:0] usr_rx2_test_o;
+ output usr_rx3_busy_o;
+ input usr_rx3_ctrl_align_en_i;
+ input usr_rx3_ctrl_align_sync_i;
+ output [7:0] usr_rx3_ctrl_char_is_a_o;
+ output usr_rx3_ctrl_char_is_aligned_o;
+ output [7:0] usr_rx3_ctrl_char_is_comma_o;
+ output [7:0] usr_rx3_ctrl_char_is_f_o;
+ output [7:0] usr_rx3_ctrl_char_is_k_o;
+ input [2:0] usr_rx3_ctrl_debug_sel_i;
+ input usr_rx3_ctrl_dec_en_i;
+ output [7:0] usr_rx3_ctrl_disp_err_o;
+ input usr_rx3_ctrl_dscr_en_i;
+ input usr_rx3_ctrl_el_buff_rst_i;
+ output [7:0] usr_rx3_ctrl_not_in_table_o;
+ input [1:0] usr_rx3_ctrl_ovs_bit_sel_i;
+ input usr_rx3_ctrl_replace_en_i;
+ output usr_rx3_ctrl_valid_realign_o;
+ output [63:0] usr_rx3_data_o;
+ output usr_rx3_pma_ll_fast_locked_o;
+ output usr_rx3_pma_ll_slow_locked_o;
+ output usr_rx3_pma_loss_of_signal_o;
+ input usr_rx3_pma_m_eye_rst_i;
+ output usr_rx3_pma_pll_lock_o;
+ output usr_rx3_pma_pll_lock_track_o;
+ input usr_rx3_pma_pwr_down_n_i;
+ input usr_rx3_pma_rst_n_i;
+ input usr_rx3_rst_n_i;
+ output [7:0] usr_rx3_test_o;
+ output usr_tx0_busy_o;
+ input [7:0] usr_tx0_ctrl_char_is_k_i;
+ input usr_tx0_ctrl_driver_pwrdwn_n_i;
+ input [7:0] usr_tx0_ctrl_enc_en_i;
+ input [7:0] usr_tx0_ctrl_end_of_frame_i;
+ input [7:0] usr_tx0_ctrl_end_of_multiframe_i;
+ output usr_tx0_ctrl_invalid_k_o;
+ input usr_tx0_ctrl_replace_en_i;
+ input [7:0] usr_tx0_ctrl_scr_en_i;
+ input [63:0] usr_tx0_data_i;
+ input usr_tx0_pma_clk_en_i;
+ output usr_tx0_pma_tx_clk_o;
+ input usr_tx0_rst_n_i;
+ output usr_tx1_busy_o;
+ input [7:0] usr_tx1_ctrl_char_is_k_i;
+ input usr_tx1_ctrl_driver_pwrdwn_n_i;
+ input [7:0] usr_tx1_ctrl_enc_en_i;
+ input [7:0] usr_tx1_ctrl_end_of_frame_i;
+ input [7:0] usr_tx1_ctrl_end_of_multiframe_i;
+ output usr_tx1_ctrl_invalid_k_o;
+ input usr_tx1_ctrl_replace_en_i;
+ input [7:0] usr_tx1_ctrl_scr_en_i;
+ input [63:0] usr_tx1_data_i;
+ input usr_tx1_pma_clk_en_i;
+ output usr_tx1_pma_tx_clk_o;
+ input usr_tx1_rst_n_i;
+ output usr_tx2_busy_o;
+ input [7:0] usr_tx2_ctrl_char_is_k_i;
+ input usr_tx2_ctrl_driver_pwrdwn_n_i;
+ input [7:0] usr_tx2_ctrl_enc_en_i;
+ input [7:0] usr_tx2_ctrl_end_of_frame_i;
+ input [7:0] usr_tx2_ctrl_end_of_multiframe_i;
+ output usr_tx2_ctrl_invalid_k_o;
+ input usr_tx2_ctrl_replace_en_i;
+ input [7:0] usr_tx2_ctrl_scr_en_i;
+ input [63:0] usr_tx2_data_i;
+ input usr_tx2_pma_clk_en_i;
+ output usr_tx2_pma_tx_clk_o;
+ input usr_tx2_rst_n_i;
+ output usr_tx3_busy_o;
+ input [7:0] usr_tx3_ctrl_char_is_k_i;
+ input usr_tx3_ctrl_driver_pwrdwn_n_i;
+ input [7:0] usr_tx3_ctrl_enc_en_i;
+ input [7:0] usr_tx3_ctrl_end_of_frame_i;
+ input [7:0] usr_tx3_ctrl_end_of_multiframe_i;
+ output usr_tx3_ctrl_invalid_k_o;
+ input usr_tx3_ctrl_replace_en_i;
+ input [7:0] usr_tx3_ctrl_scr_en_i;
+ input [63:0] usr_tx3_data_i;
+ input usr_tx3_pma_clk_en_i;
+ output usr_tx3_pma_tx_clk_o;
+ input usr_tx3_rst_n_i;
+ parameter cfg_dyn_all_rx_pma_m_eye_coarse_ena_i = 1'b0;
+ parameter cfg_dyn_all_rx_pma_m_eye_dn_i = 1'b0;
+ parameter cfg_dyn_all_rx_pma_m_eye_fine_ena_i = 1'b0;
+ parameter cfg_dyn_all_rx_pma_m_eye_i = 1'b0;
+ parameter cfg_dyn_all_rx_pma_m_eye_step_i = 4'b0000;
+ parameter cfg_dyn_all_rx_pma_m_eye_up_i = 1'b0;
+ parameter cfg_dyn_all_rx_pma_threshold_1 = 5'b00000;
+ parameter cfg_dyn_all_rx_pma_threshold_2 = 5'b00000;
+ parameter cfg_dyn_all_rx_pma_trim_locked_i = 3'b000;
+ parameter cfg_dyn_all_rx_pma_trim_mode_i = 2'b00;
+ parameter cfg_dyn_all_rx_pma_trim_unlocked_i = 3'b000;
+ parameter cfg_dyn_rx0_pma_ctle_cap_p_i = 4'b0000;
+ parameter cfg_dyn_rx0_pma_ctle_res_p_i = 4'b0000;
+ parameter cfg_dyn_rx0_pma_dfe_idac_tap1_n_i = 6'b000000;
+ parameter cfg_dyn_rx0_pma_dfe_idac_tap2_n_i = 6'b000000;
+ parameter cfg_dyn_rx0_pma_dfe_idac_tap3_n_i = 6'b000000;
+ parameter cfg_dyn_rx0_pma_dfe_idac_tap4_n_i = 6'b000000;
+ parameter cfg_dyn_rx0_pma_termination_cmd_i = 6'b000000;
+ parameter cfg_dyn_rx1_pma_ctle_cap_p_i = 4'b0000;
+ parameter cfg_dyn_rx1_pma_ctle_res_p_i = 4'b0000;
+ parameter cfg_dyn_rx1_pma_dfe_idac_tap1_n_i = 6'b000000;
+ parameter cfg_dyn_rx1_pma_dfe_idac_tap2_n_i = 6'b000000;
+ parameter cfg_dyn_rx1_pma_dfe_idac_tap3_n_i = 6'b000000;
+ parameter cfg_dyn_rx1_pma_dfe_idac_tap4_n_i = 6'b000000;
+ parameter cfg_dyn_rx1_pma_termination_cmd_i = 6'b000000;
+ parameter cfg_dyn_rx2_pma_ctle_cap_p_i = 4'b0000;
+ parameter cfg_dyn_rx2_pma_ctle_res_p_i = 4'b0000;
+ parameter cfg_dyn_rx2_pma_dfe_idac_tap1_n_i = 6'b000000;
+ parameter cfg_dyn_rx2_pma_dfe_idac_tap2_n_i = 6'b000000;
+ parameter cfg_dyn_rx2_pma_dfe_idac_tap3_n_i = 6'b000000;
+ parameter cfg_dyn_rx2_pma_dfe_idac_tap4_n_i = 6'b000000;
+ parameter cfg_dyn_rx2_pma_termination_cmd_i = 6'b000000;
+ parameter cfg_dyn_rx3_pma_ctle_cap_p_i = 4'b0000;
+ parameter cfg_dyn_rx3_pma_ctle_res_p_i = 4'b0000;
+ parameter cfg_dyn_rx3_pma_dfe_idac_tap1_n_i = 6'b000000;
+ parameter cfg_dyn_rx3_pma_dfe_idac_tap2_n_i = 6'b000000;
+ parameter cfg_dyn_rx3_pma_dfe_idac_tap3_n_i = 6'b000000;
+ parameter cfg_dyn_rx3_pma_dfe_idac_tap4_n_i = 6'b000000;
+ parameter cfg_dyn_rx3_pma_termination_cmd_i = 6'b000000;
+ parameter cfg_dyn_tx0_pma_main_en_i = 6'b000000;
+ parameter cfg_dyn_tx0_pma_main_sign_i = 1'b0;
+ parameter cfg_dyn_tx0_pma_margin_input_i = 9'b000000000;
+ parameter cfg_dyn_tx0_pma_margin_sel_i = 9'b000000000;
+ parameter cfg_dyn_tx0_pma_post_en_i = 5'b00000;
+ parameter cfg_dyn_tx0_pma_post_sel_i = 8'b00000000;
+ parameter cfg_dyn_tx0_pma_post_sign_i = 1'b0;
+ parameter cfg_dyn_tx0_pma_pre_en_i = 1'b0;
+ parameter cfg_dyn_tx0_pma_pre_sel_i = 4'b0000;
+ parameter cfg_dyn_tx0_pma_pre_sign_i = 1'b0;
+ parameter cfg_dyn_tx1_pma_main_en_i = 6'b000000;
+ parameter cfg_dyn_tx1_pma_main_sign_i = 1'b0;
+ parameter cfg_dyn_tx1_pma_margin_input_i = 9'b000000000;
+ parameter cfg_dyn_tx1_pma_margin_sel_i = 9'b000000000;
+ parameter cfg_dyn_tx1_pma_post_en_i = 5'b00000;
+ parameter cfg_dyn_tx1_pma_post_sel_i = 8'b00000000;
+ parameter cfg_dyn_tx1_pma_post_sign_i = 1'b0;
+ parameter cfg_dyn_tx1_pma_pre_en_i = 1'b0;
+ parameter cfg_dyn_tx1_pma_pre_sel_i = 4'b0000;
+ parameter cfg_dyn_tx1_pma_pre_sign_i = 1'b0;
+ parameter cfg_dyn_tx2_pma_main_en_i = 6'b000000;
+ parameter cfg_dyn_tx2_pma_main_sign_i = 1'b0;
+ parameter cfg_dyn_tx2_pma_margin_input_i = 9'b000000000;
+ parameter cfg_dyn_tx2_pma_margin_sel_i = 9'b000000000;
+ parameter cfg_dyn_tx2_pma_post_en_i = 5'b00000;
+ parameter cfg_dyn_tx2_pma_post_sel_i = 8'b00000000;
+ parameter cfg_dyn_tx2_pma_post_sign_i = 1'b0;
+ parameter cfg_dyn_tx2_pma_pre_en_i = 1'b0;
+ parameter cfg_dyn_tx2_pma_pre_sel_i = 4'b0000;
+ parameter cfg_dyn_tx2_pma_pre_sign_i = 1'b0;
+ parameter cfg_dyn_tx3_pma_main_en_i = 6'b000000;
+ parameter cfg_dyn_tx3_pma_main_sign_i = 1'b0;
+ parameter cfg_dyn_tx3_pma_margin_input_i = 9'b000000000;
+ parameter cfg_dyn_tx3_pma_margin_sel_i = 9'b000000000;
+ parameter cfg_dyn_tx3_pma_post_en_i = 5'b00000;
+ parameter cfg_dyn_tx3_pma_post_sel_i = 8'b00000000;
+ parameter cfg_dyn_tx3_pma_post_sign_i = 1'b0;
+ parameter cfg_dyn_tx3_pma_pre_en_i = 1'b0;
+ parameter cfg_dyn_tx3_pma_pre_sel_i = 4'b0000;
+ parameter cfg_dyn_tx3_pma_pre_sign_i = 1'b0;
+ parameter cfg_main_clk_to_fabric_div_en_i = 1'b0;
+ parameter cfg_main_clk_to_fabric_div_mode_i = 1'b0;
+ parameter cfg_main_clk_to_fabric_sel_i = 1'b0;
+ parameter cfg_main_rclk_to_fabric_sel_i = 2'b00;
+ parameter cfg_main_use_only_usr_clock_i = 1'b0;
+ parameter cfg_pcs_ovs_en_i = 1'b0;
+ parameter cfg_pcs_ovs_mode_i = 1'b0;
+ parameter cfg_pcs_pll_lock_ppm_i = 3'b000;
+ parameter cfg_pcs_word_len_i = 2'b00;
+ parameter cfg_pll_pma_ckref_ext_i = 1'b0;
+ parameter cfg_pll_pma_cpump_i = 4'b0000;
+ parameter cfg_pll_pma_divl_i = 2'b00;
+ parameter cfg_pll_pma_divm_i = 1'b0;
+ parameter cfg_pll_pma_divn_i = 2'b00;
+ parameter cfg_pll_pma_gbx_en_i = 1'b0;
+ parameter cfg_pll_pma_int_data_len_i = 1'b0;
+ parameter cfg_pll_pma_lvds_en_i = 1'b0;
+ parameter cfg_pll_pma_lvds_mux_i = 1'b0;
+ parameter cfg_pll_pma_mux_ckref_i = 1'b0;
+ parameter cfg_rx0_gearbox_en_i = 1'b0;
+ parameter cfg_rx0_gearbox_mode_i = 1'b0;
+ parameter cfg_rx0_pcs_8b_dscr_sel_i = 1'b0;
+ parameter cfg_rx0_pcs_align_bypass_i = 1'b0;
+ parameter cfg_rx0_pcs_buffers_bypass_i = 1'b0;
+ parameter cfg_rx0_pcs_buffers_use_cdc_i = 1'b0;
+ parameter cfg_rx0_pcs_bypass_pma_cdc_i = 1'b0;
+ parameter cfg_rx0_pcs_bypass_usr_cdc_i = 1'b0;
+ parameter cfg_rx0_pcs_comma_mask_i = 10'b0000000000;
+ parameter cfg_rx0_pcs_debug_en_i = 1'b0;
+ parameter cfg_rx0_pcs_dec_bypass_i = 1'b0;
+ parameter cfg_rx0_pcs_dscr_bypass_i = 1'b0;
+ parameter cfg_rx0_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+ parameter cfg_rx0_pcs_el_buff_max_comp_i = 4'b0000;
+ parameter cfg_rx0_pcs_el_buff_only_one_skp_i = 1'b0;
+ parameter cfg_rx0_pcs_el_buff_skp_char_0_i = 9'b000000000;
+ parameter cfg_rx0_pcs_el_buff_skp_char_1_i = 9'b000000000;
+ parameter cfg_rx0_pcs_el_buff_skp_char_2_i = 9'b000000000;
+ parameter cfg_rx0_pcs_el_buff_skp_char_3_i = 9'b000000000;
+ parameter cfg_rx0_pcs_el_buff_skp_header_0_i = 9'b000000000;
+ parameter cfg_rx0_pcs_el_buff_skp_header_1_i = 9'b000000000;
+ parameter cfg_rx0_pcs_el_buff_skp_header_2_i = 9'b000000000;
+ parameter cfg_rx0_pcs_el_buff_skp_header_3_i = 9'b000000000;
+ parameter cfg_rx0_pcs_el_buff_skp_header_size_i = 2'b00;
+ parameter cfg_rx0_pcs_el_buff_skp_seq_size_i = 2'b00;
+ parameter cfg_rx0_pcs_fsm_sel_i = 2'b00;
+ parameter cfg_rx0_pcs_fsm_watchdog_en_i = 1'b0;
+ parameter cfg_rx0_pcs_loopback_i = 1'b0;
+ parameter cfg_rx0_pcs_m_comma_en_i = 1'b0;
+ parameter cfg_rx0_pcs_m_comma_val_i = 10'b0000000000;
+ parameter cfg_rx0_pcs_nb_comma_bef_realign_i = 2'b00;
+ parameter cfg_rx0_pcs_p_comma_en_i = 1'b0;
+ parameter cfg_rx0_pcs_p_comma_val_i = 10'b0000000000;
+ parameter cfg_rx0_pcs_polarity_i = 1'b0;
+ parameter cfg_rx0_pcs_protocol_size_i = 1'b0;
+ parameter cfg_rx0_pcs_replace_bypass_i = 1'b0;
+ parameter cfg_rx0_pcs_sync_supported_i = 1'b0;
+ parameter cfg_rx0_pma_cdr_cp_i = 4'b0000;
+ parameter cfg_rx0_pma_clk_pos_i = 1'b0;
+ parameter cfg_rx0_pma_coarse_ppm_i = 3'b000;
+ parameter cfg_rx0_pma_ctrl_term_i = 6'b000000;
+ parameter cfg_rx0_pma_dco_divl_i = 2'b00;
+ parameter cfg_rx0_pma_dco_divm_i = 1'b0;
+ parameter cfg_rx0_pma_dco_divn_i = 2'b00;
+ parameter cfg_rx0_pma_dco_reg_res_i = 2'b00;
+ parameter cfg_rx0_pma_dco_vref_sel_i = 1'b0;
+ parameter cfg_rx0_pma_fine_ppm_i = 3'b000;
+ parameter cfg_rx0_pma_loopback_i = 1'b0;
+ parameter cfg_rx0_pma_m_eye_ppm_i = 3'b000;
+ parameter cfg_rx0_pma_peak_detect_cmd_i = 2'b00;
+ parameter cfg_rx0_pma_peak_detect_on_i = 1'b0;
+ parameter cfg_rx0_pma_pll_cpump_n_i = 3'b000;
+ parameter cfg_rx0_pma_pll_divf_en_n_i = 1'b0;
+ parameter cfg_rx0_pma_pll_divf_i = 2'b00;
+ parameter cfg_rx0_pma_pll_divm_en_n_i = 1'b0;
+ parameter cfg_rx0_pma_pll_divm_i = 2'b00;
+ parameter cfg_rx0_pma_pll_divn_en_n_i = 1'b0;
+ parameter cfg_rx0_pma_pll_divn_i = 1'b0;
+ parameter cfg_rx1_gearbox_en_i = 1'b0;
+ parameter cfg_rx1_gearbox_mode_i = 1'b0;
+ parameter cfg_rx1_pcs_8b_dscr_sel_i = 1'b0;
+ parameter cfg_rx1_pcs_align_bypass_i = 1'b0;
+ parameter cfg_rx1_pcs_buffers_bypass_i = 1'b0;
+ parameter cfg_rx1_pcs_buffers_use_cdc_i = 1'b0;
+ parameter cfg_rx1_pcs_bypass_pma_cdc_i = 1'b0;
+ parameter cfg_rx1_pcs_bypass_usr_cdc_i = 1'b0;
+ parameter cfg_rx1_pcs_comma_mask_i = 10'b0000000000;
+ parameter cfg_rx1_pcs_debug_en_i = 1'b0;
+ parameter cfg_rx1_pcs_dec_bypass_i = 1'b0;
+ parameter cfg_rx1_pcs_dscr_bypass_i = 1'b0;
+ parameter cfg_rx1_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+ parameter cfg_rx1_pcs_el_buff_max_comp_i = 4'b0000;
+ parameter cfg_rx1_pcs_el_buff_only_one_skp_i = 1'b0;
+ parameter cfg_rx1_pcs_el_buff_skp_char_0_i = 9'b000000000;
+ parameter cfg_rx1_pcs_el_buff_skp_char_1_i = 9'b000000000;
+ parameter cfg_rx1_pcs_el_buff_skp_char_2_i = 9'b000000000;
+ parameter cfg_rx1_pcs_el_buff_skp_char_3_i = 9'b000000000;
+ parameter cfg_rx1_pcs_el_buff_skp_header_0_i = 9'b000000000;
+ parameter cfg_rx1_pcs_el_buff_skp_header_1_i = 9'b000000000;
+ parameter cfg_rx1_pcs_el_buff_skp_header_2_i = 9'b000000000;
+ parameter cfg_rx1_pcs_el_buff_skp_header_3_i = 9'b000000000;
+ parameter cfg_rx1_pcs_el_buff_skp_header_size_i = 2'b00;
+ parameter cfg_rx1_pcs_el_buff_skp_seq_size_i = 2'b00;
+ parameter cfg_rx1_pcs_fsm_sel_i = 2'b00;
+ parameter cfg_rx1_pcs_fsm_watchdog_en_i = 1'b0;
+ parameter cfg_rx1_pcs_loopback_i = 1'b0;
+ parameter cfg_rx1_pcs_m_comma_en_i = 1'b0;
+ parameter cfg_rx1_pcs_m_comma_val_i = 10'b0000000000;
+ parameter cfg_rx1_pcs_nb_comma_bef_realign_i = 2'b00;
+ parameter cfg_rx1_pcs_p_comma_en_i = 1'b0;
+ parameter cfg_rx1_pcs_p_comma_val_i = 10'b0000000000;
+ parameter cfg_rx1_pcs_polarity_i = 1'b0;
+ parameter cfg_rx1_pcs_protocol_size_i = 1'b0;
+ parameter cfg_rx1_pcs_replace_bypass_i = 1'b0;
+ parameter cfg_rx1_pcs_sync_supported_i = 1'b0;
+ parameter cfg_rx1_pma_cdr_cp_i = 4'b0000;
+ parameter cfg_rx1_pma_clk_pos_i = 1'b0;
+ parameter cfg_rx1_pma_coarse_ppm_i = 3'b000;
+ parameter cfg_rx1_pma_ctrl_term_i = 6'b000000;
+ parameter cfg_rx1_pma_dco_divl_i = 2'b00;
+ parameter cfg_rx1_pma_dco_divm_i = 1'b0;
+ parameter cfg_rx1_pma_dco_divn_i = 2'b00;
+ parameter cfg_rx1_pma_dco_reg_res_i = 2'b00;
+ parameter cfg_rx1_pma_dco_vref_sel_i = 1'b0;
+ parameter cfg_rx1_pma_fine_ppm_i = 3'b000;
+ parameter cfg_rx1_pma_loopback_i = 1'b0;
+ parameter cfg_rx1_pma_m_eye_ppm_i = 3'b000;
+ parameter cfg_rx1_pma_peak_detect_cmd_i = 2'b00;
+ parameter cfg_rx1_pma_peak_detect_on_i = 1'b0;
+ parameter cfg_rx1_pma_pll_cpump_n_i = 3'b000;
+ parameter cfg_rx1_pma_pll_divf_en_n_i = 1'b0;
+ parameter cfg_rx1_pma_pll_divf_i = 2'b00;
+ parameter cfg_rx1_pma_pll_divm_en_n_i = 1'b0;
+ parameter cfg_rx1_pma_pll_divm_i = 2'b00;
+ parameter cfg_rx1_pma_pll_divn_en_n_i = 1'b0;
+ parameter cfg_rx1_pma_pll_divn_i = 1'b0;
+ parameter cfg_rx2_gearbox_en_i = 1'b0;
+ parameter cfg_rx2_gearbox_mode_i = 1'b0;
+ parameter cfg_rx2_pcs_8b_dscr_sel_i = 1'b0;
+ parameter cfg_rx2_pcs_align_bypass_i = 1'b0;
+ parameter cfg_rx2_pcs_buffers_bypass_i = 1'b0;
+ parameter cfg_rx2_pcs_buffers_use_cdc_i = 1'b0;
+ parameter cfg_rx2_pcs_bypass_pma_cdc_i = 1'b0;
+ parameter cfg_rx2_pcs_bypass_usr_cdc_i = 1'b0;
+ parameter cfg_rx2_pcs_comma_mask_i = 10'b0000000000;
+ parameter cfg_rx2_pcs_debug_en_i = 1'b0;
+ parameter cfg_rx2_pcs_dec_bypass_i = 1'b0;
+ parameter cfg_rx2_pcs_dscr_bypass_i = 1'b0;
+ parameter cfg_rx2_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+ parameter cfg_rx2_pcs_el_buff_max_comp_i = 4'b0000;
+ parameter cfg_rx2_pcs_el_buff_only_one_skp_i = 1'b0;
+ parameter cfg_rx2_pcs_el_buff_skp_char_0_i = 9'b000000000;
+ parameter cfg_rx2_pcs_el_buff_skp_char_1_i = 9'b000000000;
+ parameter cfg_rx2_pcs_el_buff_skp_char_2_i = 9'b000000000;
+ parameter cfg_rx2_pcs_el_buff_skp_char_3_i = 9'b000000000;
+ parameter cfg_rx2_pcs_el_buff_skp_header_0_i = 9'b000000000;
+ parameter cfg_rx2_pcs_el_buff_skp_header_1_i = 9'b000000000;
+ parameter cfg_rx2_pcs_el_buff_skp_header_2_i = 9'b000000000;
+ parameter cfg_rx2_pcs_el_buff_skp_header_3_i = 9'b000000000;
+ parameter cfg_rx2_pcs_el_buff_skp_header_size_i = 2'b00;
+ parameter cfg_rx2_pcs_el_buff_skp_seq_size_i = 2'b00;
+ parameter cfg_rx2_pcs_fsm_sel_i = 2'b00;
+ parameter cfg_rx2_pcs_fsm_watchdog_en_i = 1'b0;
+ parameter cfg_rx2_pcs_loopback_i = 1'b0;
+ parameter cfg_rx2_pcs_m_comma_en_i = 1'b0;
+ parameter cfg_rx2_pcs_m_comma_val_i = 10'b0000000000;
+ parameter cfg_rx2_pcs_nb_comma_bef_realign_i = 2'b00;
+ parameter cfg_rx2_pcs_p_comma_en_i = 1'b0;
+ parameter cfg_rx2_pcs_p_comma_val_i = 10'b0000000000;
+ parameter cfg_rx2_pcs_polarity_i = 1'b0;
+ parameter cfg_rx2_pcs_protocol_size_i = 1'b0;
+ parameter cfg_rx2_pcs_replace_bypass_i = 1'b0;
+ parameter cfg_rx2_pcs_sync_supported_i = 1'b0;
+ parameter cfg_rx2_pma_cdr_cp_i = 4'b0000;
+ parameter cfg_rx2_pma_clk_pos_i = 1'b0;
+ parameter cfg_rx2_pma_coarse_ppm_i = 3'b000;
+ parameter cfg_rx2_pma_ctrl_term_i = 6'b000000;
+ parameter cfg_rx2_pma_dco_divl_i = 2'b00;
+ parameter cfg_rx2_pma_dco_divm_i = 1'b0;
+ parameter cfg_rx2_pma_dco_divn_i = 2'b00;
+ parameter cfg_rx2_pma_dco_reg_res_i = 2'b00;
+ parameter cfg_rx2_pma_dco_vref_sel_i = 1'b0;
+ parameter cfg_rx2_pma_fine_ppm_i = 3'b000;
+ parameter cfg_rx2_pma_loopback_i = 1'b0;
+ parameter cfg_rx2_pma_m_eye_ppm_i = 3'b000;
+ parameter cfg_rx2_pma_peak_detect_cmd_i = 2'b00;
+ parameter cfg_rx2_pma_peak_detect_on_i = 1'b0;
+ parameter cfg_rx2_pma_pll_cpump_n_i = 3'b000;
+ parameter cfg_rx2_pma_pll_divf_en_n_i = 1'b0;
+ parameter cfg_rx2_pma_pll_divf_i = 2'b00;
+ parameter cfg_rx2_pma_pll_divm_en_n_i = 1'b0;
+ parameter cfg_rx2_pma_pll_divm_i = 2'b00;
+ parameter cfg_rx2_pma_pll_divn_en_n_i = 1'b0;
+ parameter cfg_rx2_pma_pll_divn_i = 1'b0;
+ parameter cfg_rx3_gearbox_en_i = 1'b0;
+ parameter cfg_rx3_gearbox_mode_i = 1'b0;
+ parameter cfg_rx3_pcs_8b_dscr_sel_i = 1'b0;
+ parameter cfg_rx3_pcs_align_bypass_i = 1'b0;
+ parameter cfg_rx3_pcs_buffers_bypass_i = 1'b0;
+ parameter cfg_rx3_pcs_buffers_use_cdc_i = 1'b0;
+ parameter cfg_rx3_pcs_bypass_pma_cdc_i = 1'b0;
+ parameter cfg_rx3_pcs_bypass_usr_cdc_i = 1'b0;
+ parameter cfg_rx3_pcs_comma_mask_i = 10'b0000000000;
+ parameter cfg_rx3_pcs_debug_en_i = 1'b0;
+ parameter cfg_rx3_pcs_dec_bypass_i = 1'b0;
+ parameter cfg_rx3_pcs_dscr_bypass_i = 1'b0;
+ parameter cfg_rx3_pcs_el_buff_diff_bef_comp_i = 4'b0000;
+ parameter cfg_rx3_pcs_el_buff_max_comp_i = 4'b0000;
+ parameter cfg_rx3_pcs_el_buff_only_one_skp_i = 1'b0;
+ parameter cfg_rx3_pcs_el_buff_skp_char_0_i = 9'b000000000;
+ parameter cfg_rx3_pcs_el_buff_skp_char_1_i = 9'b000000000;
+ parameter cfg_rx3_pcs_el_buff_skp_char_2_i = 9'b000000000;
+ parameter cfg_rx3_pcs_el_buff_skp_char_3_i = 9'b000000000;
+ parameter cfg_rx3_pcs_el_buff_skp_header_0_i = 9'b000000000;
+ parameter cfg_rx3_pcs_el_buff_skp_header_1_i = 9'b000000000;
+ parameter cfg_rx3_pcs_el_buff_skp_header_2_i = 9'b000000000;
+ parameter cfg_rx3_pcs_el_buff_skp_header_3_i = 9'b000000000;
+ parameter cfg_rx3_pcs_el_buff_skp_header_size_i = 2'b00;
+ parameter cfg_rx3_pcs_el_buff_skp_seq_size_i = 2'b00;
+ parameter cfg_rx3_pcs_fsm_sel_i = 2'b00;
+ parameter cfg_rx3_pcs_fsm_watchdog_en_i = 1'b0;
+ parameter cfg_rx3_pcs_loopback_i = 1'b0;
+ parameter cfg_rx3_pcs_m_comma_en_i = 1'b0;
+ parameter cfg_rx3_pcs_m_comma_val_i = 10'b0000000000;
+ parameter cfg_rx3_pcs_nb_comma_bef_realign_i = 2'b00;
+ parameter cfg_rx3_pcs_p_comma_en_i = 1'b0;
+ parameter cfg_rx3_pcs_p_comma_val_i = 10'b0000000000;
+ parameter cfg_rx3_pcs_polarity_i = 1'b0;
+ parameter cfg_rx3_pcs_protocol_size_i = 1'b0;
+ parameter cfg_rx3_pcs_replace_bypass_i = 1'b0;
+ parameter cfg_rx3_pcs_sync_supported_i = 1'b0;
+ parameter cfg_rx3_pma_cdr_cp_i = 4'b0000;
+ parameter cfg_rx3_pma_clk_pos_i = 1'b0;
+ parameter cfg_rx3_pma_coarse_ppm_i = 3'b000;
+ parameter cfg_rx3_pma_ctrl_term_i = 6'b000000;
+ parameter cfg_rx3_pma_dco_divl_i = 2'b00;
+ parameter cfg_rx3_pma_dco_divm_i = 1'b0;
+ parameter cfg_rx3_pma_dco_divn_i = 2'b00;
+ parameter cfg_rx3_pma_dco_reg_res_i = 2'b00;
+ parameter cfg_rx3_pma_dco_vref_sel_i = 1'b0;
+ parameter cfg_rx3_pma_fine_ppm_i = 3'b000;
+ parameter cfg_rx3_pma_loopback_i = 1'b0;
+ parameter cfg_rx3_pma_m_eye_ppm_i = 3'b000;
+ parameter cfg_rx3_pma_peak_detect_cmd_i = 2'b00;
+ parameter cfg_rx3_pma_peak_detect_on_i = 1'b0;
+ parameter cfg_rx3_pma_pll_cpump_n_i = 3'b000;
+ parameter cfg_rx3_pma_pll_divf_en_n_i = 1'b0;
+ parameter cfg_rx3_pma_pll_divf_i = 2'b00;
+ parameter cfg_rx3_pma_pll_divm_en_n_i = 1'b0;
+ parameter cfg_rx3_pma_pll_divm_i = 2'b00;
+ parameter cfg_rx3_pma_pll_divn_en_n_i = 1'b0;
+ parameter cfg_rx3_pma_pll_divn_i = 1'b0;
+ parameter cfg_test_mode_i = 2'b00;
+ parameter cfg_tx0_gearbox_en_i = 1'b0;
+ parameter cfg_tx0_gearbox_mode_i = 1'b0;
+ parameter cfg_tx0_pcs_8b_scr_sel_i = 1'b0;
+ parameter cfg_tx0_pcs_bypass_pma_cdc_i = 1'b0;
+ parameter cfg_tx0_pcs_bypass_usr_cdc_i = 1'b0;
+ parameter cfg_tx0_pcs_enc_bypass_i = 1'b0;
+ parameter cfg_tx0_pcs_esistream_fsm_en_i = 1'b0;
+ parameter cfg_tx0_pcs_loopback_i = 1'b0;
+ parameter cfg_tx0_pcs_polarity_i = 1'b0;
+ parameter cfg_tx0_pcs_protocol_size_i = 1'b0;
+ parameter cfg_tx0_pcs_replace_bypass_i = 1'b0;
+ parameter cfg_tx0_pcs_scr_bypass_i = 1'b0;
+ parameter cfg_tx0_pcs_scr_init_i = 17'b00000000000000000;
+ parameter cfg_tx0_pcs_sync_supported_i = 1'b0;
+ parameter cfg_tx0_pma_clk_pos_i = 1'b0;
+ parameter cfg_tx0_pma_loopback_i = 1'b0;
+ parameter cfg_tx1_gearbox_en_i = 1'b0;
+ parameter cfg_tx1_gearbox_mode_i = 1'b0;
+ parameter cfg_tx1_pcs_8b_scr_sel_i = 1'b0;
+ parameter cfg_tx1_pcs_bypass_pma_cdc_i = 1'b0;
+ parameter cfg_tx1_pcs_bypass_usr_cdc_i = 1'b0;
+ parameter cfg_tx1_pcs_enc_bypass_i = 1'b0;
+ parameter cfg_tx1_pcs_esistream_fsm_en_i = 1'b0;
+ parameter cfg_tx1_pcs_loopback_i = 1'b0;
+ parameter cfg_tx1_pcs_polarity_i = 1'b0;
+ parameter cfg_tx1_pcs_protocol_size_i = 1'b0;
+ parameter cfg_tx1_pcs_replace_bypass_i = 1'b0;
+ parameter cfg_tx1_pcs_scr_bypass_i = 1'b0;
+ parameter cfg_tx1_pcs_scr_init_i = 17'b00000000000000000;
+ parameter cfg_tx1_pcs_sync_supported_i = 1'b0;
+ parameter cfg_tx1_pma_clk_pos_i = 1'b0;
+ parameter cfg_tx1_pma_loopback_i = 1'b0;
+ parameter cfg_tx2_gearbox_en_i = 1'b0;
+ parameter cfg_tx2_gearbox_mode_i = 1'b0;
+ parameter cfg_tx2_pcs_8b_scr_sel_i = 1'b0;
+ parameter cfg_tx2_pcs_bypass_pma_cdc_i = 1'b0;
+ parameter cfg_tx2_pcs_bypass_usr_cdc_i = 1'b0;
+ parameter cfg_tx2_pcs_enc_bypass_i = 1'b0;
+ parameter cfg_tx2_pcs_esistream_fsm_en_i = 1'b0;
+ parameter cfg_tx2_pcs_loopback_i = 1'b0;
+ parameter cfg_tx2_pcs_polarity_i = 1'b0;
+ parameter cfg_tx2_pcs_protocol_size_i = 1'b0;
+ parameter cfg_tx2_pcs_replace_bypass_i = 1'b0;
+ parameter cfg_tx2_pcs_scr_bypass_i = 1'b0;
+ parameter cfg_tx2_pcs_scr_init_i = 17'b00000000000000000;
+ parameter cfg_tx2_pcs_sync_supported_i = 1'b0;
+ parameter cfg_tx2_pma_clk_pos_i = 1'b0;
+ parameter cfg_tx2_pma_loopback_i = 1'b0;
+ parameter cfg_tx3_gearbox_en_i = 1'b0;
+ parameter cfg_tx3_gearbox_mode_i = 1'b0;
+ parameter cfg_tx3_pcs_8b_scr_sel_i = 1'b0;
+ parameter cfg_tx3_pcs_bypass_pma_cdc_i = 1'b0;
+ parameter cfg_tx3_pcs_bypass_usr_cdc_i = 1'b0;
+ parameter cfg_tx3_pcs_enc_bypass_i = 1'b0;
+ parameter cfg_tx3_pcs_esistream_fsm_en_i = 1'b0;
+ parameter cfg_tx3_pcs_loopback_i = 1'b0;
+ parameter cfg_tx3_pcs_polarity_i = 1'b0;
+ parameter cfg_tx3_pcs_protocol_size_i = 1'b0;
+ parameter cfg_tx3_pcs_replace_bypass_i = 1'b0;
+ parameter cfg_tx3_pcs_scr_bypass_i = 1'b0;
+ parameter cfg_tx3_pcs_scr_init_i = 17'b00000000000000000;
+ parameter cfg_tx3_pcs_sync_supported_i = 1'b0;
+ parameter cfg_tx3_pma_clk_pos_i = 1'b0;
+ parameter cfg_tx3_pma_loopback_i = 1'b0;
+ parameter location = "";
+ parameter rx_usrclk_use_pcs_clk_2 = 1'b0;
+ parameter tx_usrclk_use_pcs_clk_2 = 1'b0;
+endmodule
diff --git a/techlibs/nanoxplore/io_map.v b/techlibs/nanoxplore/io_map.v
new file mode 100644
index 000000000..edbb0437b
--- /dev/null
+++ b/techlibs/nanoxplore/io_map.v
@@ -0,0 +1,15 @@
+module \$__BEYOND_IBUF (input PAD, output O);
+ NX_IOB_I _TECHMAP_REPLACE_ (.IO(PAD), .O(O), .C(1'b0));
+endmodule
+
+module \$__BEYOND_OBUF (output PAD, input I);
+ NX_IOB_O _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(1'b1));
+endmodule
+
+module \$__BEYOND_TOBUF (output PAD, input I, input C);
+ NX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .C(C));
+endmodule
+
+module \$__BEYOND_IOBUF (output PAD, input I, output O, output C);
+ NX_IOB _TECHMAP_REPLACE_ (.IO(PAD), .I(I), .O(O), .C(C));
+endmodule
diff --git a/techlibs/nanoxplore/latches_map.v b/techlibs/nanoxplore/latches_map.v
new file mode 100644
index 000000000..c28f88cf7
--- /dev/null
+++ b/techlibs/nanoxplore/latches_map.v
@@ -0,0 +1,11 @@
+module \$_DLATCH_N_ (E, D, Q);
+ wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+ input E, D;
+ output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+ wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+ input E, D;
+ output Q = E ? D : Q;
+endmodule
diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
new file mode 100644
index 000000000..6e6a96035
--- /dev/null
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -0,0 +1,164 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2024 Miodrag Milanovic
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+ if (GetSize(sig) == 0)
+ return State::S0;
+ return sig[0];
+}
+
+static void nx_carry_chain(Module *module)
+{
+ SigMap sigmap(module);
+
+ dict carry;
+ for (auto cell : module->cells())
+ {
+ if (cell->type == ID(NX_CY_1BIT)) {
+ if (cell->getParam(ID(first)).as_int() == 1) continue;
+ if (!cell->hasPort(ID(CI)))
+ log_error("Not able to find connected carry.\n");
+ SigBit ci = sigmap(cell->getPort(ID(CI)).as_bit());
+ carry[ci] = cell;
+ }
+ }
+
+ dict> carry_chains;
+ log("Detecting carry chains\n");
+ for (auto cell : module->cells())
+ {
+ if (cell->type == ID(NX_CY_1BIT)) {
+ if (cell->getParam(ID(first)).as_int() == 0) continue;
+
+ vector chain;
+ Cell *current = cell;
+ chain.push_back(current);
+
+ SigBit co = sigmap(cell->getPort(ID(CO)).as_bit());
+ while (co.is_wire())
+ {
+ if (carry.count(co)==0)
+ break;
+ //log_error("Not able to find connected carry.\n");
+ current = carry[co];
+ chain.push_back(current);
+ if (!current->hasPort(ID(CO))) break;
+ co = sigmap(current->getPort(ID(CO)).as_bit());
+ }
+ carry_chains[cell] = chain;
+ }
+ }
+
+ log("Creating NX_CY cells.\n");
+ for(auto& c : carry_chains) {
+ Cell *cell = nullptr;
+ int j = 0;
+ int cnt = 0;
+ IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
+ IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
+ IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
+ if (!c.second.at(0)->getPort(ID(CI)).is_fully_const()) {
+ cell = module->addCell(NEW_ID, ID(NX_CY));
+ cell->setParam(ID(add_carry), Const(1,2));
+ cell->setPort(ID(CI), State::S1);
+
+ cell->setPort(names_A[0], c.second.at(0)->getPort(ID(CI)).as_bit());
+ cell->setPort(names_B[0], State::S0);
+ j++;
+ }
+
+ for (size_t i=0 ; iaddCell(NEW_ID, ID(NX_CY));
+ SigBit ci = c.second.at(i)->getPort(ID(CI)).as_bit();
+ cell->setPort(ID(CI), ci);
+ if (ci.is_wire()) {
+ cell->setParam(ID(add_carry), Const(2,2));
+ } else {
+ if (ci == State::S0)
+ cell->setParam(ID(add_carry), Const(0,2));
+ else
+ cell->setParam(ID(add_carry), Const(1,2));
+ }
+ }
+ if (j==3) {
+ if (cnt !=0 && (cnt % 24 == 0)) {
+ SigBit new_co = module->addWire(NEW_ID);
+ cell->setPort(ID(A4), State::S0);
+ cell->setPort(ID(B4), State::S0);
+ cell->setPort(ID(S4), new_co);
+ cell = module->addCell(NEW_ID, ID(NX_CY));
+ cell->setParam(ID(add_carry), Const(1,2));
+ cell->setPort(ID(CI), State::S1);
+ cell->setPort(ID(A1), new_co);
+ cell->setPort(ID(B1), State::S0);
+ j = 1;
+ } else {
+ if (c.second.at(i)->hasPort(ID(CO)))
+ cell->setPort(ID(CO), c.second.at(i)->getPort(ID(CO)));
+ }
+ cnt++;
+ }
+ cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(ID(A))));
+ cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(ID(B))));
+
+ if (c.second.at(i)->hasPort(ID(S)))
+ cell->setPort(names_S[j], c.second.at(i)->getPort(ID(S)));
+
+ j = (j + 1) % 4;
+ module->remove(c.second.at(i));
+ }
+ }
+}
+
+struct NXCarryPass : public Pass {
+ NXCarryPass() : Pass("nx_carry", "NanoXplore: create carry cells") { }
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" nx_carry [options] [selection]\n");
+ log("\n");
+ log("Fixes carry chain if needed, break it on 24 elements and group by 4 into NX_CY.\n");
+ log("\n");
+ }
+ void execute(std::vector args, RTLIL::Design *design) override
+ {
+ log_header(design, "Executing NX_CARRY pass.\n");
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ for (auto module : design->selected_modules())
+ nx_carry_chain(module);
+ }
+} NXCarryPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/nanoxplore/rf_init.vh b/techlibs/nanoxplore/rf_init.vh
new file mode 100644
index 000000000..909a1c0cd
--- /dev/null
+++ b/techlibs/nanoxplore/rf_init.vh
@@ -0,0 +1,17 @@
+function [9728-1:0] rf_init_to_string;
+ input [1152-1:0] array;
+ input integer blocks;
+ input integer width;
+ reg [9728-1:0] temp; // (1152+1152/18)*8
+ integer i;
+begin
+ temp = "";
+ for (i = 0; i < blocks; i = i + 1) begin
+ if (i != 0) begin
+ temp = {temp, ","};
+ end
+ temp = {temp, $sformatf("%b",array[(i+1)*width-1: i*width])};
+ end
+ rf_init_to_string = temp;
+end
+endfunction
diff --git a/techlibs/nanoxplore/rf_rams_l.txt b/techlibs/nanoxplore/rf_rams_l.txt
new file mode 100644
index 000000000..112655184
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_l.txt
@@ -0,0 +1,15 @@
+ram distributed $__NX_RFB_L_ {
+ abits 6;
+ width 16;
+ cost 10;
+ init no_undef;
+ prune_rom;
+
+ port sw "W" {
+ clock anyedge;
+ }
+ port sr "R" {
+ clock anyedge;
+ rden;
+ }
+}
diff --git a/techlibs/nanoxplore/rf_rams_m.txt b/techlibs/nanoxplore/rf_rams_m.txt
new file mode 100644
index 000000000..d872405a3
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_m.txt
@@ -0,0 +1,15 @@
+ram distributed $__NX_RFB_M_ {
+ abits 6;
+ width 16;
+ cost 10;
+ init no_undef;
+ prune_rom;
+
+ port sw "W" {
+ clock anyedge;
+ }
+ port sr "R" {
+ clock anyedge;
+ rden;
+ }
+}
diff --git a/techlibs/nanoxplore/rf_rams_map_l.v b/techlibs/nanoxplore/rf_rams_map_l.v
new file mode 100644
index 000000000..e529ce1e1
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_map_l.v
@@ -0,0 +1,30 @@
+module $__NX_RFB_L_ (
+ input PORT_W_CLK,
+ input PORT_W_WR_EN,
+ input [5:0] PORT_W_ADDR,
+ input [15:0] PORT_W_WR_DATA,
+ input PORT_R_CLK,
+ input PORT_R_RD_EN,
+ input [5:0] PORT_R_ADDR,
+ output [15:0] PORT_R_RD_DATA,
+);
+ parameter INIT = 1152'bx;
+ parameter PORT_W_CLK_POL = 1'b1;
+ parameter PORT_R_CLK_POL = 1'b1;
+
+ NX_RFB_L_WRAP #(
+ .mode(0),
+ .mem_ctxt(INIT),
+ .rck_edge(~PORT_R_CLK_POL),
+ .wck_edge(~PORT_W_CLK_POL)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(PORT_R_CLK),
+ .WCK(PORT_W_CLK),
+ .I(PORT_W_WR_DATA),
+ .RA(PORT_R_ADDR),
+ .WA(PORT_W_ADDR),
+ .RE(PORT_R_RD_EN),
+ .WE(PORT_W_WR_EN),
+ .O(PORT_R_RD_DATA)
+ );
+endmodule
diff --git a/techlibs/nanoxplore/rf_rams_map_m.v b/techlibs/nanoxplore/rf_rams_map_m.v
new file mode 100644
index 000000000..a64dc3388
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_map_m.v
@@ -0,0 +1,30 @@
+module $__NX_RFB_M_ (
+ input PORT_W_CLK,
+ input PORT_W_WR_EN,
+ input [5:0] PORT_W_ADDR,
+ input [15:0] PORT_W_WR_DATA,
+ input PORT_R_CLK,
+ input PORT_R_RD_EN,
+ input [5:0] PORT_R_ADDR,
+ output [15:0] PORT_R_RD_DATA,
+);
+ parameter INIT = 1152'bx;
+ parameter PORT_W_CLK_POL = 1'b1;
+ parameter PORT_R_CLK_POL = 1'b1;
+
+ NX_RFB_M_WRAP #(
+ .mode(0),
+ .mem_ctxt(INIT),
+ .rck_edge(~PORT_R_CLK_POL),
+ .wck_edge(~PORT_W_CLK_POL)
+ ) _TECHMAP_REPLACE_ (
+ .RCK(PORT_R_CLK),
+ .WCK(PORT_W_CLK),
+ .I(PORT_W_WR_DATA),
+ .RA(PORT_R_ADDR),
+ .WA(PORT_W_ADDR),
+ .RE(PORT_R_RD_EN),
+ .WE(PORT_W_WR_EN),
+ .O(PORT_R_RD_DATA)
+ );
+endmodule
diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v
new file mode 100644
index 000000000..2f572650b
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_map_u.v
@@ -0,0 +1,345 @@
+
+module $__NX_RFB_U_DPREG_ (
+ input PORT_W_CLK,
+ input [6-1:0] PORT_W_ADDR,
+ input [6-1:0] PORT_R_ADDR,
+ input [36-1:0] PORT_W_WR_DATA,
+ input PORT_W_WR_EN,
+ output [36-1:0] PORT_R_RD_DATA
+);
+ parameter INIT = 1152'bx;
+ parameter PORT_W_CLK_POL = 1'b1;
+ parameter OPTION_MODE = 0;
+ parameter WIDTH = 18;
+ parameter BITS_USED = 0;
+ localparam BLOCK_NUM = OPTION_MODE == 2 ? 64 : 32;
+ localparam BLOCK_SIZE = OPTION_MODE == 3 ? 36 : 18;
+
+`include "rf_init.vh"
+
+ // mode 0 - DPREG
+ // mode 2 - NX_XRFB_64x18
+ // mode 3 - NX_XRFB_32x36
+ NX_RFB_U #(
+ .mode(OPTION_MODE),
+ .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, BLOCK_NUM, BLOCK_SIZE))),
+ .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(PORT_W_CLK),
+ .I1(PORT_W_WR_DATA[0]),
+ .I2(PORT_W_WR_DATA[1]),
+ .I3(PORT_W_WR_DATA[2]),
+ .I4(PORT_W_WR_DATA[3]),
+ .I5(PORT_W_WR_DATA[4]),
+ .I6(PORT_W_WR_DATA[5]),
+ .I7(PORT_W_WR_DATA[6]),
+ .I8(PORT_W_WR_DATA[7]),
+ .I9(PORT_W_WR_DATA[8]),
+ .I10(PORT_W_WR_DATA[9]),
+ .I11(PORT_W_WR_DATA[10]),
+ .I12(PORT_W_WR_DATA[11]),
+ .I13(PORT_W_WR_DATA[12]),
+ .I14(PORT_W_WR_DATA[13]),
+ .I15(PORT_W_WR_DATA[14]),
+ .I16(PORT_W_WR_DATA[15]),
+ .I17(PORT_W_WR_DATA[16]),
+ .I18(PORT_W_WR_DATA[17]),
+ .I19(PORT_W_WR_DATA[18]),
+ .I20(PORT_W_WR_DATA[19]),
+ .I21(PORT_W_WR_DATA[20]),
+ .I22(PORT_W_WR_DATA[21]),
+ .I23(PORT_W_WR_DATA[22]),
+ .I24(PORT_W_WR_DATA[23]),
+ .I25(PORT_W_WR_DATA[24]),
+ .I26(PORT_W_WR_DATA[25]),
+ .I27(PORT_W_WR_DATA[26]),
+ .I28(PORT_W_WR_DATA[27]),
+ .I29(PORT_W_WR_DATA[28]),
+ .I30(PORT_W_WR_DATA[29]),
+ .I31(PORT_W_WR_DATA[30]),
+ .I32(PORT_W_WR_DATA[31]),
+ .I33(PORT_W_WR_DATA[32]),
+ .I34(PORT_W_WR_DATA[33]),
+ .I35(PORT_W_WR_DATA[34]),
+ .I36(PORT_W_WR_DATA[35]),
+ .O1(PORT_R_RD_DATA[0]),
+ .O2(PORT_R_RD_DATA[1]),
+ .O3(PORT_R_RD_DATA[2]),
+ .O4(PORT_R_RD_DATA[3]),
+ .O5(PORT_R_RD_DATA[4]),
+ .O6(PORT_R_RD_DATA[5]),
+ .O7(PORT_R_RD_DATA[6]),
+ .O8(PORT_R_RD_DATA[7]),
+ .O9(PORT_R_RD_DATA[8]),
+ .O10(PORT_R_RD_DATA[9]),
+ .O11(PORT_R_RD_DATA[10]),
+ .O12(PORT_R_RD_DATA[11]),
+ .O13(PORT_R_RD_DATA[12]),
+ .O14(PORT_R_RD_DATA[13]),
+ .O15(PORT_R_RD_DATA[14]),
+ .O16(PORT_R_RD_DATA[15]),
+ .O17(PORT_R_RD_DATA[16]),
+ .O18(PORT_R_RD_DATA[17]),
+ .O19(PORT_R_RD_DATA[18]),
+ .O20(PORT_R_RD_DATA[19]),
+ .O21(PORT_R_RD_DATA[20]),
+ .O22(PORT_R_RD_DATA[21]),
+ .O23(PORT_R_RD_DATA[22]),
+ .O24(PORT_R_RD_DATA[23]),
+ .O25(PORT_R_RD_DATA[24]),
+ .O26(PORT_R_RD_DATA[25]),
+ .O27(PORT_R_RD_DATA[26]),
+ .O28(PORT_R_RD_DATA[27]),
+ .O29(PORT_R_RD_DATA[28]),
+ .O30(PORT_R_RD_DATA[29]),
+ .O31(PORT_R_RD_DATA[30]),
+ .O32(PORT_R_RD_DATA[31]),
+ .O33(PORT_R_RD_DATA[32]),
+ .O34(PORT_R_RD_DATA[33]),
+ .O35(PORT_R_RD_DATA[34]),
+ .O36(PORT_R_RD_DATA[35]),
+ .RA1(PORT_R_ADDR[0]),
+ .RA2(PORT_R_ADDR[1]),
+ .RA3(PORT_R_ADDR[2]),
+ .RA4(PORT_R_ADDR[3]),
+ .RA5(PORT_R_ADDR[4]),
+ .RA6(PORT_R_ADDR[5]),
+ .RA7(),
+ .RA8(),
+ .RA9(),
+ .RA10(),
+ .WA1(PORT_W_ADDR[0]),
+ .WA2(PORT_W_ADDR[1]),
+ .WA3(PORT_W_ADDR[2]),
+ .WA4(PORT_W_ADDR[3]),
+ .WA5(PORT_W_ADDR[4]),
+ .WA6(PORT_W_ADDR[5]),
+ .WE(PORT_W_WR_EN),
+ .WEA(1'b0)
+ );
+endmodule
+
+module $__NX_RFB_U_SPREG_ (
+ input PORT_RW_CLK,
+ input [4:0] PORT_RW_ADDR,
+ input [17:0] PORT_RW_WR_DATA,
+ input PORT_RW_WR_EN,
+ output [17:0] PORT_RW_RD_DATA
+);
+ parameter INIT = 576'bx;
+ parameter PORT_RW_CLK_POL = 1'b1;
+ parameter BITS_USED = 0;
+`include "rf_init.vh"
+
+ NX_RFB_U #(
+ .mode(1),
+ .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, 32, 18))),
+ .wck_edge(PORT_RW_CLK_POL == 1 ? 1'b0 : 1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(PORT_RW_CLK),
+ .I1(PORT_RW_WR_DATA[0]),
+ .I2(PORT_RW_WR_DATA[1]),
+ .I3(PORT_RW_WR_DATA[2]),
+ .I4(PORT_RW_WR_DATA[3]),
+ .I5(PORT_RW_WR_DATA[4]),
+ .I6(PORT_RW_WR_DATA[5]),
+ .I7(PORT_RW_WR_DATA[6]),
+ .I8(PORT_RW_WR_DATA[7]),
+ .I9(PORT_RW_WR_DATA[8]),
+ .I10(PORT_RW_WR_DATA[9]),
+ .I11(PORT_RW_WR_DATA[10]),
+ .I12(PORT_RW_WR_DATA[11]),
+ .I13(PORT_RW_WR_DATA[12]),
+ .I14(PORT_RW_WR_DATA[13]),
+ .I15(PORT_RW_WR_DATA[14]),
+ .I16(PORT_RW_WR_DATA[15]),
+ .I17(PORT_RW_WR_DATA[16]),
+ .I18(PORT_RW_WR_DATA[17]),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(PORT_RW_RD_DATA[0]),
+ .O2(PORT_RW_RD_DATA[1]),
+ .O3(PORT_RW_RD_DATA[2]),
+ .O4(PORT_RW_RD_DATA[3]),
+ .O5(PORT_RW_RD_DATA[4]),
+ .O6(PORT_RW_RD_DATA[5]),
+ .O7(PORT_RW_RD_DATA[6]),
+ .O8(PORT_RW_RD_DATA[7]),
+ .O9(PORT_RW_RD_DATA[8]),
+ .O10(PORT_RW_RD_DATA[9]),
+ .O11(PORT_RW_RD_DATA[10]),
+ .O12(PORT_RW_RD_DATA[11]),
+ .O13(PORT_RW_RD_DATA[12]),
+ .O14(PORT_RW_RD_DATA[13]),
+ .O15(PORT_RW_RD_DATA[14]),
+ .O16(PORT_RW_RD_DATA[15]),
+ .O17(PORT_RW_RD_DATA[16]),
+ .O18(PORT_RW_RD_DATA[17]),
+ .O19(),
+ .O20(),
+ .O21(),
+ .O22(),
+ .O23(),
+ .O24(),
+ .O25(),
+ .O26(),
+ .O27(),
+ .O28(),
+ .O29(),
+ .O30(),
+ .O31(),
+ .O32(),
+ .O33(),
+ .O34(),
+ .O35(),
+ .O36(),
+ .RA1(),
+ .RA2(),
+ .RA3(),
+ .RA4(),
+ .RA5(),
+ .RA6(),
+ .RA7(),
+ .RA8(),
+ .RA9(),
+ .RA10(),
+ .WA1(PORT_RW_ADDR[0]),
+ .WA2(PORT_RW_ADDR[1]),
+ .WA3(PORT_RW_ADDR[2]),
+ .WA4(PORT_RW_ADDR[3]),
+ .WA5(PORT_RW_ADDR[4]),
+ .WA6(),
+ .WE(PORT_RW_WR_EN),
+ .WEA(1'b0)
+ );
+endmodule
+
+module $__NX_XRFB_2R_1W_ (
+ input PORT_W_CLK,
+ input [4:0] PORT_W_ADDR,
+ input [4:0] PORT_A_ADDR,
+ input [4:0] PORT_B_ADDR,
+ input [17:0] PORT_W_WR_DATA,
+ input PORT_W_WR_EN,
+ output [17:0] PORT_A_RD_DATA,
+ output [17:0] PORT_B_RD_DATA
+);
+ parameter INIT = 576'bx;
+ parameter PORT_W_CLK_POL = 1'b1;
+ parameter BITS_USED = 0;
+`include "rf_init.vh"
+
+ NX_RFB_U #(
+ .mode(4),
+ .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, 32, 18))),
+ .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)
+ ) _TECHMAP_REPLACE_ (
+ .WCK(PORT_W_CLK),
+ .I1(PORT_W_WR_DATA[0]),
+ .I2(PORT_W_WR_DATA[1]),
+ .I3(PORT_W_WR_DATA[2]),
+ .I4(PORT_W_WR_DATA[3]),
+ .I5(PORT_W_WR_DATA[4]),
+ .I6(PORT_W_WR_DATA[5]),
+ .I7(PORT_W_WR_DATA[6]),
+ .I8(PORT_W_WR_DATA[7]),
+ .I9(PORT_W_WR_DATA[8]),
+ .I10(PORT_W_WR_DATA[9]),
+ .I11(PORT_W_WR_DATA[10]),
+ .I12(PORT_W_WR_DATA[11]),
+ .I13(PORT_W_WR_DATA[12]),
+ .I14(PORT_W_WR_DATA[13]),
+ .I15(PORT_W_WR_DATA[14]),
+ .I16(PORT_W_WR_DATA[15]),
+ .I17(PORT_W_WR_DATA[16]),
+ .I18(PORT_W_WR_DATA[17]),
+ .I19(),
+ .I20(),
+ .I21(),
+ .I22(),
+ .I23(),
+ .I24(),
+ .I25(),
+ .I26(),
+ .I27(),
+ .I28(),
+ .I29(),
+ .I30(),
+ .I31(),
+ .I32(),
+ .I33(),
+ .I34(),
+ .I35(),
+ .I36(),
+ .O1(PORT_A_RD_DATA[0]),
+ .O2(PORT_A_RD_DATA[1]),
+ .O3(PORT_A_RD_DATA[2]),
+ .O4(PORT_A_RD_DATA[3]),
+ .O5(PORT_A_RD_DATA[4]),
+ .O6(PORT_A_RD_DATA[5]),
+ .O7(PORT_A_RD_DATA[6]),
+ .O8(PORT_A_RD_DATA[7]),
+ .O9(PORT_A_RD_DATA[8]),
+ .O10(PORT_A_RD_DATA[9]),
+ .O11(PORT_A_RD_DATA[10]),
+ .O12(PORT_A_RD_DATA[11]),
+ .O13(PORT_A_RD_DATA[12]),
+ .O14(PORT_A_RD_DATA[13]),
+ .O15(PORT_A_RD_DATA[14]),
+ .O16(PORT_A_RD_DATA[15]),
+ .O17(PORT_A_RD_DATA[16]),
+ .O18(PORT_A_RD_DATA[17]),
+ .O19(PORT_B_RD_DATA[0]),
+ .O20(PORT_B_RD_DATA[1]),
+ .O21(PORT_B_RD_DATA[2]),
+ .O22(PORT_B_RD_DATA[3]),
+ .O23(PORT_B_RD_DATA[4]),
+ .O24(PORT_B_RD_DATA[5]),
+ .O25(PORT_B_RD_DATA[6]),
+ .O26(PORT_B_RD_DATA[7]),
+ .O27(PORT_B_RD_DATA[8]),
+ .O28(PORT_B_RD_DATA[9]),
+ .O29(PORT_B_RD_DATA[10]),
+ .O30(PORT_B_RD_DATA[11]),
+ .O31(PORT_B_RD_DATA[12]),
+ .O32(PORT_B_RD_DATA[13]),
+ .O33(PORT_B_RD_DATA[14]),
+ .O34(PORT_B_RD_DATA[15]),
+ .O35(PORT_B_RD_DATA[16]),
+ .O36(PORT_B_RD_DATA[17]),
+ .RA1(PORT_A_ADDR[0]),
+ .RA2(PORT_A_ADDR[1]),
+ .RA3(PORT_A_ADDR[2]),
+ .RA4(PORT_A_ADDR[3]),
+ .RA5(PORT_A_ADDR[4]),
+ .RA6(PORT_B_ADDR[0]),
+ .RA7(PORT_B_ADDR[1]),
+ .RA8(PORT_B_ADDR[2]),
+ .RA9(PORT_B_ADDR[3]),
+ .RA10(PORT_B_ADDR[4]),
+ .WA1(PORT_W_ADDR[0]),
+ .WA2(PORT_W_ADDR[1]),
+ .WA3(PORT_W_ADDR[2]),
+ .WA4(PORT_W_ADDR[3]),
+ .WA5(PORT_W_ADDR[4]),
+ .WA6(),
+ .WE(PORT_W_WR_EN),
+ .WEA(1'b0)
+ );
+endmodule
\ No newline at end of file
diff --git a/techlibs/nanoxplore/rf_rams_u.txt b/techlibs/nanoxplore/rf_rams_u.txt
new file mode 100644
index 000000000..94e002eeb
--- /dev/null
+++ b/techlibs/nanoxplore/rf_rams_u.txt
@@ -0,0 +1,66 @@
+# Register-File RAMs for NanoXplore NG-ULTRA
+
+# Dual-port RAMs.
+# NX_RFB_U in mode 0 (DPREG)
+# NX_RFB_U in mode 2 (NX_XRFB_64x18)
+# NX_RFB_U in mode 3 (NX_XRFB_32x36)
+
+ram distributed $__NX_RFB_U_DPREG_ {
+ option "MODE" 0 {
+ cost 30;
+ widthscale 30;
+ abits 5;
+ widths 18 global;
+ }
+ option "MODE" 2 {
+ cost 50;
+ widthscale 30;
+ abits 6;
+ widths 18 global;
+ }
+ option "MODE" 3 {
+ cost 50;
+ widthscale 30;
+ abits 5;
+ widths 36 global;
+ }
+ init no_undef;
+
+ port sw "W" {
+ clock anyedge;
+ }
+ port ar "R" {
+ }
+}
+
+# Single-port RAMs.
+# NX_RFB_U in mode 1 (SPREG)
+
+ram distributed $__NX_RFB_U_SPREG_ {
+ cost 30;
+ widthscale;
+ abits 5;
+ width 18;
+ init no_undef;
+ port arsw "RW" {
+ clock anyedge;
+ }
+}
+
+# Single write dual read RAMs.
+# NX_RFB_U in mode 4 (NX_XRFB_2R_1W)
+
+ram distributed $__NX_XRFB_2R_1W_ {
+ cost 40;
+ widthscale 30;
+ abits 5;
+ width 18;
+ init no_undef;
+ port sw "W" {
+ clock anyedge;
+ }
+ port ar "A" {
+ }
+ port ar "B" {
+ }
+}
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
new file mode 100644
index 000000000..4674559fb
--- /dev/null
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -0,0 +1,370 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2024 Hannah Ravensloft
+ * Copyright (C) 2024 Miodrag Milanovic
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthNanoXplorePass : public ScriptPass
+{
+ SynthNanoXplorePass() : ScriptPass("synth_nanoxplore", "synthesis for NanoXplore FPGAs") { }
+
+ void on_register() override
+ {
+ RTLIL::constpad["synth_nanoxplore.abc9.W"] = "300";
+ }
+
+ void help() override
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth_nanoxplore [options]\n");
+ log("\n");
+ log("This command runs synthesis for NanoXplore FPGAs.\n");
+ log("\n");
+ log(" -top \n");
+ log(" use the specified module as top module\n");
+ log("\n");
+ log(" -family \n");
+ log(" run synthesis for the specified NanoXplore architecture\n");
+ log(" generate the synthesis netlist for the specified family.\n");
+ log(" supported values:\n");
+ log(" - medium: NG-Medium\n");
+ log(" - large: NG-Large\n");
+ log(" - ultra: NG-Ultra\n");
+ log("\n");
+ log(" -json \n");
+ log(" write the design to the specified JSON file. writing of an output file\n");
+ log(" is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -run :\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
+ log("\n");
+ log(" -abc9\n");
+ log(" use new ABC9 flow (EXPERIMENTAL)\n");
+ log("\n");
+ log(" -nocy\n");
+ log(" do not map adders to CY cells\n");
+ log("\n");
+ log(" -nodffe\n");
+ log(" do not use flipflops with L in output netlist\n");
+ log("\n");
+ log(" -min_ce_use \n");
+ log(" do not use flip-flops with load signal if the resulting count is less\n");
+ log(" than min_ce_use in output netlist\n");
+ log("\n");
+ log(" -min_srst_use \n");
+ log(" do not use flip-flops with async reset signal if the resulting count is less\n");
+ log(" than min_srst_use in output netlist\n");
+ log("\n");
+ log(" -norfram\n");
+ log(" do not use Register File RAM cells in output netlist\n");
+ log("\n");
+ log(" -nobram\n");
+ log(" do not use block NX_RAM cells in output netlist\n");
+ log("\n");
+ log(" -noiopad\n");
+ log(" do not insert IO buffers\n");
+ log("\n");
+ log(" -no-rw-check\n");
+ log(" marks all recognized read ports as \"return don't-care value on\n");
+ log(" read/write collision\" (same result as setting the no_rw_check\n");
+ log(" attribute on all memories).\n");
+ log("\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ help_script();
+ log("\n");
+ }
+
+ string top_opt, json_file, family;
+ bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check;
+ std::string postfix;
+ int min_ce_use, min_srst_use;
+
+ void clear_flags() override
+ {
+ top_opt = "-auto-top";
+ json_file = "";
+ family = "";
+ flatten = true;
+ abc9 = false;
+ nocy = false;
+ nodffe = false;
+ norfram = false;
+ nobram = false;
+ noiopad = false;
+ no_rw_check = false;
+ postfix = "";
+ min_ce_use = 8;
+ min_srst_use = 8;
+ }
+
+ void execute(std::vector args, RTLIL::Design *design) override
+ {
+ string run_from, run_to;
+ clear_flags();
+
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++)
+ {
+ if (args[argidx] == "-top" && argidx+1 < args.size()) {
+ top_opt = "-top " + args[++argidx];
+ continue;
+ }
+ if ((args[argidx] == "-family" || args[argidx] == "-arch") && argidx+1 < args.size()) {
+ family = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-json" && argidx+1 < args.size()) {
+ json_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx+1 < args.size()) {
+ size_t pos = args[argidx+1].find(':');
+ if (pos == std::string::npos)
+ break;
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos+1);
+ continue;
+ }
+ if (args[argidx] == "-flatten") {
+ flatten = true;
+ continue;
+ }
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
+ continue;
+ }
+ if (args[argidx] == "-abc9") {
+ abc9 = true;
+ continue;
+ }
+ if (args[argidx] == "-nocy") {
+ nocy = true;
+ continue;
+ }
+ if (args[argidx] == "-nodffe") {
+ nodffe = true;
+ continue;
+ }
+ if (args[argidx] == "-min_ce_use" && argidx+1 < args.size()) {
+ min_ce_use = atoi(args[++argidx].c_str());
+ continue;
+ }
+ if (args[argidx] == "-min_srst_use" && argidx+1 < args.size()) {
+ min_srst_use = atoi(args[++argidx].c_str());
+ continue;
+ }
+ if (args[argidx] == "-norfram") {
+ norfram = true;
+ continue;
+ }
+ if (args[argidx] == "-nobram") {
+ nobram = true;
+ continue;
+ }
+ if (args[argidx] == "-iopad") {
+ noiopad = false;
+ continue;
+ }
+ if (args[argidx] == "-noiopad") {
+ noiopad = true;
+ continue;
+ }
+ if (args[argidx] == "-no-rw-check") {
+ no_rw_check = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
+
+ if (family.empty()) {
+ //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
+ family = "ultra";
+ }
+
+ if (family == "ultra") {
+ postfix = "_u";
+ } else if (family == "medium") {
+ postfix = "_m";
+ } else if (family == "large") {
+ postfix = "_l";
+ } else
+ log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str());
+
+ if (!design->full_selection())
+ log_cmd_error("This command only operates on fully selected designs!\n");
+
+ log_header(design, "Executing SYNTH_NANOXPLORE pass.\n");
+ log_push();
+
+ run_script(design, run_from, run_to);
+
+ log_pop();
+ }
+
+ void script() override
+ {
+ std::string no_rw_check_opt = "";
+ if (no_rw_check)
+ no_rw_check_opt = " -no-rw-check";
+ if (help_mode)
+ no_rw_check_opt = " [-no-rw-check]";
+
+ if (check_label("begin"))
+ {
+ run("read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim" + postfix + ".v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb" + postfix + ".v");
+ run("techmap -map +/nanoxplore/cells_wrap.v");
+ run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str()));
+ }
+
+ if (check_label("coarse"))
+ {
+ run("proc");
+ if (flatten || help_mode)
+ run("flatten", "(skip if -noflatten)");
+ run("tribuf -logic");
+ run("deminout");
+ run("opt_expr");
+ run("opt_clean");
+ run("check");
+ run("opt -nodffe -nosdff");
+ run("fsm");
+ run("opt");
+ run("wreduce");
+ run("peepopt");
+ run("opt_clean");
+ run("share");
+ run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+ run("opt_expr");
+ run("opt_clean");
+ run("alumacc");
+ run("opt");
+ run("memory -nomap" + no_rw_check_opt);
+ run("opt_clean");
+ }
+
+ if (check_label("map_ram"))
+ {
+ std::string args = "";
+ if (family == "medium")
+ args += " -D IS_NG_MEDIUM";
+ if (nobram)
+ args += " -no-auto-block";
+ if (norfram)
+ args += " -no-auto-distributed";
+ if (help_mode)
+ args += " [-no-auto-block] [-no-auto-distributed]";
+ run("memory_libmap -lib +/nanoxplore/rf_rams"+ postfix + ".txt -lib +/nanoxplore/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -norfram)");
+ run("techmap -map +/nanoxplore/rf_rams_map"+ postfix + ".v -map +/nanoxplore/brams_map.v");
+ run("techmap -map +/nanoxplore/cells_wrap.v t:NX_RAM*");
+ run("techmap -map +/nanoxplore/cells_wrap" + postfix + ".v t:NX_XRFB* t:NX_RFB*");
+ }
+
+ if (check_label("map_ffram"))
+ {
+ run("opt -fast -mux_undef -undriven -fine");
+ run("memory_map");
+ run("opt -undriven -fine -mux_undef");
+ }
+
+ if (check_label("map_gates"))
+ {
+ if (nocy)
+ run("techmap");
+ else {
+ run("techmap -map +/techmap.v -map +/nanoxplore/arith_map.v");
+ run("nx_carry");
+ }
+ if (help_mode || !noiopad) {
+ run("iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top", "(skip if '-noiopad')");
+ run("techmap -map +/nanoxplore/io_map.v");
+ }
+ run("opt -fast");
+ }
+
+ if (check_label("map_ffs"))
+ {
+ std::string dfflegalize_args = " -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r";
+ if (help_mode) {
+ dfflegalize_args += " [-cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r]";
+ } else if (!nodffe) {
+ dfflegalize_args += " -cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r";
+ }
+ dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use);
+ run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
+ run("opt_merge");
+ run("techmap -map +/nanoxplore/latches_map.v");
+ run("techmap -map +/nanoxplore/cells_map.v");
+ run("opt_expr -undriven -mux_undef");
+ run("clean -purge");
+ }
+
+ if (check_label("map_luts"))
+ {
+ if (abc9) {
+ std::string abc9_opts = " -maxlut 4";
+ std::string k = "synth_nanoxplore.abc9.W";
+ if (active_design && active_design->scratchpad.count(k))
+ abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
+ else
+ abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
+ run("abc9" + abc9_opts);
+ } else {
+ std::string abc_args = " -dress";
+ abc_args += " -lut 4";
+ run("abc" + abc_args);
+ }
+ run("techmap -map +/nanoxplore/cells_map.v t:$lut");
+ run("opt -fast");
+ run("clean");
+ }
+
+ if (check_label("check"))
+ {
+ run("autoname");
+ run("hierarchy -check");
+ run("stat");
+ run("check -noinit");
+ run("blackbox =A:whitebox");
+ run("setundef -zero -undriven");
+ }
+
+ if (check_label("json"))
+ {
+ if (!json_file.empty() || help_mode)
+ run(stringf("write_json %s", help_mode ? "" : json_file.c_str()));
+ }
+ }
+} SynthNanoXplorePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/tests/arch/nanoxplore/.gitignore b/tests/arch/nanoxplore/.gitignore
new file mode 100644
index 000000000..1d329c933
--- /dev/null
+++ b/tests/arch/nanoxplore/.gitignore
@@ -0,0 +1,2 @@
+*.log
+/run-test.mk
diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys
new file mode 100644
index 000000000..9356944c8
--- /dev/null
+++ b/tests/arch/nanoxplore/add_sub.ys
@@ -0,0 +1,71 @@
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -run :prove -map +/nanoxplore/cells_sim.v -map +/nanoxplore/cells_sim_u.v synth_nanoxplore -noiopad
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 2 t:NX_CY
+select -assert-count 4 t:NX_LUT
+select -assert-none t:NX_CY t:NX_LUT %% t:* %D
+
+design -reset
+read_verilog <