mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00
Code Activity

Renamed "stdcells.v" to "techmap.v"

Browse source
This commit is contained in:
Clifford Wolf 2014-07-31 02:32:00 +02:00
parent 6ca0c569d9
commit 1202f7aa4b
9 changed files with 15 additions and 12 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/common/simcells.v
View file

@ -21,7 +21,7 @@
*
* This verilog library contains simple simulation models for the internal
* logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
* mapper (see "techmap.v" in this directory) and expected by the "abc" pass.
*
*/