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Renamed "stdcells.v" to "techmap.v"

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This commit is contained in:
Clifford Wolf 2014-07-31 02:32:00 +02:00
parent 6ca0c569d9
commit 1202f7aa4b
9 changed files with 15 additions and 12 deletions
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2
passes/techmap/.gitignore vendored
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@ -1 +1 @@
stdcells.inc
techmap.inc

6
passes/techmap/Makefile.inc
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@ -10,16 +10,16 @@ OBJS += passes/techmap/hilomap.o
OBJS += passes/techmap/extract.o
endif
GENFILES += passes/techmap/stdcells.inc
GENFILES += passes/techmap/techmap.inc
passes/techmap/stdcells.inc: techlibs/common/stdcells.v
passes/techmap/techmap.inc: techlibs/common/techmap.v
$(P) echo "// autogenerated from $<" > $@.new
$(Q) echo "static char stdcells_code[] = {" >> $@.new
$(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
$(Q) echo "0};" >> $@.new
$(Q) mv $@.new $@
passes/techmap/techmap.o: passes/techmap/stdcells.inc
passes/techmap/techmap.o: passes/techmap/techmap.inc
TARGETS += yosys-filterlib
GENFILES += passes/techmap/filterlib.o

4
passes/techmap/techmap.cc
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@ -26,7 +26,7 @@
#include <stdio.h>
#include <string.h>
#include "passes/techmap/stdcells.inc"
#include "passes/techmap/techmap.inc"
// see simplemap.cc
extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
@ -790,7 +790,7 @@ struct TechmapPass : public Pass {
RTLIL::Design *map = new RTLIL::Design;
if (map_files.empty()) {
FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
Frontend::frontend_call(map, f, "<techmap.v>", verilog_frontend);
fclose(f);
} else
for (auto &fn : map_files)