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Renamed "stdcells.v" to "techmap.v"

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Clifford Wolf 2014-07-31 02:32:00 +02:00
parent 6ca0c569d9
commit 1202f7aa4b
9 changed files with 15 additions and 12 deletions
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manual/CHAPTER_Techmap.tex
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@ -27,7 +27,7 @@ cells with the provided implementation.
When no map file is provided, {\tt techmap} uses a built-in map file that
maps the Yosys RTL cell types to the internal gate library used by Yosys.
The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in
The curious reader may find this map file as {\tt techlibs/common/techmap.v} in
the Yosys source tree.
Additional features have been added to {\tt techmap} to allow for conditional